BIOS Tutorial and codes

8/10/2019 BIOS Tutorial and codes

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BIOS Tutorial

Definitions

BIOS

CMOS Chipset

Setup

BIOS

Basic Input Output System. All computer hardware has to work with softwarethrough an interface. The BIOS gives the computer a little builtin starter kit torun the rest of softwares from flopp! disks "#$$% and hard disks "&$$%. TheBIOS is responsible for booting the computer b! providing a basic set oinstructions. It performs all the tasks that need to be done at startup time' (OST"(owerOn Self Test) booting an operating s!stem from #$$ or &$$%#urthermore) it provides an interface to the underl!ing hardware for the operatings!stem in the form of a librar! of interrupt handlers. #or instance) each time a ke!is pressed) the C(* "Central (rocessing *nit% perform an interrupt to read thatke!. This is similar for other input+output devices "Serial and parallel ports) videocards) sound cards) hard disk controllers) etc...%. Some older (C,s cannot co

operate with all the modern hardware because their BIOS doesn,t support thathardware. The operating s!stem cannot call a BIOS routine to use it- this problemcan be solved b! replacing !our BIOS with an newer one) that does support !ournew hardware) or b! installing a device driver for the hardware.

CMOS

Complementary Metal Oxide Semiconductor. To perform its tasks) the BIOS

need to know various parameters "hardware configuration%. These arepermanentl! saved in a little piece "/ b!tes% of CMOS 0AM "short' CMOS%The CMOS power is supplied b! a little batter!) so its contents will not be lostafter the (C is turned off. Therefore) there is a batter! and a small 0AM memor!on board) which never "should...% loses its information. The memor! was inearlier times a part of the clock chip) now it,s part of such a highl! IntegratedCircuit "IC%. CMOS is the name of a technolog! which needs ver! low power sothe computer,s batter! is not too much in use.


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Actuall!) there is not a batter! on new boards) but an accumulator "1i2Cad inmost cases%. It is recharged ever! time the computer is turned on. If !our CMOSis powered b! e3ternal batteries) be sure that the! are in good operating conditionAlso) be sure that the! do not leak. That ma! damage the motherboardOtherwise) !our CMOS ma! suddenl! 4forget4 its configuration and !ou ma! belooking for a problem elsewhere. In the monolithic (C and (C+5T) this

information is supplied b! setting the $I( "$ualInline (ackage% switches at themotherboard or peripheral cards. Some new motherboards have a technolog!named the $allas 1ov0am. It eliminates having an onboard batter!' There is a67 !ear lithium cell epo3!ed into the chip.

Chipset

A (C consists of different functional parts installed on its motherboard' ISA

"Industr! Standard Architecture%) 8ISA "8nhanced Industr! StandardArchitecture% 98SA "9ideo 8nhanced Standards Association% and (CI"(eripheral Component Interface% slots) memor!) cache memor!) ke!board plugetc... 1ot all of these are present on ever! motherboard. The chipset enables a setof instructions so the C(* can work "communicate% with other parts of themotherboard. 1owada!s most of the discrete chips- (IC "(rogrammable InterrupController%) $MA "$irect Memor! Access%) MM* "Memor! Management *nit%cache) etc... are packed together on one) two or three chips- the chipset. Since

chipsets of a different brand are not the same) for ever! chipset there is a BIOSversion. 1ow we have fewer and fewer chipsets which do the :ob. Some chipsetshave more features) some less. O(Ti is such a commonl! used chipset. In somewell integrated motherboards) the onl! components present are the C(*) the twoBIOS chips "BIOS and ;e!board BIOS%) one chipset IC) cache memor!"$0AMs) $!namic 0andom Access Memor!%) memor! "SIMMs) Single InlineMemor! Module) most of the time% and a clock chip.

Setup

Setup is the set of procedures enabling the configure a computer according to itshardware caracteristics. It allows !ou to change the parameters with which theBIOS configures !our chipset. The original IBM (C was configured b! means of$I( switches buried on the motherboard. Setting (C and 5T $I( switches

properl! was something of an arcane art. $I( switches+:umpers are still used formemor! configuration and clock speed selection.


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configuration information. CMOS was originall! set b! a program on the$iagnostic $isk) however later clones incorporated routines in the BIOS whichallowed the CMOS to be "re%configured if certain magic ke!strokes were used.

*nfortunatel! as the chipsets controlling modern C(*s have become morecomple3) the variet! of parameters specifiable in S8T*( has grown. Moreover

there has been little standardi=ation of terminolog! between the half do=en BIOSvendors) three do=en chipset makers and large number of motherboard vendorsComplaints about poor motherboard documentation of S8T*( parameters arever! common.

To e3acerbate matters) some parameters are defined b! BIOS vendors) othersb!chipset designers) others b! motherboard designers) and others b! variouscombinations of the above. (arameters intended for use in $esign and$evelopment) are intermi3ed with parameters intended to be ad:usted b!

technicians who are fre>uentl! :ust as baffled b! this stuff as ever!one else is1o one person or organi=ation seems to understand all the parameters availablefor an! given S8T*(.

Hardware Performance

S!stem Timing

The ?ear @77 problem

The Motherboard

The Central (rocessor

Although computers ma! have basic similarities "the! all look the same on ashelf%) performance will differ markedl! between them) :ust the same as it does

with cars. The (C contains several processes running at the same time) often atdifferent speeds) so a fair amount of coordination is re>uired to ensure that the!don,t work against each other.

Most performance problems arise from bottlenecsbetween components that arenot necessaril! the best for a particular :ob) but a result of compromise between

price and performance. *suall!) price wins out and !ou have to work around theproblems this creates.


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The trick to getting the most out of an! machine is to make sure that eachcomponent is giving of its best) then eliminate potential bottlenecks betweenthem. ?ou can get a bottleneck simpl! b! having an old piece of e>uipment that isnot designed to work at modern high speed a computer is only as fast as itsslowest component) but bottlenecks can also be due to badl! written software.

System Timin!

The clock is responsible for the speed at which numbers are crunched andinstructions e3ecuted. It results in an electrical signal that switches constantl!

between high and low voltage several millions times a second.

The System Cloc) or C;I1) is the fre>uenc! used b! the processor- on @sand s) this will be half the speed of the main cr!stal on the motherboard "theC(* devides it b! two%) which is often called C;@I1. / processors run at thesame speed) because the! use both edges of the timing signal. A clock generatorchip "@@/ or similar% is used to s!nchroni=e timing signals around thecomputer) and the data bus would be run at slower speed s!nchronousl! with theC(*) e.g. C;I1+/ for an ISA bus with a M&= C(*.

ATC; is a separate clock for the bus) when it,s run as!nchronousl!) or notderived from C;@I1. There is also a 6/.6 M&= cr!stal which was used for als!stem timing on 5Ts. 1ow it,s onl! used for the colour fre>uenc! of the video

controller "/D%.

The "ear #$$$ problem

As far as the (C hardware is concerned) the problem lies with the Real TimeClock) or 0TC) and its relation to the internal $OS clock device driver"COC;E%) which is actuall! a counter and not a real clock at all. ?ou can verif!if !our s!stem has this problem b! setting the date :ust before midnight 6FFF andleaving the machine running to see what happen when it reaches @777. $OScopes with the problem >uite easil!. &owever) if !ou turn the power off andreboot) !ou might see a s!stem date starting somewhere in 6F7 "do not log on tothe network) if it is the case) otherwise !ou might get the server time%. The date76+76+6F7 is usuall! set if !our CMOS contents are lost) and 76+7/+6F7 if anoutofrange date is encountered.

The reason for this discrepanc! is the interaction between the two clocksmentioned above. The 0TC lives inside the CMOS chip that keeps the BIOS


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settings and is kept alive b! the batter!. Some of these cannot keep track of thecenturies b! themselves) so a b!te is used in the CMOS to do the :ob insteadAlso) the! are trimmed at the factor! to a certain tolerance) t!picall! plus orminus @7 seconds a month) which will onl! be kept to if the desired operatingenvironment is kept "temprerature) humidit!) etc.%.

The $OS device driver "COC;E%) on the other hand) onl! interrogates the 0TC"via the BIOS% when the machine starts) then proceeds to ignore it as long as the(C is running. This is to save going as far as the 0TC for the time) which is aslower process. The date supplied is converted to the number of da!s sinceGanuar! 6st 6F7) and the number of seconds since midnight of the current da!The latter is stored in the counter b! the BIOS) and when $OS needs to read theclock) the BIOS is called to read the counter and the number of ticks is converted

back to seconds. If the counter goes past midnight) it is reset to =ero b! the BIOSand the first caller after that is told that the da! has advanced. As a result) if morethant @/ hours has elapsed between calls) there is no wa! that $OS can tell whichda! it is.

This is wh! there is often a time difference between !our watch and !our (C atthe end of the da!- the s!stem clock has to compete for attention with otherdevices) and is often reprogrammed b! games) etc) who use it for their owntiming purposes) mostl! to do with running the video faster. In short) beinginterrupt dri%en) its accurac! depends on s!stem activit!.

As $OS operates between 6F7 and @7FF) it can figure out that 77 e>uates to@777) although it ma! have problems if the 0TC specificall! hands it a date of6F77) or an! other incompatible date. In practice) the BIOS converts it as well-some correct the time automaticall! at boot and some will suppl! $OS with @777instead of a hardware date of 6F77. Others cannot produce a date later than 6FFFan!wa!- Award BIOS /.DH prior to 1ovember 6FFD can onl! accept dates

between 6FF/ and 6FFF. A good wa! to solve the @777 problem "for the BIOSaspect of it at least% is the chan!e your motherboard. &ave a look a

[email protected] www.sbhs.com/y2k.

The Motherboard

This is a large circuit board to which are fi3ed the Central Processor"C(*%) thedata bus) memor! and various support chips) such as those that control speed andtiming the ke!board) etc. The C(* does all the thinking) and is told what to do b!instructions contained in memor!) so there will be a direct twowa! connection
http://www.year2000.com/http://www.sbhs.com/y2khttp://www.year2000.com/http://www.sbhs.com/y2k


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between them. The data bus is actuall! a part of the C(*) although it,s treatedseparatel!.

83tra circuitr! in the form of expansion cardsis placed into expansion slotsonthe data bus) so the basic setup of the computer can be changed easil! "fore3ample) !ou can connect more disk drives or a modem there%.

A math coprocessor is fre>uentl! fitted alongside the main processor) which isspeciall! built to cope with noninteger arithmetic "e.g. decimal points%. The main

processor has to convert decimals and fractions to whole numbers beforecalculating them) and then has to convert them back again.

The Central Processor

The chip that was the brains of the original IBM (C was called the 7

manufactured b! Intel. In the da!s Intel developed the 7) microprocessorswere classified b! their e3ternal databus. Intel has thus officiall! classified their7 as an bit &MOS microprocessor. Although it was internall! classified as

being 6bit) it spoke to the data bus and memor! with bits in order to keep thecosts down and keep in line with the capabilities of the support chips. Then whenit wanted to send two characters to the screen over the data bus) it had to sendthem one at a time) rather than both together) so there was an idle state wherenothing was done ever! time the data was sent.

In addition) it could onl! talk to 6 Mb of memor! at an! time- there were @7ph!sical connections between it and the C(*. On a binar! s!stem this represents@@7) or 6)7/)D.

The &$#&'

The 7@ was introduced in response to competition from manufacturers whowere cloning the IMB (C. The connections between the various parts of themotherboard became 6bit throughout) thus increasing efficienc! / times. It also

has @/ memor! address lines) so it could talk to 6Mb of ph!sical memor!&owever) $OS could not use it since it had to be addressed in protected mode$OS can onl! run in real mode) which is restricted to the 6 Mb that can be seen

b! the 7. Therefore) a (entium running $OS is :ust a fast 5T. Gust as the7) the 7@ C(* is limitted to 6MB "J /;B% when running in real modeThe 7@ C(* has to run in protected mode to access e3tended memor!. On a7@ s!stem) $OS, e3tended memor! manager "himem.s!s% uses BIOS service


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I1T 6Dh+A&Kh to move data from+to e3tended memor!. I1T 6Dh enters andleaves protected mode.

The &$(&'

Compa> was the first compan! to use the 7 "the $5 version) as opposed tothe S5see below%) which uses @ bits between itself and memor!) but 6 towards

the data bus) which has not reall! been developed in tandem wit the rest of themachine. This is partl! to ensure backwards compatibilit! and partl! due to the

plumbing arrangements of running a fast C(* with faster memor! and a slow bus" M&=%.

The can run multiple copies of real mode "that is) it can create several virtual7s%. It uses paging to remap memor! so that these machines are brought to theattention of the C(* when the programs in them re>uire it- this is done on atimeslice basis) around 7 times a second) which is how we get multitasking in


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The &$(&'S)

The 7S3 is a @bit chip internall!) but 6bit e3ternall! to both memor! andthe data bus) so !ou get bottlenecking. It is a cutdown version of the 7$5)created to both cut costs and give the impression the @ was obsolete "true%)

because at the time other manufacturers could make the @ under license

Although it can run specific software) it looks like a @ to the machine it isin) so e3isting @ motherboards could be used to plug in S5 C(*s. At thesame clock speed) a S5 is around @DN slower than a $5.

The &$*&'

To nontechnical people) the 7/ is a fast 7$5 with an onboard math coprocessor and ; of cache memor!. It is not reall! a newer technolog! as such"onl! second generation%) but better use is made of its facilities. #or e3ample) ittakes fewer instruction c!cles to do the same :ob) and is optimi=ed to keep asman! operations inside the chip as possible. The prefetch unit was replaced

b! ; of S0AM cache) and pipelining was replaced b! burst mode) which workson the theor! that most of the time spent getting data concerns its address. Burstallows a device to send large amounts of data in a short time without interruption(ipelining on the re>uires @ clocks per transfer- onl! one is needed with /Burst Mode. Memor! parit! checks also take their own path at the same time asthe data the! relate to. The / has an onboard clock) and both edges of thes>uare wave signal are used to calculate the clock signal) so the motherboard runs

at the same speed as the C(*. In addition) the bus s!stem uses a single pulsec!cle. Henerall! speaking) at the same clock speed) a / will deliver between @ times the performance of a .

The &$*&'S)

The /S5 is as above) but with the math coprocessor facilit! disabledtherefore !ou should find no significant difference between it and a - a +/7is broadl! e>uivalent to a /+@D.

Cloc Doublin!

The $5+4 chip runs at double speed of the original) but it is not the same ashaving a proper high speed motherboard because the bus will still be running atthe normal speed. *nfortunatel!) high speed motherboards are more e3pensive

because of having to design out 0# emissions) and the like.


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Actual performance depends on how man! accesses are satisfied from the chip,scache) which is how the C(* is kept bus!) rather than waiting for the rest of themachine. If the C(* has to go outside the cache) effective speed is the same asthe motherboard or) more properl!) the relevant bus "memor! or data%) so best

performance is obtained when all the C(*,s needs are satisfied from inside itself&owever) performance is still good if it has to use cache) as the hit rate is around

F7N. The $5/ has a larger cache "6;% to cope with the higher speed.

The Pentium

8ssentiall! two /s in parallel "or rather an S5 and a $5%) so more instructionsare processed at the same time- t!picall! two at once. This) however) depends onwhether software can take advantage of it) and get the timing of the binar! code

:ust right. It has separate ; caches) for instructions and data) split into bankswhich can be accessed alternatel!. It has a /bit bus) to cope with @ @bit chips.

The Pentium Pro

This is a 0ISC chip with a / hardware emulator on it) running at @77 M&= ofbelow. Several techni>ues are used b! this chip to produce more performancethan its predecessors- speed is achieved b! dividing processing into more stagesand more work is done within each clock c!cle- three instructions can be decodedin each one) as opposed to two for the (entium.

In additions) instruction decoding and e3ecution are decoupled) which means tha

instructions can still be e3ecuted if one pipeline stops "such as when oneinstruction is waiting for data from memor!- the (entium would stop al

processing at this point%. Instructions are sometimes e3ecuted out of order) that isnot necessaril! as written down in the program) but rather when information isavailable) although the! won,t be much out of se>uence- :ust enough to makethings run smoother.

It has a ; cache for programs and data) but it will be a two chip set) with theprocessor and a @D; @ cache in the same package. It is optimi=ed for @bicode) so will run 6bit code no faster than a (entium.

Cyrix

The 3 is a (entiumt!pe chip with (entium (ro characteristics) as it cane3ecute faster instructions out of se>uence. The! use a P-Rating to determine

performance relative to the (entium) so a 36 is e>uivalent to a (entium6) even if running at 6 M&=.


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Summin! up

In principle) the faster the C(* the better) but onl! if !our applications do a lot oflogical operations and calculation "where the work is centered around the chip%rather than writing to disk. #or e3ample) when a t!pical word processing taskreplacing a 6 M&= with a M&= one "doubling the speed% will onl! ge

!ou something like a D67N increase in practical performance) regardless of whathe benchmarks might sa!. It is often a better idea to spend money on a fasterhard dis.

Also) with onl! Mb 0AM in !our computer) !ou won,t see much performanceincrease from a $5@+ until !ou get a (entium F7 "none at all between a$5/+677 and a (entium D%.


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36@7

D7 @ @D

36

DD @

36D7

7 @ 7

36

@

Memory

Memor! T!pes

Memor! Access

uired. Actuall!) the! consist of a capacitor anda transistor- the capacitor stores a charge "data%) which represents a 6) and thetransistor acts as a switch that turns the charge on or off.


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could onl! be accessed se>uentiall!. A 0OM) on the other hand) is a memor! chipwith its electronic switches permanentl! on of off) so the! can,t be changedhence +ead Only Memory.

Static +,M"S0AM% is the fastest available) with a t!pical access time of @D

nanoseconds. Static 0AM is e3pensive and can onl! store a >uarter of the datathat $0AM is able to in the same given area) although it does retain it for aslong as the chip is powered. The transistors are connected so that onl! one iseither in or out at an! time- whichever one is in stands for a 6 bit. S!nchronousS0AM allows a faster data stream to pass through it- which is needed whenused for cacheing on F7 and 677 M&= (entium.

Dynamic +,M "$0AM% uses internal capacitors to store data "a single

transistor turns it on of off% which lose their charge over time) so the! needconstant refreshing to retain information) otherwise 6s will turn to 7s. The endresult is that between ever! memor! access is sent an electrical charge thatrefreshes the chip,s capacitors to keep data in a fit state) which cannot bereached whilst recharging is going on. 0eading a $0AM discharges itscontents) so the! have to be written back to immediatel! to keep the saneinformation.

-nhanced D+,M"8$0AM% replaces standard $0AM and the S0AM in the

level @ cache on the motherboard) t!picall! combining @D b!tes of 6DnsS0AM inside Dns $0AM. Since the S0AM can take a whole @D b!te pageof memor! at once) it gives an effective 6Dns access speed when !ou get a hit

"Dns otherwise%. The level @ cache is replaced with an SIC chip to sort outchipset vs. memor! re>uirements. S!stem performance is increased b! around/7N. 8$0AM has a separate write path that accepts and completes re>uestswithout the rest of the chip.

.+,M"


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clock c!cle- otherwise) each se>uential 0AM access inside the same pagetakes @ clock c!cles instead of ) once the page has been selected. As itreplaces level @ cache and doesn,t need a separate controller) space on themotherboard is saved) which is good for notebooks. It also saves batter!

power. In short) 8$O gives and increased bandwidth due to shortening of thepage mode c!cle) but it doesn,t appear to be that much faster in practice.

Memory ,ccess

The cycle timeis the time it takes to read from and write to a memor! cell) and itconsists of two stages- precharge and access. Prechar!eis where the capacitor inthe memor! cell is able to recover from a previous access and stabili=e. ,ccessiswhere a data bit is actuall! moved between memor! and the bus or the C(*Total access timeincludes the finding of data) data flow and recharge) and parts

of the access time can be eliminated or overlapped to improve performance. Thecombination of precharge and access e>uals c!cle time) which is what !ou shoulduse to calculate wait states from.

There are wa!s of making refreshes happen so that the C(* doesn,t notice "i.eConcurrent and &idden%) which is helped b! the / being able to use its on

board cache and not needing to use memor! so often an!wa!. In addition) !ou canaffect the +ow ,ccess Strobe "0AS%) or have Column ,ccess Strobe "CAS

before 0AS "see Advanced Chipset Setup%.

The fastest $0AM commonl! available is rated at 7ns. As these chips needalternate refresh c!cles) under normal circumstances data will actuall! beobtained ever! 6@7ns) giving !ou and effective speed of around M&= for thewhole computer) regardless of the C(* speed) assuming no action is taken tocompensate. Memor! chips therefore need to be operating at something like @7nsto keep up) assuming that the C(* needs onl! one clock c!cle for each one fromthe memor! bus- one internal c!cle for each e3ternal one. Intel processors mostl!use two for one) so the M&= C(* is actuall! read! to use memor! ever! 7ns

but !ou need to allow a little more for overheads) such as data assembl! and thelike. One wa! of matching the capacities of components with different speedsincludes the use of wait states.

Cloc Speed

/MH01

Cycle Time

/ns1

6 6777

D @77
http://var/www/apps/conversion/tmp/scratch_4/advchip.htmhttp://var/www/apps/conversion/tmp/scratch_4/advchip.htm


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6@D

6@

6

@7 D7

@D /7

7/7 @D

.ait States

A wait state indicates how man! ticks of the s!stem clock the C(* has to wait formemor! to catch upit will generall! be 7 or 6) but can be up to if !ou,re usingslower memor! chips.


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A processor +,M cache) which is a bridge between the C(* and slower main

memor!- it consists of an!where between @D6@; of "fast% Static 0AM chipsand is designed to retain the most fre>uentl! accessed code and data from mainmemor!. It can make 6 wait state 0AM look like that with 7 wait stateswithout ph!sical ad:ustments) assuming that the data the C(* wants is in thecache when re>uired "known as a cache hit%. To minimi=e the penalt! of a

cache miss) cache and memor! access are often in parallel) with one beingterminated when not re>uired. On a /) how much cache !ou need reall!depends on the amount of memor!- $ell sa! that :umping from 6@; to @D;onl! increases the hit rate b! around DN and 9iglen sa! !ou onl! need morethan @D; if !ou have more than @ Mb 0AM. A cache should be fast andcapable of holding the contents of several different parts of main memor!Software pla!s a part as well) since cache operation is based on the assumptionthat programs access memor! where the! have done so alread!) or are likel! to

ne3t) ma!be through looping "where code is reused% or code is organi=ed to bene3t to other relevant parts. A basic cache design will look up an address forthe C(* and return the data inside one clock c!cle) or @7ns at D7 M&=

AsynchronousS0AM will be used for this. As the round trip from the C(* tocache and back again takes up a certain amount of time) onl! the remainder isavailable to retrieve data) which gets smaller as the motherboard speed isincreased. SynchronousS0AM uses a buffer to keep the whole routine insideone clock c!cle) even though it ma! use two "or more% clock c!cles the first

time round. The address from the C(* is stored) and while the ne3t is comingin to the buffer) the data for the first is retrieved) and the c!cle continues.(ipeline S0AM uses more clock c!cles) t!picall! three) the first time roundand Burst S0AM will deliver / words "blocks of data% over for consecutivec!cles if the re>uest from the C(* is for the first- there will be no waiting forthe C(* to re>uest each one individuall!. 1ote the level @ cache can beunreliable) so be prepared to disable it in the interests of reliabilit!. #orma3imum efficienc!) or minimum access time) a cache ma! be subdivided intosmaller blocks that can be separatel! loaded) so the chances of a different partof memor! being re>uested and the time needed to replace a wrong section areminimi=ed. There are three mapping schemes that assist with this'

3ully ,ssociati%e) where the whole address is kept with each block of

data in the cache "in tag 0AM%) needed because it is assumed there is norelationships between the blocks. This can be inefficient) as an addresscomparison needs to be made with ever! entr! each time the C(*

presents the address for its ne3t instruction.


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one b!te is accessed at a time- also) the! t!picall! run between 6D7/77ns) sousing them will be slow relative to @bit memor! at 77ns) which is capable ofmaking four accesses at once.

Shado$ RA% is the process of cop!ing the contents of a 0OM directl! intoe3tended memor! which is given the same address as the 0OM) from where it

will run much faster. The original 0OM is then disabled) and the new locationwrite protected. If !our applications e3ecute 0OM routines often enoughenabling Shadow 0AM will make a difference in performance of around Nassuming a program spends about 67N of its time using instructions from 0OM

but theoreticall! as high as 77N. The drawback is that the 0AM set aside forshadowing cannot be used for an!thing else) and !ou will lose a correspondingamount of e3tended memor!) The remainder of *pper Memor!) however) canusuall! be remapped to the end of e3tended memor! and used there.

uests. Some programs don,t make use of the video 0OM)

preferring to directl! address the card,s registers) so !ou ma! want to usee3tended memor! for something else. If !ou machine hangs during the startupse>uence for no apparent reason) check that !ou haven,t shadowed an area ofupper memor! containing a 0OM that doesn,t like itparticularl! one on a harddisk controller) or that !ou haven,t got two in the same 6@; segment.

Base Memory

The first /7; available) which traditionall! contains $OS) device drivers) TS0sand an! programs to be run) plus their data) so the less room $OS takes up) themore there is for the rest. $ifferent versions of $OS were better or worse in thisrespect. In fact) under normal circumstances) !ou can e3pect the first F7; or so toconsist of'

AnInterrupt &ector Ta'le) which is 6; in si=e) including the name and addressof the program providing the interrupt service. Interrupt vectors point toroutines in the BIOS or $OS that programs can use to perform low levelhardware access. $OS uses io4sys and msdos4sys for the BIOS and $OSrespectivel!.

0OM BIOS tables) which are used b! s!stem 0OMs to keep track of what,s

going on. This will include I+O addresses and possibl! userdefined hard diskdata.


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$OS itself) plus an! associated data files it needs to operate with "e.g. buffers

etc.%.

$OS was written to run applications inside the bottom /7; block simpl!because the designers of the original IBM (C decided to. Memor! at the time wase3pensive) and most C(+M machines onl! used /; an!wa! "the (C with 6@;was E67)777P%. Other machines of the same era used more- the Sirius allowedF; for programs. Contrar! to popular belief)


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include network interface cards or graphics adapters. There is no memory in itthe space is simpl! reserved. This is wh! the memor! count on older machineswith onl! 6 Mb was /7 J /; of etended memory- the /; was remappedabove 6 Mb so it could be used.


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In effect) IM "/.7% directl! swaps the contents of an! 6; block of e3pandedmemor! with a similar one inside upper memor!- no swapping takes place) butthe pages have their address changed to look as if it does. Once the page frame ismapped to a page on the card) the data of that page can be seen b! the C(*.(oints to note about IM'

It,s normall! onl! available for data "no program code%.

(rograms need to be speciall! written to use it.

In theor!) IM / doesn,t need a page frame) the programs !ou run ma! welle3pect to see one. In addition) there could be up to / pages) so !ou could bankswitch up to a megab!te at a time) effectivel! doubling the address space of theC(*) and enabling program code to be run and multitasking. This was calledlarge-+rame .%S) but it still used onl! four pages in upper memor!- the idea wasto remove most of the memor! on the motherboard. The memor! card 'ack+illed

conventional memor! and used the e3tra pages for banking.On an 7 or @based machine) e3panded memor! is usuall! provided b!circuitr! on an e3pansion card) but there are some software solutions. "and/% based machines have memor! management built in to the central processorso all that,s needed is the relevant software to emulate IM /emm(&'4exe osimilar%.

7irtual Memory

49irtual4 in the computer industr! is a word meaning that something is other thanwhat it appears to be. Man! people have difficulties to understand what virtualmemor! actuall! means. 9irtual memor! is memor! that does not e3ist. Severalcontradictor! definitions about virtual memor! e3ist. #or some) virtual memor! isnot disk space. $isk "swap% space is used for backing allocated "committed%memor! "global data) heap and stack% when the OS ran out of s!stem memor!"0AM%. 83ample' ?ou create a program and define a stack of /;B. Because

!our program reall! doesn,t re>uire /;B "onl! @;B%) the OS will allocate onl!one page "/;% during runtime. The other /;B /;B K 7;B is virtuamemor!- memor! that does not e3ist) not in s!stem memor!) not on disk. Onl!when !our program runs out of stack) another page will be allocated unless a totaof /;B is used alread!.

#rom another point of view) 9irtual Memor! isn,t memor! at all) but hard diskspace made to look like it- the opposite of a 0AM disk.


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Bac!round

Before the da!s of the original IBM (C) there were no standards. The first agreedupon bus specification which was drawn up was called the S677. Steven Gobsand Steven


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above the capabilit! of disk drives) or most network and video cards. Theaveragedata throughput is around a >uarter of that. Its design makes it difficult tomi3 and 6bit 0AM or 0OM within the same 6@; block of upper memor!an bit 9HA card could force all other cards in the same "C777$###% range touse bits as well) which was a common source of ine3plicable crashes where 6

bit network card were involved.

System ,ttributes PC or )T ,T Classic Bus

Processor 7+7 @ and higher

CP6 Modes 0eal 0eal+(rotected

-xpansion Slot bit 6 bit

Slot Type ISA ISA

Interrupts J 1MI 6 J 1MI

DM, Channels /

Maximum +,M 6 MB 6 MB3loppy Controller 7;+@7; 6.@M+6.//M

-IS,

-xtended Industry Standard ,rchitecture. An evolution of ISA and"theoreticall!% backward compatible with it) including the speed " M&=%) so theincreased data throughput is mainl! due to the bus doubling in si=ebut !ou mususe 8ISA e3pansion cards. It has its own $MA arrangements) which can use thecomplete address space. On advantage of 8ISA "and Micro Channel% is the easeof setting up e3pansion cardsplus them in and run the configuration softwarewhich will automaticall! detect their settings.

System ,ttributes -IS, IS,

Memory Capacity / HB 6 MB

Data bus width @ bit 6 bit

DM, +an!e / HB 6 MB

DM, data path +6+@ +6Maximum DM, Transfer MB+sec @ MB+sec

Bus ,rbitration Bus Masters Single

Bus Master data path 6+@ 6

Synchronous cloc rate . M&= . M&=


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MC,

Micro Channel ,rchitecture. A proprietar! standard established b! IBM in 6Fto take over from ISA) and therefore incompatible with an!thing else. It comes intwo versions) 6 and @bit and) in practical terms) is capable of transferringaround @7 MBps.

It was found that poorl! designed ISA bus machines did have fairl! high radiofre>uenc! emissions. Hood ISA bus designs complied with the basic #CC Class Aregulations. MCA) with its ver! strict #CC Class B certification) has a distinctadvantage over ISA and 8ISA as C(* clock speeds go higher and higher. MCA isver! well shielded which makes it immune to electrical noise.

MCA is designed to eliminate the hassle associated with setting :umpers and $I(switches on adapter boards. The adapter card booklet describing all possiblesettings gets invariabl! lost) making the card unusable if the card,s environmenchanges. IBM,s answer is called (rogrammable Option Selection "(OS% which is

built into MCA computers. The (OS uses a special file called an Adapter$escription #ile "A$#% which is supplied with each adapter board. This A$#contains all the possible setting and configurations for the specific card. The (OSwill also take care of an! conflicting settings.

MCA also corrects an! potential timing problems which ma! e3ist betweenadapter boards or even memor!. 8ach e3pansion slot is supposed to carr! the

same signals as an! other slot but this might not alwa!s happen. 8ffects on thebus) such as capacitance and signal propagation dela!s) can cause timingwindows to appear differentl! in different slots. These effects cause une3plained

problems to occur mostl! in a random fashion. MCA has the abilit! to wait for aresponse "automatic wait states% until the adapter is read! to continue. This canslow the process down but is considered more important than the 4ghost4s!mptoms found on ISA.

79 Bus

The 9ideo 8lectronics Standards Association "98SA% formed a committee inGune 6FF@ to stud! e3isting and certainl! emerging) local bus video s!stems interms of connector la!out) signal and data structures. In September 6FF@ the!finalised the 98SA ocal Bus connector which connects devices directl! to thelocal+host bus. There,s also an ,Opti local bus connector,. This connector e3tendsthe 8ISA bus where the 9B connector e3tends the ISA bus. The local bus is one


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more directl! suited to the C(*- it,s ne3t door "hence local%) has the samebandwidth and runs at the same speed) so the bottleneck is less "ISA was local inthe earl! da!s%. $ata is therefore moved along the bus at processor speeds. 79B6S) a @bit bus which allows bus mastering) and uses two c!cles to transfers a@bit word) peaking at Mb+sec. It also supports burst mode) where a singleaddress c!cle precedes four data c!cles) meaning that / @bit words can move in

onl! D c!cles) as opposed to ) giving 67D Mb+sec at M&=. The speed ismainl! obtained b! allowing 9Bus adapter cards first choice at interceptingC(* c!cles. It,s not designed to cope with more than a certain number of cards at

particular speeds- e.g. at ) @ at /7 and onl! 6 at D7 M&=) and even that oftenneeds a wait state inserted. 9Bus @ is /bit) !ielding @7 Mb+sec at D7 M&=There are two t!pes of slot- Master and Slave. Master boards "e.g. SCScontrollers% have their own C(*s which can do their own things- slaves "i.evideo cards% don,t. A slave board will work on a master slot) but not vice versa.

PCI

PCI) which is a me==anine bus) divorced from the C(*) giving it someindependence and the abilit! to cope with more devices) so it,s more suited tocrossplatform work. It is time multiple3ed) meaning that address and data linesshare connections. It has its own burst mode that allows 6 address c!cle to befollowed b! as man! data c!cles as s!stem overheads allow. At nearl! 6 word per

c!cle) the potential is @/ Mb+sec. It can operate up to M&=) or M&= with(CI @.6 and can transfer data at @ bits per clock c!cle so !ou can get up to 6@Mb!tes+sec "@/ with @.6%. The (CI @.6 specs include a /bit M&= (CI bus8ach (CI card can perform up to functions) and !ou can have more than one

busmastering card on the bus. It should be noted) though) that man! functions arenot available with (CI) such as sound. 1ot !et) an!wa!. It is part of the plug and

playstandard) assuming !our operating s!stem and BIOS agree) so it is autoconfiguring "although some cards use :umpers instead of storing information in achip%- it will also share interrupts under the same circumstances. The (CI chipsethandles transactions between cards and the rest of the s!stem) and allows other

buses to be bridged to it "t!picall! and ISA bus to allow older cards to be used%1ot all of them are e>ual) though- certain features) such as 'yte merging) ma! beabsent. The connector ma! var! according to the voltage the card uses ". or Dvsome cards can cope with both%


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Basic Optimi0ation Trics

This section is intended for users who have a limited knowledge of BIOS setup to

safel! alter their settings. It provides a set of fundamental procedures that ma!help improve the performance of !our s!stem. Also) have a look at the importanBIOS settingssection.

Make sure that all standard settin!scorrespond to the installed components of

!our s!stem. #or instance) !ou should verif! the date) the time) availablememor!) hard disks and flopp! disks. #or more information) go to the StandardCMOS Setupsection.

Make sure that !our cache memory "internal and e3ternal% is enabled. O

course !ou must have internal "6% and e3ternal "@% cache memor! presenwhich is alwa!s the case for recent s!stems "less than five !ears old%. #or moreinformation) go to the Advanced CMOS Setup section. 0ecentl!) somemotherboards were found having fae cache memory. Some unscrupulousmanufacturers are using solid plastics chips containing no memor! to lurevendors and customers and then gain e3tra profits in an highl! competitivesemiconductors market. BewareP #or more information about this scam"mostl! occurring in 8ngland%) please consult this


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Important BIOS Settin!s

This is a short list of settings important for the appropriate configuration of !ours!stem. A long list is available in the inde3 section. DO ;OTmess with thesesettings unless !ou have read carefully their implications. Also) please have alook at thebasic optimi=ation trickson how to coordinate some of these settings.

Standard CMOS Setup

$ate and Time

(rimar! $ispla!

;e!board &ard $isk C T!pe

#lopp! $rive A

,d%anced CMOS Setup

Above 6 MB Memor! Test

Memor! parit! error check

1umeric (rocessor Test

S!stem Boot Se>uence 83ternal Cache Memor!

Internal Cache Memor!

(assword Checking Option

9ideo 0OM Shadow C777)6;

S!stem 0OM Shadow #777)/;

,d%anced Chipset Setup

AT B*S Clock Selection Memor! 0ead


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Slot 5 *sing I1TR

5th Available I0

(CI I$8 I0 Map to

AT bus clock fre>uenc!

(CI Clock #re>uenc!

ISA Bus Clock #re>uenc!

Standard CMOS Setup

+emember youn!


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Hard dis C type' The number of !our primar! "master% hard drive. Most of

the time this number is /) which means that !ou must specif! the drive specsaccording to !our hard drive manual.

Cyln' The number of c!linders on !our hard disk.

Head' The number of heads.

.Pcom' uenc!Modulated) or 0) 0un ength imited%. Set it to 7 or ma3 C!lR.

Sect' The number of sectors per track. It is often 6 for M#M and @ for

0 &$$. On other t!pes of drives) it will var!.

Si0e' This is automaticall! calculated according the number of c!linders

heads and sectors. It is in megab!tes and applies this formula' "&ds C! Sect D6@% + 67/.

-ID- specifications.


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Hard dis D type' The number of !our secondar! "slave% hard drive. Same

procedure than above. uent is9HA+(HA+8HA. Modern computers have 9HA "9ideo Hraphics Arra!%. If!ou have an older black+white displa! select Mono or &ercules) if !our 9ideoadapter card is te3t onl!) select M$A.

?eyboard' Installed recommended. If 4not installed4 this option sets the BIOS

to pass the ke!board test in the (OST) allowing to reset a (C without ake!board "file server) printer server) etc.%) without the BIOS producing ake!board error. As a s!stem administrator) !ou can uninstall the ke!board as a

supplementar! securit! procedure to prevent people messing up with theserver.

,d%anced CMOS Setup

+emember=

Ma! var! according to !our s!stem) BIOS version and brand. Some functions

ma! not be present or the order and name may be different "particularl! fordifferent BIOS brand%. ;now -),CT9" what !ou are doing. Someconfigurations ma! keep !our computer off from bootin!. If that,s the caseSwitch the power off. Turn !our computer on .HI9- keeping the D-9 ke!

pressed. This is supposed to erase the BIOS memor!. If it still doesn,t bootconsult !our motherboard manual. ook for a 4forget CMOS 0AM4 :umper. Setit. Tr! it again. If it still doesn,t boot) ask a friend or post to a computer hardwarenewsgroup. ?ou are permitted to panic.


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Typematic +ate Pro!rammin!' $isabled recommended. It enables the

t!pematic rate programming of the ke!board. 1ot all ke!boards support thisThe following two entries specif! how the ke!board is programmed if enabled

Typematic +ate Delay /msec1' D77 ns recommended. The initial dela! before

ke! autorepeat starts) that is how long !ou,ve got to press a ke! before it startsrepeating.

Typematic +ate /Chars8Sec1' 6D. It is the fre>uenc! of the autorepeat i.e

how fast a ke! repeats.

,bo%e @ MB Memory Test' If !ou want the s!stem to check the memor!

above 6 MB for errors. Disabled recommendedfor faster boot se>uence. The&IM8M.S?S driver for $OS .@ verifies the 5MS "83tended Memor!Specification%) so this test is redundant. It is thus preferable to use the 5MStest provided b! &IM8M.S?S since it is operating in the real environmen"where user wait states and other are operational%.

Memory Test Tic Sound' 8nabled recommended. It gives an audio record

that the boot se>uence is working properl!. (lus) it is an aural confirmation of!our C(* clock speed+Turbo switch setting. An e3perimented user can hear ifsomething is wrong with the s!stem :ust be the memor! test tick sound. Sinces!stems have now much more memor! than before) this setting is not commonan!more.

Memory Parity -rror Chec' -nabled recommended. Additional feature to

test bit errors in the memor!. All "or almost all% (Cs are checking theirmemor! during operation.8ver! b!te in memor! has another ninth bit) thawith ever! write access is set in such wa! that the parit! of all b!tes is odd


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speed of slower memor!. 7 ns and 7 ns SIMMS will surel! make !our s!stemcrash and !ourself wonder what is the problem "I know%.

Hard Dis Type *A +,M ,rea' The BIOS has to place the &$ t!pe / data

somewhere in memor!. ?ou can choose between $OS memor! or (C BIOS"or peripheral card% memor! area 7'77. $OS memor! is valuable) !ou onl!have /7;B of it. So !ou should tr! to use 7'77 memor! area instead. Therema! be some peripheral card which needs this area too "sound card) networkcard) whatever%. So if there are some fanc! cards in !our (C) check themanuals if the!,re using the 7'77 area. But in most cases this will workwithout checking. This is redundant if BIOS is shadowed "ma!be not in ver!old BIOSes%. The 0AM area can be verified b! checking address of int/6h andint/h. These are fi3ed disk parameters blocks. If the! point to the BIOS areaBIOS made modification of parameters before mapping 0AM there.

If An! 8rror4.ait for 3@ If ,ny -rror' uence encounte

an error it asks !ou to press #6. Onl! at ,nonfatal, errors. If disabled) thes!stem prints a warning and continues to boot without waiting for !ou to pressan! ke!s. 8nabled recommended. $isabled if !ou want the s!stem to operateas a server without a ke!board.

System Boot 6p ;um 9oc' Specif! if !ou want the 1um ock ke! to be

activated at boot up. Some like it) some do not. MS$OS "starting with .7ma!be earlier% allows a 41*MOC;K4 directive in config.s!s) too- isomeone turns the BIOS flag off but has 1*MOC;KO1 in their

configuration file) the! ma! be a bit perturbed. ;umeric Processor Test' 8nabled if !ou have a math coprocessor "built in for

the /$5) /$5@) /$5 and (entium D famil!%. $isabled if !oudon,t "S5) $5) /S5) /SC and /$C%. If disabled) !our #(*"#loating (oint *nit) if present% isn,t recogni=ed as present b! the s!stem andwill therefore significantl! decrease the performance of !our s!stem.

.eite Coprocessor' If !ou have ues for adding some securit! to a (C.


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System Boot Seuence' uent error in CMOS setupas if $isabled when !ou have cache memor!) the s!stem performancedecreases significantl!. Most s!stems have from /; to D6@; of e3ternalcache. It is a cache between the C(* and the s!stem bus. $ifferent operatings!stems ma! address different levels of cache memor!. #or instance) $OS and


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memor! above 6 MB. 1ormall! all 0AM access above 6 MB is handledthrough the ke!board controller chip "7/@ or /@%. *sing this option willmake the access faster than the normal method. This option is ver! useful innetworking and multitasking operating s!stems.

Turbo Switch 3unction' 8nables or disables the turbo switch. $isabled

recommended. This setting is now removed since there are no need to switch

from normal to turbo modes. Shadow Memory Cacheable' ?ou increase speed b! cop!ing 0OM to 0AM

$o !ou want to increase it b! cacheing it ?es or no see 9ideo BIOS Areacacheable. ?es recommended for MS$OS and OS+@. inu3 and other *ni3like operating s!stems will not use the cached 0OMs and will benefit from theadditional available memor! if the! are not cached.

Password Checin! Option' Setup password to have access to the s!stem and

+ or to the setup menu. Hood if the computer is to be shared with several

persons and !ou don,t want an!one "friends) sister) etc.% to mess up with theBIOS. $efault password' AMI "if !ou have AMI BIOS%. Award' BIOSTA0 orA


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Some video cards ma!be using different addresses than C777 and C/77. If it isthe case) !ou should use supplied utilities that will shadow the video BIOS) inwhich case !ou should disable this setting in the CMOS. 9ideo BIOSshadowing can cause software like 5#ree "the free 5


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,daptor +OM Shadow -C$$E@'?' $isabled. SCSI controller cards with

their own BIOS could be accelerated b! using Shadow 0AM. Some SCSIcontrollers do have some 0AM areas too) so it depends on the brand.

Some SCSI adapters do not use I+OAddresses. The BIOS address range containswritable addresses) which in fact are the I+Oports. This means this address mustnot be shadowed and even not be cached.

System +OM Shadow 3$$$E '*?' Same thing as 9ideo shadow) bu

according to the s!stem BIOS "main computer BIOS%. -nabledrecommended for impro%ed performance. S!stem BIOS shadowing andcaching should be disabled to run an!thing but $OS "


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Cachein!

Memory

,utomatic Confi!uration' Allows the BIOS to set automaticall! severa

important settings "e.g. Clock divider) wait states) etc.%. 9er! useful fornewbies. Disabled recommended if you want to play around with thesettin!s. If !ou have some special adapter cards) !ou will also have to disablethis option.

?eyboard +eset Control' 8nable CtrlAlt$el warm reboot. 8nabled

recommended for more control over !our s!stem.

+efresh

Hidden +efresh' Allows the 0AM refresh memor! c!cles to take place in

memor! banks not used b! !our C(* at this time) instead or together with thenormal refresh c!cles) which are e3ecuted ever! time a certain interrup"$07 ever! 6D ms% is called b! a certain timer "O*T6%. 8ver! time it takes @to / ms for the refresh. One refresh c!cle ever! Q6 us refreshes @D rows in Q/ms. 8ach refresh c!cle onl! takes the e>uivalent of one memor! read or lessas CAS "Column Address Strobe% is not needed for a refresh c!cle. Some0AM can do it) some not. Tr!. If the computer fails) turn it off. 8nabledrecommended. There are t!picall! t!pes of refresh schemes' c!cle steal

c!cle stretch) or hidden refresh. C!cle steal actuall! steals a clock c!cle fromthe C(* to do the refresh. C!cle stretch actuall! dela!s a c!cle from theprocessor to do the refresh. Since it onl! occurs ever! sa! /ms or so) it,s animprovement from c!cle steal.


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Concurrent +efresh' Both the processor and the refresh hardware have access

to the memor! at the same time. If !ou switch this off) the processor has towait until the refresh hardware has finished "it,s a lot slower%. -nabledrecommended.

Burst +efresh5(erforms several refresh c!cles at once. Increase the s!stem

performance.

D+,M Burst at * +efresh50efresh is occurring at Bursts of four) increasing

the s!stem performance.

Hi2speed +efresh50efreshes are occurring at an higher fre>uenc!) which is

improving the s!stem performance. Of course) not all t!pes of memor! cansupport it and Slow 0efresh is preferred.

Sta!!ered +efresh50efresh is performed on memor! banks se>uentiall!. The

advantages are related to less power consumption and less interferencebetween memor! banks.

Slow Memory +efresh Di%ider5The AT refresh c!cle occurs normall! ever!

6 ns) straining the C(*. If !ou can select an higher value) such as / ns) !ouwill increase the performance of !our s!stem.

Decoupled +efresh Option58nables the ISA bus and the 0AM to refresh

separatel!. Because refreshing the ISA bus is more slow) this causes less strainon the C(*.

+efresh 7alue' The lower this value is) the best the performance.

+efresh +,S ,cti%e Time' The amount of active time needed for 0owAddress Strobe during refresh. The lower the better.

Data Bus

Sin!le ,9- -nable' Address atch 8nable "A8% is an ISA Bus Signal "(in

B@% that indicates that a valid address is posted on the bus. The bus is used tocommunicate with and 6 bit peripheral cards. Some chipsets have thecapabilit! to support an enhanced mode in which multiple A8 assertions ma!

be made during a single Bus C!cle. Single A8 8nable apparentl! enables ordisables that capabilit!. Ma! slow the video bus speed if enabled. $isabled"1o% recommended.

,T B6S Cloc Selection /or ,T Bus Cloc Source1' Hives a division of the

C(* clock "or S!stem Clock% so it can reach the ISA 8ISA bus clock. Animproper setting ma! cause significant decrease in performance. The settingsare in terms of C;+3) "or C;I1+3 and C;@+3% where 3 ma! have valueslike @) ) /) D) etc. C; represents !our processor speed) with the e3ception


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that clockmultiple processors need to use the 85T801A clock rate) so a/$5) /$5@+) and /$5+FF all count as and should have adivider value of /. #or @ and processors) C; is half the speed of theC(*. ?ou should try to reach &4(( Mh0"that,s the old bus clock of IBM ATthere ma! be cards which could do higher) but it,s not highl! recommended%On some motherboards) the AT bus speed is .6D Mh=. On new BIOS versions

there is an A*TO setting that will look at the clock fre>uenc! and determinethe proper divider. &ere are some appropriate settings'

C;+

S5+$56) $5@7) $5@D) $5@+D7)$5/+677

C;+/

S5+$5) $5@+) $5+FF

C;+D

$5/7) $5@+7

C;+

$5D7) $5@+677

Selectin! the ri!ht cloc di%ider. ?ou can tr! other clock settings to increaseperformance. If !ou choose a too small di%ider "C;+@ for a $5% yoursystem may han!. #or a too bi! di%ider"C;+D for a $5% the performanceof IS, cards will decrease. This setting is for data e3change with ISA cards;OT 79 bus and PCI cards which run at C(* bus clock speeds' @DMh=Mh= and higher. If !our ISA cards are fast enough to keep up) it is possible to

run the bus at 6@ Mh=. 1ote that if !ou switch cr!stals to overclock !our C(*)!ou are also overclocking the ISA bus unless !ou change settings to compensateGust because !ou can overclock the C(* doesn,t mean !ou can get awa! withoverclocking the ISA bus. It might :ust be one card that causes trouble) but one isenough. It might cause trouble even if !ou aren,t using it b! responding when itshouldn,t.

IS, Bus Speed' As above) but related to (CI.

Bus Mode' It can be set in s!nchronous and as!nchronous modes. In

s!nchronous mode) the C(* clock is used) while in as!nchronous mode theATC; is used.

,T Cycle .ait State'


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&2bit MemoryE I8O .ait State' As above) e3cept this setting is for bit

operations.

@'2bit I8O +eco%ery Time' The additional dela! time inserted after ever! 6

bit operations. This value is added to the minimum dela! inserted after ever!AT c!cles.

3ast ,T Cycle' If enabled) ma! speed up transfer rates with ISA cards) notabl!

video.

IS, I+G' Inform the (CI cards of the I0s used b! ISA cards) so the! be

discarded.

DM, .ait States' The number of wait states inserted before direct memor!

access "$MA%. The lower the better.

DM, Cloc Source' The source of the $MA clock for which some periphera

controllers) like flopp!) tape) network and SCSI adapters use to address

memor!) which is D M&= ma3imum. -$$$$ +OM belon!s to ,TB6S' Tells if the 87777 area "upper memor!%

belongs to the MB $0AM or to the AT bus. ?es recommended.

Memory +emappin!' 0emaps the memor! used b! the BIOS "A7777 to

#### / k% above the 6 Mb limit. If enabled !ou cannot shadow 9ideo andS!stem BIOS. $isabled recommended.

3ast Decode -nable' 8nabled recommended. 0efers to some hardware that

monitors the commands sent to the ke!board controller chip. The original AT

used special codes not processed b! the ke!board itself to control theswitching of the @ processor back from protected mode to real mode. The@ had no hardware to do this) so the! actuall! have to reset the C(* toswitch back. This was not a speed! operation in the original AT) since IBMnever e3pected that an OS might need to :ump back and forth between real and

protected modes. Clone makers added a few ($ chips to monitor thecommands sent to the ke!board controller chip) and when the 4reset C(*4code was seen) the ($ chips did an immediate reset) rather than waiting forthe ke!board controller chip to poll its input) recogni=e the reset code) and thenshut down the C(* for a short period. This 4fast decode4 of the ke!board resecommand allowed OS+@ and


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0OM within the same 6@; block of high address space. Thus) an bit BIOS0OM on a 9HA card forced all other peripherals using the C777$fff range toalso use bits. B! doing an 4earl! decode4 of the high address lines along withthe +6 bit select flag) the I+O bus could then use mi3ed and 6 bi

peripherals. It is possible that on later s!stems) this BIOS flag controls the4fast decode4 on these address lines.

-xtended I8O Decode' The normal range of I+O addresses is 773ff- 67 bitsof I+O address space. 83tended I+Odecode enables wider I+Oaddress bus. TheC(* support a /; I+O space) 6 address lines. Most motherboards or I+Oadapters can be decoded onl! b! 67 address bits.

I8O +eco%ery Time' I+O recover! time is the number of wait states to be

inserted between two consecutive I+O operations. It is generall! specified as atwo number pair e.g. D+. The first number is the number of wait states toinsert on an bit operation) the second the number of waits on a 6 bit

operation. A few BIOSes specif! an I+O Setup time "AT Bus "I+O% Command$ela!%. It is specified similarl! to IO 0ecover! Time) but is a dela! beforeSTA0TI1H an I+O operation rather than a dela! B8T


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find an! such drives in the future. The relevant parameter for block mode is thenumber of sectors per interrupt. The ma3imum number of sectors per interruptis often "but not alwa!s% related to the drive,s buffer si=e. If this setting is notset properl!) communication with COM ports ma! not work properl!. If the

block si=e "sectors+interrupt% is set to too large a value) !ou ma! e3perienceserial port overruns and C0C errors. To fi3 this) decrease the block si=e

"preferred% or disable block mode altogether.#or more info) please have a lookat The 8I$8 #AATA harddisks.

ID- DM, Transfer Mode' Settings are $isabled) T!pe B "for 8ISA% and

Standard "for (CI%. Standard is the fastest but ma! cause problems with I$8C$ 0OMs. The standard t!pe is t!pe #. 1ote that both are socalled 4third

part! $MA4 and should not be confused with firstpart! "busmastering% $MAoffered b! man! modern boards.

ID- Multiple Sector Mode'


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the number of clocks needed to load four @bit words into a C(* internalcache. T!picall! specified as clocks per word. @666 indicates D clocks toload the four words and is the theoretical minimum for current high end C(*s"/$5) /S5) /$5@) /$5/) (entium%. Conceptuall!) the mnnnnotation is narrowl! limited to C(*s supporting burst mode and with cachesorgani=ed as / word 4lines4. &owever it would not be a surprise to see it

e3tended to other C(* architectures. It takes simple integer values) such as @666) 666 or @@@. This determines the number of wait states for thecache 0AM in normal and burst transfers "the latter for / onl!%. The lower!ou computer can support) the better. /666 is usuall! recommended.

Cache .rite Option' Same thing as memor! wait states) but according to

cache ram.

3ast Cache +ead8.rite' 8nable if !ou have two banks of cache) /; or

@D;.

Cache .ait State5ike conventional memor!) the lower wait states for !ourcache) the better. 7 will give the optimal performance) but 6 wait state ma! bere>uired for bus speed higher than M&=.

Ta! +am Includes Dirty' 8nabling will cause an increase in performance

because the cache is not replaced during c!cles) simpl! written over. It wilusuall! cut the ma3imum cachable range in half) as one bit is taken off theaddress tag in order to be used as a dirt! tag bit. So) if !ou have a lot ofmemor!) !ou might be better off without dirt! tag bit.

;on2Cacheable Bloc2@ Si0e' $isabled. The 1onCacheable region iintended for a memor!mapped I+O device that isn,t supposed to be cached#or e3ample) some video cards can present all video memor! at 6D Mb 6Mb so software doesn,t have to bankswitch. If the noncacheable regioncovers actual 0AM memor! !ou are using) e3pect a significant performancedecrease for accesses to that area. If the noncacheable region covers onl! none3istent memor! addresses) don,t worr! about it. If !ou don,t want to cachesome memor! !ou can e3clude @ regions of memor!. There are good reasons

not to cache some memor! areas. #or e3ample) if the memor! areacorresponds to some kind of buffer memor! on a card so that the card ma!alter the contents of this buffer without warning the cache to invalidate thecorresponding cache lines. Some BIOSes take more options than enabled+disabled) namel! 1onlocal +1oncache +$isabled "9B onl!%.

;on2Cacheable Bloc2@ Base' 7;B. 8nter the base address of the area !ou

don,t want to cache. It must be a multiple of the 1onCacheable Block6 Si=eselected.


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;on2Cacheable Bloc2# Si0e' $isabled.

;on2Cacheable Bloc2# Base' 7;B.

Cacheable +,M ,ddress +an!e' *suall! chipsets allow memor! to be

cached :ust up to 6 or @ MB. This is to limit the number of bits of a memor!address that need to be saved in the cache together with its contents. If !ouonl! have /MB of 0AM) select /MB here. The lower the better) don,t enter6MB if !ou onl! have MB installedP

7ideo BIOS ,rea Cacheable' To cache or not to cache video BIOS) a good

>uestion. ?ou should tr! what is better video access is faster with ,enabled,but cache has its si=e.


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D+,M C,S Timin! Delay' The default is no CAS dela!. $0AM is

organi=ed b! rows and columns and accessed through strobes. Then a memor!read+write is performed) the C(* activates 0AS "0ow Access Strobe% to findthe row containing the re>uired data. Afterwards) a CAS "Column AccessStrobe% specifies the column. 0AS and CAS are used to identif! a location in a$0AM chip. 0AS access is the speed of the chip while CAS is half the speed.


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PCI Slot Confi!uration

Although an unlimited number of (CI slots is allowed) in practice / is thema3imum) due to loading considerations.(CI cards and slots use an internainterrupt s!stem) with each slot being able to activate up to /) labelled eitherI1TRAI1TR$) or I1TR6I1TR/. These are nothing to do with I0s) although

the! can be mapped to them if the card concerned needs it. T!picall! I0s F and67 are reserved for this) but an! available ones can be used.

9atency Timer /PCI Clocs1. Controls the length of time an agent on the (CI

bus can hold the bus when another has re>uested it) so ever!thing gets its fairshare.Since the (CI bus runs faster than the ISA bus) the (CI bus must beslowed during interactions with it. This setting allows !ou to define how longthe (CI bus will dela! for a transaction between the given (CI slot and the ISA

bus. This number is dependent on the (CI master device in use and varies from

7 to @DD. AMI defaults to ) but /7 clocks is a good place to start at M&="(hoeni3%. The shorter the value) the more rapid access to the bus a devicegets) with better response times) but the lower becomes the effective

bandwidth and hence data throughput. 1ormall!) leave this alone) but !oucould set it to a lower value if !ou have latenc! sensitive cards "e.g. audiocards and+or network cards with small buffers%. Increase slightl! if I+Osensitive applications are being run.

*sing I0. Affected b! the Trigger method.


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PCI ID- I+G Map to. Allows !ou to configure !our s!stem to the t!pe of

I$8 disk controller- an ISA device is assumed. The more apparent difference isthe t!pe of slot being used. &owever) if !ou have a (CI I$8 controller) thissetting allows !ou to specif! which slot has the controller and which (CI I1TR"A) B)C or $% is associated with the connected hard drives. 1ote that this refersto the hard disk rather than individual partitions. Since each I$8 controller

supports two drives) !ou can select the I1TR for each. 1ote also that theprimar! has a lower interrupt than the secondar!) as described in Slot 3 *singI1TR.

(CIAuto. If the I$8 is detected b! the BIOS on one of the (CI slots)

then the apropriate I1TR channel will be assigned to I0 6/.

(CISlot 5. If the I$8 is not detected) !oun can manuall! select the slot.

(rimar! I$8 I1TR) Secondar! I$8 I1TR. Assigns @ I1T channels for

primar! and secondar! channels) if supported.

ISA. Assigns no I0s to (CI slots. *se for (CI I$8 cards that connect

I0s 6/ and 6D directl! from an ISA slot using a table from a legac!paddleboard.

PCI Bus Parin!. Sort of bus mastering- a device parking on the (CI Bus has

full control of the bus for a short time. Improves performance when that deviceis being used) but e3cludes others. Tr! with 1ICs and &ard $isk Controllers.

ID- Buffer for DOS J .in. #or I$8 read ahead and posted write buffers) so

!ou can increase throughput to and from I$8 devices b! buffering reads andwrites. Slower I$8 devices could end up slower) though.

ID- Master /Sla%e1 PIO Mode. Changes I$8 data transfer speed- Mode 7/

or Auto. (IO means (rogrammed Input+Output. 0ather than have the BIOSissue commands to effect transfers to or from the disk drive) (IO allows theBIOS to tell the controller what it wants) and then lets the controller and theC(* perform the complete task b! themselves. Modes 6/ are available.

HC9? PCIC9?. &ost C; vs (CI C; divider- A*TO) 66) 66.D.

PCI2IS, BC9? Di%ider. (CI Bus C; vs ISA Bus C; divider- A*TO

(CIC;6+) (CIC;6+@) (CIC;6+/.

CP6 to PCI Byte Mer!e. See B!te Merging for e3planation "below%.

PCI .rite2byte2Mer!e.


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is not used and the C(* read c!cle will not be completed until the (CI bussignals that it is read! to receive the data. The former is best for performance.

PCI2to2CP6 .rite Buffer. See above.

CP62to2PCI +ead29ine. uired if !ou add an Intel Over$riveprocessor to !our s!stem.

CP62to2PCI +ead2Burst. uential C(*memor! read c!cles addressed to the (CI will be translated into fast (CI burstmemor! c!cles. (erformance is improved) but some nonstandard (CI adapters"e.g. 9HA% ma! have problems.

PCI to D+,M Buffer. Improves (CI to $0AM performance b! allowing

data to be stored if a destination is bus!.Buffers are needed because the (CIbus is divorced from the C(*.

9atency for CP6 to PCI write. $ela! time before C(* writes data to the (CI

bus.

PCI Cycle Cache Hit .S. Similar to above.


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PCI Master 9atency. If !our (CI Master cards control the bus for too long

there is less time for the C(* to control it. A longer latenc! time gives theC(* more of a chance. $on,t use =ero.

Max burstable ran!e. The ma3imum bursting length for each #0AM8R

asserting. #0AM8R is an electrical signal. $unno what it does) !et.

CP6 to PCI burst memory write. If enabled) backtoback se>uential C(*

memor! write c!cles to (CI are translated to (CI burst memor! write c!clesOtherwise) each single write to (CI will have an associated #0AM8Rse>uence. 8nabled is best for performance) but some nonstandard (CI cards"e.g. 9HA% ma! have problems.

3ast Bac To Bac. (ossibl! as above) but working on itP

CP6 to PCI post memory write. 8nabling allows up to / $words of data to

be posted to (CI. Otherwise) not onl! is buffering disabled) completion oC(* writes is limited "e.g. C(* write does not complete until the (CItransaction completes%. 8nabled is best for performance.

CP6 to PCI .rite Buffer. As above. Buffers are needed because the (CI bus

is divorced from the C(*- the! improve overall s!stem performance b!allowing the processor "or bus master% to do what it needs without writing datato its final destination- the data is temporaril! stored in fast buffers.

PCI to IS, .rite Buffer.


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9ocal Memory @2@'M. To increase performance) !ou can map slower device

memor! "e.g. on the ISA bus% into much faster local bus memor!. ocalmemor! is set aside and the start point transferred from the device memor! tolocal memor!. The default is enabled.

@2@'M Memory 9ocation. The area in the memor! map allocated for ISA

option 0OMs. Choices are ocal "default% or 1onlocal.

Byte Mer!in!. This e3ists where writes to se>uential memor! addresses are

merged into one (CItomemor! operation) which increases performance forolder applications that write to video memor! in b!tes rather than wordsnotsupported on all (CI video cards. 8nable unless !ou get bad graphics. See alsone3t for a variation.

Byte Mer!e Support. or 6bit data en route from the C(* to the (CI bus

is held in a buffer where it is accumulated) or merged) into @bit data) givingfaster performance. In this case) enabling means that C(*(CI writes are

buffered "Award%.

Multimedia Mode. 8nables or disables palette snooping for multimedia cards.

7ideo Palette Snoop. Controls how a (CI graphics card can 4snoop4 write

c!cles to an ISA video card,s colour palette registers. Snooping essentiall!means interfereing with a device.Onl! set to $isabled if'

An ISA card connects to a (CI graphics card through a 98SA connector

The ISA card connects to a colour monitor) and

The ISA card uses the 0AM$AC on the (CI card) and (alette Snooping "0AM$AC shadowing% not operative on (CI card.

PCI87F, Palette Snoop. Alters the 9HA palette setting while graphic signals

pass through the feature connector of (CI 9HA card and are processed b!M(8H card. 8nable if !ou have M(8H connections through the 9HA featureconnector- this means !ou can ad:ust (CI+9HA palettes. 9HA snooping isused b! multimedia video devices "e.g. video capture boards% to look ahead atthe video controller "9HA device% to see what color palette is currentl! in use

It is onl! in e3ceptional circumstances that !ou might ever need to enable this)so disable for ordinar! s!stems. "Award BIOS%.

Snoop 3ilter. Saves the need for multiple en>uiries to the same line if it was

in>uired previousl!.


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the same wa! that the first @; page of the # range is useable after boot up hasfinished.

P Piped ,ddress. $efault is $isabled

PCI ,rbiter Mode. $evices gain access to the (CI bus through arbitration

There are two modes) 6 "the default% and @. The idea is to minimi=e the time ittakes to gain control of the bus and move data. Henerall!) Mode 6 should besufficient) but tr! mode @ if !ou get problems.

Stop CP6 .hen 3lush ,ssert. See below.

Stop CP6 when PCI 3lush.


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7-S, Master Cycle ,DS


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9ocal memory chec point. Allows !ou to select between two techni>ues for

decoding and error checking local bus writes to $0AM during a memor!c!cle.

SlowK83tra wait state- better checking "default%.

#astK1o e3tra wait state used.

3+,M-< !eneration. uest to generate an I+O channel read! "IOC&0$?% signal.

7F, Type. This data is used when the video bios is being shadowed. TheBIOS uses this information to determine which bus to use. Choices areStandard "default%) (CI) ISA+98SA.

PCI Mstr Timin! Mode. This s!stem supports two timing modes) 7 "default%

and 6.

PCI ,rbit4 +otate Priority. T!picall!) the s!stem manages or arbitrates access

to the (CI bus on a firstcomefirstserved basis. ueue. I8O Cycle Post2.rite.


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State Machines. The chipset uses four state machines to manage specific C(*

and+or (CI operations. 8ach can be thought of as a highl! optimi=ed processcenter designed to handle specific operations. Henerall!) each operationinvolves a master device and the bus it wishes to emplo!. The four statemachines are'

C$% &aster to C$% 'us (CC)

C$% &aster to $C 'us (C$)

$C &aster to $C 'us ($$)

$C &aster to C$% 'us ($C)

8ach have the following settings'

Address 7


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writes will not be buffered and the C(* will be forced to wait until the write iscompleted.

CP6 +ead Multiple Prefetch. A prefetch occurs during a process "e.g

reading from the (CI or memor!% when the chipset peeks at the ne3instruction and actuall! begins the ne3t read. The Orion chipset has four readlines. A multiple prefetch means the chipset can initiate more than one prefetch

during a process. $efault is $isabled. CP6 9ine +ead Multiple. A line read means that the C(* is reading a ful

cache line.


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C$%CLK1*+ C$% see# 1*+ (Default)

C$%CLK3 C$% see#3

1, -h. 1, -h.

C$%CLK2 C$% see#2

MaxE Burstable +an!e. Sets the si=e of the ma3imum range of contiguousmemor! which can be addressed b! a burst from the (CI bus) a half or one ;.

IS, Bus Cloc 3reuency. Allows !ou to set the speed of the ISA bus in

fractions of the (CI bus speed) so if the (CI bus is operating at its theoreticalma3imum) Mh=) (CIC;+ would !ield an ISA speed of 66 Mh=.

/*1+ -h. (#efault)

$CCLK, uarter see# of the $C 'us

$CCLK3 One th!r# see# of the $C 'us

& Bit I8O +eco%ery Time. The recover! time is the length of time) measured

in C(* clocks) which the s!stem will dela! after the completion of aninput+output re>uest to the ISA bus) needed because the C(* is running fasterthan the bus) and needs to be slowed down. Clock c!cles are added to aminimum dela! "usuall! D% between (CIoriginated I+O c!cles to the ISA busChoices are from 6 to or C(* clocks. 6 is the default.

@' Bit I8O +eco%ery Time. As above) for 6 bit I+O. Choices are from 6 to /

C(* clocks. 6 is the default.

I8O +eco%ery Time. A programmed dela! which allows the (CI bus to

e3change data with the slower ISA bus without data errors. Settings are infractions of the (CI BC'

2 BCLK=Two BCLK (#efault)

, BCLK=Four BCLK

4 BCLK=5!"ht BCLK

12 BCLK=Twel6e BCLK

PCI Concurrency. 8nabled "default% means that more than one (CI device

can be active at a time "Award%. uires constant attention. This involvesturning on additional read and write buffering in the chipset. The (CI bus can


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also obtain access c!cles for small data transfers without the dela!s caused b!renegotiatiating bus access for each part of the transfer) so is meant to improve

performance and consistenc!.

PCI Streamin!. $ata is t!picall! moved to and from memor! and between

devices in discrete chunks of limited si=es) because the C(* is involved. Onthe (CI bus) data can be streamed) that is) much larger chunks can be moved

without the C(* being bothered. 8nable for best performance. PCI Burstin!. Consecutive writes from C(* will be regarded as a (CI Burst

c!cle. 8nable K best performance- some cards might not like it.

PCI /ID-1 Burstin!. As above) but this one enables burst mode access to

video memor! over the (CI bus. The C(* provides the first address) andconsecutive data is transferred at one word per clock. The device must support

burst mode.

Burst Copy2Bac Option.


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commands fall within the same address space) the c!cle will be automaticall!interpreted as a (CI command.

Master +etry Timer. This sets how long the C(* master will attempt a (CI

c!cle before the c!cle is unmasked "terminated%. The choices are measured in(CIC;s which the (CI timer. 9alues are 67 "default%) 6) / or (CIC;s.

PCI Pre2Snoop. (resnooping is a techni>ue b! which a (CI master can

continue to burst to the local memor! until a /; page boundar! is reachedrather than :ust a line boundar!.

CP68PCI .rite Phase. $etermines the turnaround between the address and

data phases of the C(* master to (CI slave writes. Choices are 6 C;"default% or 7 C;.

PCI Preempt Timer. This item sets the length of time before one (CI master

preempts another when a service re>uest has been pending.

D!sa'le# 8o ree&t!on (#efault)*

270 LCLKs $ree&t after 270 LCLKs






+ LCLKs $ree&t after + LCLKs

CP6 to PCI POST8B6+ST. $ata from the C(* to the (CI bus can be posted

"buffered b! the controller% and+or burst. This sets the methods.

(OST+CO1.B*0ST. (osting and bursting supported "default%.

1O18+1O18. 1either supported.

(OST+1O18. (osting but not bursting supported.

PCI C9?.


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CP6 cycle cache hit same point.


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6. $ispla! some basic information about the video card like its brand) videoBIOS version and video memor! available. Since the s!stem,s BIOS takes overthe (OST right after the video card BIOS) !ou will not have enough time toread the displa!ed information.

@. $ispla! the BIOS version and cop!right notice in upper middle screen. ?ouwill see a large se>uence of numbers at the bottom of the screen. This

se>uence is the BIOS identification line.. $ispla! memor! count. ?ou will also hear tick sounds if !ou have enabled i

"see Memor! Test Tick Sound section%./. If !ou have a (CI bus) the s!stem will attempt an initialisation of the cards and

will displa! the card,s name.D. Once the (OST have succeeded and the BIOS is read! to call the operating

s!stem "$OS) OS+@) 1T)


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N&$*# Fate 2 ,#$ -rrorN' Hate A@7 on the ke!board controller "7/@% is no

working.

N,ddress 9ine ShortN' 8rror in the address decoding circuitr!.

NCache Memory BadE Do ;ot -nable CacheN' Cache memor! is defective.

NCH2# Timer -rrorN' There is an error in timer @. Several s!stems have two

timers. NCMOS Battery State 9owN' The batter! power is getting low. It would be a

good idea to replace the batter!.

NCMOS Checsum 3ailureN ' After CMOS 0AM values are saved) a

checksum value is generated for error checking. The previous value is differenfrom the current value.

NCMOS System Options ;ot SetN' The values stored in CMOS 0AM are

either corrupt or none3istent.

NCMOS Display Type MismatchN' The video t!pe in CMOS 0AM is not theone detected b! the BIOS.

NCMOS Memory Si0e MismatchN' The ph!sical amount of memor! on the

motherboard is different than the amount in CMOS 0AM.

NCMOS Time and Date ;ot SetN' Self evident.

NDisette Boot 3ailureN' The boot disk in flopp! drive A' is corrupted

"virus%. Is an operating s!stem present

NDisplay Switch ;ot ProperN' A video switch on the motherboard must be

set to either color or monochrome. NDM, -rrorN' 8rror in the $MA "$irect Memor! Access% controller.

NDM, @ -rrorN' 8rror in the first $MA channel.

NDM, # -rrorN' 8rror in the second $MA channel.

N3DD Controller 3ailureN' The BIOS cannot communicate with the flopp!

disk drive controller.

NHDD Controller 3ailureN' The BIOS cannot communicate with the hard

disk drive controller.

NI;T+ @ -rrorN' Interrupt channel 6 failed (OST.

NI;T+ # -rrorN' Interrupt channel @ failed (OST.

N?eyboard -rrorN' There is a timing problem with the ke!board.

N?B8Interface -rrorN' There is an error in the ke!board connector.

NParity -rror N' (arit! error in s!stem memor! at an unknown address.

NMemory Parity -rror at xxxxxN' Memor! failed at the 33333 address.


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/2@*1 +eference ;umber/@'1 Halt on POST -rror

7 Off

6 On

/@A1 Initiali0e CMOS in e%ery boot

7 Off

6 On

/@&1 Bloc pins ## and #( of the eyboard controller

7 Off

6 On

/@1 Mouse support in BIOS8eyboard controller

7 Off

6 On

/#$1 .ait for 3@ if error found 7 Off

6 On

/#@1 Display floppy error durin! POST

7 Off

6 On

/##1 Display %ideo error durin! POST

7 Off

6 On/#(1 Display eyboard error durin! POST

7 Off

6 On

/#2#'1 BIOS Date Month/#A2#&1 BIOS Date Day/#2($1 BIOS Date "ear/(#2(1 Chipset Identification 8 BIOS ;ame/*@1 ?eyboard controller %ersion number

Second Identification 9ine

/@2#1 Pin number for cloc switchin! throu!h eyboard controller/(1 Indicates hi!h si!nal on pin switches cloc speed to hi!h or low


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& &igh

ow

/1 Cloc switchin! throu!h chipset re!isters

7 Off

6 On

/A2@$1 Port address to switch cloc hi!h/@#2@(1 Data %alue to switch cloc hi!h/@2@'1 Mas %alue to switch cloc hi!h/@&2#@1 Port address to switch cloc low/#(2#*1 Data %alue to switch cloc low/#'2#A1 Mas %alue to switch cloc low/#2(@1 Pin number for turbo switch

Third Identification 9ine

/@2#1 ?eyboard Controller Pin for cache control/(1 Indicates whether hi!h si!nal on cache control pin enables or disables cache

& 8nable

$isable

/1 Indicates if the hi!h si!nal if used on the eyboard controller pin

7 #alse 6 True

/A21 Cache control throu!h chipset re!isters

7 Cache control off

6 Cache control on

/@@2@#1 Port address to enable cache throu!h special port/@*2@1 Data %alue to enable cache throu!h special port/@A2#$1 Mas %alue to enable cache throu!h special port/##2#(1 Port address to disable cache throu!h special port/#2#'1 Data %alue to disable cache throu!h special port/#&2#1 Mas %alue to disable cache throu!h special port/(@1 Pin number for resettin! the (( memory controller/((1 BIOS modified fla! /Incremented each time BIOS is modified1


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Chan!in! "our Password

8nable !ou to change the active password. The default is no password.

+emember your password.rite it down somewhereAsk !ourself' $o Ireall! need to set a password to access m! s!stem and+or the BIOS "is !our

brother + sister + kid + emplo!ee + colleague that dangerous% If securit! is of someminor concern to !ou) disabled recommended.


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Standard CMOS setup) so in general !ou can e3pect !our s!stem to boot withoutproblems after selecting this.

,uto Confi!uration with Power2on Defaults


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consult !our motherboard manual. ook for a 4forget CMOS 0AM4 :umper. Setit. Tr! it again. If it still doesn,t boot) ask a friend or post to a computer hardwarenewsgroup. ?ou are permitted to panic.

Typematic +ate Pro!rammin!' $isabled recommended. It enables the

t!pematic rate programming of the ke!board. 1ot all ke!boards support thisThe following two entries specif! how the ke!board is programmed if enabled

Typematic +ate Delay /msec1' D77 ns recommended. The initial dela! before

ke! autorepeat starts) that is how long !ou,ve got to press a ke! before it startsrepeating.

Typematic +ate /Chars8Sec1' 6D. It is the fre>uenc! of the autorepeat i.e

how fast a ke! repeats.

,bo%e @ MB Memory Test' If !ou want the s!stem to check the memor!

above 6 MB for errors. Disabled recommendedfor faster boot se>uence. The&IM8M.S?S driver for $OS .@ verifies the 5MS "83tended Memor!Specification%) so this test is redundant. It is thus preferable to use the 5MStest provided b! &IM8M.S?S since it is operating in the real environmen"where user wait states and other are operational%.

Memory Test Tic Sound' 8nabled recommended. It gives an audio record

that the boot se>uence is working properl!. (lus) it is an aural confirmation of!our C(* clock speed+Turbo switch setting. An e3perimented user can hear ifsomething is wrong with the s!stem :ust be the memor! test tick sound. Sinces!stems have now much more memor! than before) this setting is not commonan!more.

Memory Parity -rror Chec' -nabled recommended. Additional feature to

test bit errors in the memor!. All "or almost all% (Cs are checking theirmemor! during operation.8ver! b!te in memor! has another ninth bit) thawith ever! write access is set in such wa! that the parit! of all b!tes is odd

8/10/2019

Documents

BIOS Tutorial and codes