Biometric Application Programming Interface for Java Card

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Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc.

Confidential and Proprietary

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Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc.

Sharad Kumar Sharad Kumar Freescale Semiconductor Pvt. Ltd.Freescale Semiconductor Pvt. Ltd.India Design CenterIndia Design [email protected]@freescale.com

DAC Workshop on Post-Silicon Debug: DAC Workshop on Post-Silicon Debug: Technologies, Methodologies, and Best-PracticesTechnologies, Methodologies, and Best-Practices

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Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MagniV, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.

Post Silicon Validation –GoalsPost Silicon Validation –Goals

• Supplement Pre-Silicon Verification with functional tests− IP Level−System tests (Use-cases and SoC performance)−Stress tests (Multi-core and I/O concurrent tests)

• Electrical Validation−Process, voltage, temperature, frequency sensitivities−Determine Core Fmax and Platform Fmax−Power measurement correlation to tester

• High Speed Signal Integrity−I/O characterization− Standards Compliance (PCI express, USB, DDR3 etc.)

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Post Silicon Validation – Must Support Post Silicon Validation – Must Support

• Tester Linkages− Convert speed hunted core patterns for use in tester environment.

Usually part of production patterns for part binning.−Methodology to take a core or IP test to the tester environment –

often needed for debug or part screening

• Early Customers−Early samples provided to customer when tester screening not

robust. Enable screening of early customer samples – 2-3 weeks after packaged part

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SoC Challenges: Several Facets of ComplexitySoC Challenges: Several Facets of Complexity

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SoC Challenges: Multi-threaded Multi-coresSoC Challenges: Multi-threaded Multi-cores

• Multi-core, multi-threaded cores• Arranged as clusters with shared L2 Cache• 3 DDR controller with Platform Cache shared with I/O

peripherals

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SoC Challenges: Complex, High-Speed SoC Challenges: Complex, High-Speed InterfacesInterfaces

• Large complex I/O blocks− PCIe, SRIO, SATA, USB, 10G ethernet

• Routed through 32 lanes of 10Ghz SERDES• Cores and I/O drive traffic to memory via common bus fabric

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Functional Validation – Cores and PlatformFunctional Validation – Cores and Platform

• Multi-Core, Multi-thread Validation− Coherency at different levels − Memory ordering, dual-thread, livelock and deadlock scenarios− Validation through directed tests and random instruction tests

• Challenge is Debug!− Hardware support § Real time instruction, data traces§ Triggering LSRL dumps from functional conditions

− Ability to cross-run between simulation, emulation and post silicon§ Common tooling

− Need for validation§ Checking granularity tuning, self-checking§ Techniques such as QED (http://www.src.org/library/research-catalog/2136.001/#tab-summary)

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Functional Validation – IP, System and StressFunctional Validation – IP, System and Stress

• Use directed tests and random tests

• Measure feature coverage (coverage from random test case generation)

• Different tests than verification

• Run typical use-Run typical use-cases – domain cases – domain specific (networking, specific (networking, wireless etc.)wireless etc.)

• Different than Linux Different than Linux or complex OS or complex OS based runs – Driven based runs – Driven by debug, by debug, reproducibilityreproducibility

IP testingIP testing System testsSystem tests

• Run selected Run selected “randomly “randomly generated”generated” tests for tests for individual IP individual IP concurrentlyconcurrently

• Mix IP and Core Mix IP and Core tests, run for long tests, run for long duration duration

• Run mix of use-case Run mix of use-case and random testsand random tests

Stress TestsStress Tests

Debug Methods:• Logic Analyzers• Protocol Analyzers• SoC debug features – Real time trace,

LSRL, performance counters, debug registers etc.

• Software code based schemes

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Electrical ValidationElectrical Validation

• Shmoo IP, system and stress tests across voltage, frequency, temperatures across various matrix parts (slow, fast etc.)

• New technology node (28nm or smaller) , asynchronous logic.

• Debug − Similar to functional failure debug− Need additional schemes like on-

chip clock control to vary internal frequency, adjust cycle, phase width etc.

• Challenge− How many parts per process

corner to run on board?

V

Freq

FP P P P

FP P P P

FP P P F

FP P F F

V

Freq

V

Freq

V

Freq

V

Freq

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Emulation LinkagesEmulation Linkages

• Accelerate pre-silicon Accelerate pre-silicon verificationverification− Secure boot from internal ROM

• Debug Silicon failureDebug Silicon failure− Run and debug post-silicon tests

(500Khz to 1MHz)− Validate RTL fixes for silicon re-

spins- performance and functional• Develop post silicon testsDevelop post silicon tests

− Use a mix of software simulators and emulator for test-case development

• Use emulator as a virtual Use emulator as a virtual testertester− Get patterns ready for silicon.

Usually slow on traditional simulators

• Pattern GenerationPattern Generation− BIST & other DFT patterns− Cache error injection patterns

FunctionalFunctional TesterTester

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Tester Pattern Generation: Soft FlowTester Pattern Generation: Soft Flow

• Flow− Required test executable (.elf) is post

processed to generate a template− Template macros have equivalent

simulation VCDs (pre-generated)− VCD macros stitched together to

create a complete test− VCD converted to tester pattern

• Advantages− Pattern generated through scripts− No LA capture, no additional visibility

mode in SoC, or board design− Easy to debug

C:'$; SYSCFGP:Atpb_WR32_22(#8400,#FF72,#0100,#FFFC,#0000);C:'$; RUN_COREP:Atpb_WR32_22(#8400,#FF70,#1010,#0100,#0000);C:'$; EXPECTED(READ CHECK)P:Atpb_RD32_56(#8c00,#FFFF,#FFE0,#BE7E,#261A);

P:Atpb_WR32_22(#8400,#FF72,#0100,#FFFC,#0000);

P:Atpb_RD32_56(#8c00,#FF72,#0100,#FFFC,#0000);

Debug Read command added to check writeDebug Read command added to check write

command_command_<#bits>_<#clock cycles><#bits>_<#clock cycles>

address, data pairaddress, data pair

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Post Silicon Validation – Goal is to find issuesPost Silicon Validation – Goal is to find issues

• Coverage collection is important, but also record:− Fails, percentage of fails− Dates of failure, test-card where failure occurs− ECID of the parts that fail – may point to certain process tuning− Other hardware, software, setup related things

Device Points Passes Fails %Pass %Fail %Fails / hits

Sum Fails

Sum Passes

IP_0 159 159 68 100 42 0.47 1392 292982

IP_1 517 504 99 97 19 0.18 1786 993784

IP_2 514 504 71 98 13 0.03 361 1385144

• Though processes are mature and provide the hooks, engineer attitude matters in chasing down difficult bugs!

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Post Silicon Validation: Why do some problems Post Silicon Validation: Why do some problems escape?escape?• Industry wide challenge

−Software, hardware, system complexity increasing exponentially −How much validation is enough? § Coverage methodology

• Aggressive customer expectations. Typical requirements:§ Provide samples within 2 weeks of first silicon§ All related collateral like design documentation, coverage logs

FPP

Pre-Silicon Post-Silicon

Validation

FPP

Pre-Silicon Post-Silicon

Validation

> 2 years back Now

• Verification and Validation methods and strategies must keep up. New ones need to be devised.

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Biometric Application Programming Interface for Java Card