Basic Verilog programs file completely verified and correct simulation results using Modelsim Simulator and xilinx syntheser
Text of Basic Verilog Programs file
Verilog Lab 2012
EXPERIMENT NO. 1AIM:To write a VERILOG code for a master slave D-flip flop & simulate the code using Modelsim simulator.
Block Diagram & Schematic:-
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Verilog Lab 2012FUNCTIONAL DESCRIPTION :A masterslave D flip-flop is created by connecting two gated D latches in series, and inverting the enable input to one of them. It is called masterslave because the second latch in the series only changes in response to a change in the first (master) latch. VERILOG CODE : Module for D Flipflip module dff(d,clk,rst, q,qbar); input d,clk,rst; output q,qbar; reg q,qbar; always @(posedge clk or negedge rst) begin if(!rst) begin q