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ECE 545—Digital System Design with VHDLLecture 1A

Digital Logic RefresherPart A – Combinational Logic Building Blocks

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Lecture Roadmap – Combinational Logic

• Basic Logic Review• Basic Gates• De Morgan’s Laws

• Combinational Logic Building Blocks• Multiplexers• Decoders, Demultiplexers• Encoders, Priority Encoders• Multipliers• Shifters, Rotators

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Textbook References

• Combinational Logic Review

• Stephen Brown and Zvonko Vranesic,

Fundamentals of Digital Logic with VHDL Design, 3rd or 2nd Edition

§ Chapter 2 Introduction to Logic Circuits (2.1-2.8 only)

§ Chapter 6 Combinational-Circuit Building Blocks (6.1-6.5 only)

• OR your undergraduate digital logic textbook (chapters on combinational logic)

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Basic Logic Review

some slides modified from:S. Dandamudi, �Fundamentals of Computer Organization and Design�

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Rules• If you believe that you know a correct

answer, please raise your hand• I will select one or more students

(independently whether an answer given by the first student is correct or incorrect)

• Please, identify yourself by first nameand give an answer

• Correct answer = 1 bonus point

Problem 1

List all 2-input logic gates that you can recall

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Basic Logic Gates (2-input versions) Problem 2

How would you generalize the definitionsof 2-input logic gates to N-input logic gates?

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Basic Logic Gates Generalized

• Simple logic gates• AND à 0 if one or more inputs is 0, 1 otherwise• AND à 1 if all inputs are 1, 0 otherwise• OR à 1 if one or more inputs is 1, 0 otherwise• OR à 0 if all inputs are 0, 1 otherwise• NAND = AND + NOT

• 1 if one or more inputs is 0, 0 otherwise• 0 if all inputs are 1, 1 otherwise

• NOR = OR + NOT• 0 if one or more input is 1, 1 otherwise• 1 if all inputs are 0, 0 otherwise

• XOR à 1 if an odd number of inputs is 1, 0 otherwise• XNOR à 1 if an even number of inputs is 1, 0 otherwise

• NAND and NOR gates require fewer transistors than AND and OR in standard CMOS

Problem 3

How many 2-input logic functions can be theoretically defined (whether they make sense or not)?

How many N-input logic functions can be theoretically defined (whether they make sense or not)?

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Number of Functions

• Number of functions• With N logical variables, we can define

22N functions• Some of them are useful

• AND, NAND, NOR, XOR, …• Some are not useful:

• Output is always 1• Output is always 0

• �Number of functions� definition is useful in proving completeness property

Problem 4List all 1-input logic gates.

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Problem 5

What is a minimum set of gates that can be used to implement any logic function?

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Complete Set of Gates

• Complete sets• A set of gates is complete

• if we can implement any logic function using only the type of gates in the set

• Some example complete sets• {AND, OR, NOT} Not a minimal complete set• {AND, NOT}• {OR, NOT}• {NAND}• {NOR}

• Minimal complete set• A complete set with no redundant elements.

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NAND as a Complete Set

• Proving NAND gate is universal

Problem 6

List four ways of expressing logic functions.

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Logic Functions

• Logic functions can be expressed in several ways:• Truth table• Logical expressions• Graphical schematic form • HDL code

• Example:• Majority function

• Output is one whenever majority of inputs is 1• We use 3-input majority function

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Alternative Representations of Logic Function

Truth table

A B C F

0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1

Logical expression formF = A B + B C + A C

Graphical schematic form

F <= (A AND B) OR (B AND C) OR (AAND C) ;HDL code:

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Boolean Algebra

Boolean identitiesName AND version OR versionIdentity x.1 = x x + 0 = xComplement x. x’ = 0 x + x’ = 1Commutative x.y = y.x x + y = y + xDistribution x. (y+z) = xy+xz x + (y. z) =

(x+y) (x+z)Idempotent x.x = x x + x = xNull x.0 = 0 x + 1 = 1

Problem 7

Prove the OR version of the BooleanDistribution identity:

x + (y ∙ z) = (x+y) ∙ (x+z)

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Boolean Algebra (cont�d)

• Boolean identities (cont�d)Name AND version OR version

Involution x = (x�)� ---Absorption x. (x+y) = x x + (x.y) = xAssociative x.(y. z) = (x. y).z x + (y + z) =

(x + y) + z

Problem 8

What are the De Morgan’s Laws?Write their equations and draw their schematic representation.

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De Morgan’s Laws

Name AND version OR version

de Morgan (x. y)� = x� + y� (x + y)� = x� . y�

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Alternative symbols for NAND and NOR

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Deriving Equivalent Expressions

• Using NAND gates• Get an equivalent expression

A B + C D = (A B + C D)��• Using de Morgan�s law

A B + C D = ( (A B)� . (C D)�)�• Can be generalized

• Example: Majority function

A B + B C + AC = ((A B)� . (B C)� . (AC)�)�

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Majority Function Using AND, OR, NOT

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Majority Function Using NAND

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Majority Function Using NAND

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Combinational Logic Building Blocks

Some slides modified from:S. Dandamudi, �Fundamentals of Computer Organization and Design�

S. Brown and Z. Vranesic, "Fundamentals of Digital Logic"

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Problem 9

How many select inputs does an 8-to-1 MUX have?

How many select inputs does an n-to-1 MUX have?

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Multiplexers

• multiplexer• n binary inputs (binary input = 1-bit input)• log2n binary selection inputs• 1 binary output• Function: one of n inputs is placed onto output• Called n-to-1 multiplexer

n inputs 1 output

log2n selection inputs

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2-to-1 Multiplexer

(a) Graphical symbol

f

s

w0w1

0

1

(b) Truth table

01

f

fs

w0

w1

(c) Sum-of-products circuit

sw0w1

(d) Circuit with transmission gates

w 0

w 1 f

s

Source: Brown and Vranesic 34

4-to-1 Multiplexer

f

s 1

w 0 w 1

0001

(b) Truth table

w 0 w 1

s 0

w 2 w 3

1011

0 0 1 1

1 0 1

f s 1

0

s 0

w 2 w 3

f

(c) Circuit

s 1

w 0

w 1

s 0

w 2

w 3

(a) Graphic symbol

Source: Brown and Vranesic

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Multi-bit 4-to-1 Multiplexer

• When drawing schematics, can draw multi-bit multiplexers• Example: 8-bit 4-to-1 multiplexer

• 4 inputs (each 8 bits)• 1 output (8 bits)• 2 selection bits

• Can also have multi-bit 2-to-1 muxes, 16-to-1 muxes, etc.

f

s 1

w 0 w 1

0001

(b) Truth table

w 0 w 1

s 0

w 2 w 3

1011

0 0 1 1

1 0 1

f s 1

0

s 0

w 2 w 3

(a) Graphic symbol

8

8

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8-bit 4-to-1 Multiplexer

f(7)

s 1

0001

s 0

1011

f(6)

s 1

0001

s 0

1011

f(0)

s 1

0001

s 0

1011

w0(7)w1(7)w2(7)w3(7)

w0(6)w1(6)w2(6)w3(6)

w0(0)w1(0)w2(0)w3(0)

An 8-bit 4-to-1 multiplexer is composedof eight [1-bit] 4-to-1 multiplexers

f

s 1

w 0 w 1

0001

s 0

w 2 w 3

1011

8

8=

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Problem 10

How many outputs does a decoder with two data inputs have?

How many outputs does a decoder with n data inputs have?

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Decoders

• Decoder• n binary inputs• 2n binary outputs• Function: decode encoded information

• If enable=1, one output is asserted high, the other outputs are asserted low• If enable=0, all outputs asserted low

• Often, enable pin is not needed (i.e. the decoder is always enabled)• Called n-to-2n decoder

• Can consider n binary inputs as a single n-bit input• Can consider 2n binary outputs as a single 2n-bit output

• Decoders are often used for RAM/ROM addressing

n-1

w 0

ninputs

EnEnable

2 n outputs

y 0

w y 2 n 1 –

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2-to-4 Decoder

0 0 1 1

1 0 1

y 3 w 1

0

w 0

(c) Logic circuit

w 1

w 0

- -

1 1

0

1 1

En

0 0 1

0

0

y 2

0 1 0

0

0

y 1

1 0 0

0

0

y 0

0 0 0

1

0

y 0

y 1

y 2

y 3

En

w 1

En

y 3 w 0 y 2

y 1 y 0

(a) Truth table (b) Graphical symbol

Source: Brown and Vranesic

Problem 11

Show how to implement a decoder that recognizes the following 4 ranges of a 16-bit address A, and generates the corresponding enable signals e0,e1,e2,e3:

For A in: AssertC000-CFFF: e0D000-DFFF: e1E000-EFFF: e2F000-FFFF: e3

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Demultiplexers

• Demultiplexer• 1 binary input• n binary outputs• log2n binary selection inputs• Function: places input onto one of n outputs, with the remaining outputs asserted low• Called 1-to-n demultiplexer

• Closely related to decoder• Can build 1-to-n demultiplexer from log2n-to-n decoder by using the decoder's enable

signal as the demultiplexer's input signal, and using decoder's input signals as the demultiplexer's selection input signals.

n outputs1 input

log2n selection inputs

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1-to-4 Demultiplexer

Problem 12

How many inputs does an encoder with two data outputs have?

How many inputs does an encoder with n data outputs have?

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Encoders

2 n inputs

w 0

y 0

y n 1 –

n outputs

• Encoder• 2n binary inputs• n binary outputs• Function: encodes information into an n-bit code• Called 2n-to-n encoder

• Can consider 2n binary inputs as a single 2n-bit input• Can consider n binary output as a single n-bit output

• Encoders only work when exactly one binary input is equal to 1

w 2 n 1 –

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4-to-2 Encoder

0 0 1 1

1 0 1

w 3 y 1

0

y 0

(b) Circuit

w 1

w 0

0 0 1

0

w 2

0 1 0

0

w 1

1 0 0

0

w 0

0 0 0

1

y 0

w 2

w 3 y 1

(a) Truth table

Problem 13

What is a difference between encoder and priority encoder?

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Priority Encoders

2 n inputs

w 0

w 2 n 1 –

y 0

y n 1 –

n outputs

• Priority Encoder• 2n binary inputs• n binary outputs• 1 binary "valid" output• Function: encodes information into an n-bit code based on priority of inputs• Called 2n-to-n priority encoder

• Priority encoder allows for multiple inputs to have a value of '1', as it encodes the input with the highest priority (e.g., MSB = highest priority, LSB = lowest priority)

• "valid" output indicates when priority encoder output is valid• Priority encoder is more common than an encoder

z "valid" output

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4-to-2 MSB Priority Encoder

-001

010

w0 y1

-

y0

1 1

01

1

11

z

1--

0

-

w1

01-

0

-

w2

001

0

-

w3

000

0

1

Problem 14

Show how to implement a 4-to-2 MSB Priority Encoder using multiplexers anda minimum number of logic gates

Problem 15

What is the width of an output of a 4x4 unsigned multiplier?

What is the width of an output of a 4x4 signed multiplier?

What is the width of an output of a NxN unsigned multiplier?

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4x4-bit Unsigned Multiplier

4 4

a b

8

c*

U

10

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4x4-bit Signed Multiplier

4 4

a b

8

c S

*

Problem 16

What is the width of an output of a 4x8 unsigned multiplier?

What is the width of an output of a 4x8 signed multiplier?

What is the width of an output of a NxM unsigned multiplier?

Problem 17

Give an example of binary inputs to an unsigned 4x4 multiplier and a signed 4x4 multiplierthat produce different results.

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Unsigned vs. Signed Multiplication

1111 1111x

11100001

1515x

225

1111 1111x

00000001

-1-1x

1

Unsigned Signed

Problem 18

Explain the difference between logic shift rightand arithmetic shift right

What arithmetic operations these shifts correspond to?

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Logical Shift Right

A(3) A(2) A(1) A(0)

�0� A(3) A(2) A(1)

A

C

4

4

A

C>>1

L

11

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Arithmetic Shift Right

A(3) A(2) A(1) A(0)

A(3) A(2) A(1)

A

C

4

4

A

C>>1

A(3)

A

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Fixed Rotation

A(3) A(2) A(1) A(0)

A(2) A(1) A(0) A(3)

A4

4

A

C<<< 1

C

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8-bit Variable Rotator Left

8

8

3

A

B

C

A <<< B

Explain using simple diagrams (based on medium-scale logic components)how to efficiently perform the followingoperations in hardware using combinationallogic only

A. C = A <<< 3B. C = A <<< B,

where A and C are 16-bit variablesand B is a 4-bit variable

Problem 19

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Fixed rotation C = A <<< 3

a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0)

a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13)

<<< 3 Variable rotation C = A <<< B