(Baremetal Flow) AN-755 Subscribe Send … Clock to ADCs FMC Port A AD9680 JESD204B Subclass 1 Control SPI Control 4 device_clk Core PLL Reference Clock TX/RX Transceiver PLL Reference

Implementing JESD204B IP Core System ReferenceDesign with ARM HPS As Control Unit

(Baremetal Flow)2015.12.30

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The Altera® JESD204B IP core is a high-speed point-to-point serial interface for digital-to-analog (DAC)or analog-to-digital (ADC) converters to transfer data to or from the FPGA devices.

The JESD204B IP core is part of the IP Catalog library, which is distributed with the software anddownloadable from the Altera website.

This reference design demonstrates the JESD204B IP core operating as part of a system that includes:

• Altera JESD204B transport layer (assembler and deassembler)• test pattern generator and checker• core PLL• Serial Parallel Interface (SPI) – Master module• reset sequencer• various dynamic reconfiguration controllers• ARM® hard processor subsystem (HPS) as the control unit

The key feature of this reference design is the software-based control flow that utilizes the ARM HPScontrol unit.

The reference design utilizes the Arria V SoC Development Kit to interoperate with the Analog Devices(ADI) AD9680 ADC daughter card that connects to the development board.

Related Information

• Reference Design ZIP File for AN 755• JESD204B IP Core User Guide• Quartus Prime Handbook Volume 1: Design and Synthesis

For detailed description of the reset sequencer module.• Altera Transceiver PHY User Guide• Arria V Hard Processor System Technical Reference Manual• Altera SoC Embedded Design Suite User Guide• Embedded Peripherals IP User Guide• ADI AD9680 ADC Datasheet• ADI AD9516 Clock Module Datasheet

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Reference Design OverviewThis reference design is implemented on the Arria V SoC development board interoperating with the ADIAD9680 ADC converter card.

Figure 1: JESD204B Reference Design with ARM HPS Control Unit Block Diagram

Figure shows a system level block diagram of the JESD204B system reference design with the ARM HPScontrol unit.

ExternalClock Source

PatternGenerator

Avalon-STUser Data

Avalon-ST User Data

Test PatternGenerator

Test PatternChecker

Top-Level Qsys Systemjesd204b_ed_soc.qsys

Assembler(Transport

Layer)

ARM HPSand

Peripherals

Deassembler(Transport

Layer)

JESD204Subsystem

SPI

Core PLLframe_clk

frame_clklink_clk

Cold Reset

ARM HPS Reset

Warm ResetDebug Reset

Arria V Device (5ASTFD5K3F40I3)

Top-Level HDL (jesd204b_ed.sv)

fpga_clk_50

Arria V SoC Development Board

153.6 MHz

614.4 MHz

AD9516

SMA

ClocktoADCs

FMCPort A

AD9680

JESD204BSubclass 1 Control

SPI Control4

device_clkCore PLLReference Clock

TX/RXTransceiver PLLReference Clock

sysrefsync_n

JESD204BInterface

ADC

ADC

Lane 0

Lane 1

Lane 2

Lane 3

Avalon-ST

Avalon-ST

Avalon-ST 32 Bitper transceiver

lane


lane

50 MHzISSP

EdgeDetect

The reference design consists of these components and sub components:

• Qsys system:

• ARM HPS control unit and various processor peripherals• JESD204B subsystem• SPI master module

• Top level HDL:

• Core PLL• In-system source and probes (ISSP)• Edge detectors• Altera transport layer (assembler and deassembler)• Test pattern generator and checker

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• ARM HPS control unit—generates a one-shot SYSREF pulse for the JESD204B IP core and theAD9680 module (for Subclass 1 mode compliance).

• device_clk (153.6 MHz) clock signal sourced from the AD9516 external clock module—acts as thereference clock for the on-chip core PLL and transceiver PHY PLL.

• Core PLL module—generates the link clock (link_clk) and frame clock (frame_clk).• Oscillator on-board the Arria V SoC development board—supplies a 50 MHz clock (fpga_clk_50) to

clock the control plane.• Altera In-System Source and Probes (ISSP) module instantiated in the top level HDL—generates the

following resets for the ARM HPS control unit:

• Cold reset• Warm reset• Debug reset

• Edge detect module instantiated in the top level HDL—shapes the reset pulses generated by the ISSPmodule to meet the ARM HPS reset pulse width requirements.

• AD9516 external clock module

• Supplies a 614.4 MHz clock to the ADCs on the AD9680 module via an SMA connector.• Supplies a 153.6 MHz reference clock to the FPGA via an SMA connector on the AD9680 module.

The reference clock is passed through from the AD9680 module to the FPGA via the FMCconnector.

• You can replace this module with any external clock module that supplies a 614.4 MHz and 153.6MHz reference clock.

• AD9680 module

• Configuration of the AD9680 converter parameters is through a 4-wire SPI master module viaFMC connector.

• Configured to transmit on 4 high-speed transceiver lanes (L=4) to the FPGA.• Each lane is configured to 6.144 Gbps data rate.• Passes through the FPGA reference clock (device_clk) from the AD9516 clock module to the FPGA

via the FMC connector.

Table 1: System Clocking

This table summarizes the system clocking of the reference design.

Clocks Description Source Modules Clocked

device_clk Reference clock for thedata path

External Core PLL, transceiver PHY PLL

link_clk Link layer clock device_clk JESD204B IP core link layer, transport layerlink interface

frame_clk Frame layer clock device_clk Transport layer, test pattern generator andchecker, downstream modules

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Clocks Description Source Modules Clocked

fpga_clk_50 Control plane clock External ARM HPS control unit and any peripheralsconnected to ARM HPS via Avalon-MM/AXIbus interconnect

Related InformationJESD204B IP Core User GuideFor more information about the JESD204B system clocking.

Getting Started

Hardware and Software RequirementsThis reference design uses the following hardware and software tools:

• Arria V SoC development kit• ADI AD9680 ADC converter card• ADI AD9516 clock module• Quartus® Prime software version 15.1• Altera SoC Embedded Design Suite (EDS) with ARM DS-5 Altera Edition tool

Hardware Setup1. Install the ADI AD9680 converter card module to the FMC port A (J26) on the Arria V SoC develop‐

ment board.2. Connect the USB cable to the USB-Blaster® II connector on the development board.3. Connect the power adapter shipped with the development board to the power supply jack (J34).4. Connect the AD9516 power adapter to the power supply jack on the AD9516 clock module card.5. Connect the USB cable from your workstation to the USB connector on the AD9516 card.6. Connect the AD9516 clock module OUT0 SMA connector (J0A) to the CLKIN SMA connector (J801)

on the AD9680 card.7. Connect the AD9516 clock module OUT8 SMA connector (J8A) to the Refclk to FPGA SMA

connector (J804) on the AD9680 card.8. Turn on the power for the AD9516 clock module card.9. Configure the clock settings of the AD9516 to output 614.4 MHz clock for the ADCs at OUT0 SMA

connector and 153.6 MHz for the FPGA at OUT8 SMA connector. Refer to the AD9516 documenta‐tion for more information on configuring the AD9516 clock module.

10.Turn on the power for the Arria V SoC development board.

The hardware system is now ready for programming.

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Compiling the HDL and Programming the Board1. Extract the reference design from the reference design ZIP file (jesd204b_av_soc_ref_design.zip).2. Launch the Quartus Prime software.3. On the File menu, click Open Project.4. Navigate to your project directory and select the Quartus project archive file (jesd204b_ed.qar). Click

Open.5. In the Restore Archived Project window, verify that the archive file name is jesd204b_ed.qar and set

the destination folder to the destination folder of your choice. Click OK. The Quartus project opens inthe Quartus window.

6. To compile the HDL, navigate to the Processing menu and select Start Compilation. The Quartussoftware compiles the design and indicates the compilation status in the Tasks panel.

7. After compilation is done, you are ready to program the FPGA device with the programming file.Navigate to the Tools menu and click Programmer.

8. In the Programmer window, click Add File.9. In the Select Programming File window, navigate to <your project directory>/output_files/jesd204b_

ed.sof and click Open.10.Verify that all the hardware setup options are set correctly to your system configurations.11.Click Start to download the file into the Arria V SoC device on the development board. Alternatively,

if you want to use the pre-generated golden programming file, skip the Quartus compilation in step 6.In step 9, select <your project directory> output_files/jesd204b_ed_golden.sof and proceed accordingly.

After programming the Arria V SoC device on the development board, the system needs to be initializedvia software before the JESD204B link can be fully active.

Attention: Do not skip this initialization step. The JESD204B link will not function correctly withoutsoftware link initialization.

Setting up the Software Command Line Environment1. Create a software workspace in a project directory of your choice. For ease of reference, this document

will assume the software workspace name of <your project directory>/software.2. Launch the SoC EDS ARM DS-5 Altera Edition tool.3. In the Select a workspace dialog box, navigate to the software workspace, <your project directory>/

software and click OK.4. Import the software archive project into your workspace. On the File menu, click Import.5. In the Import/Select window, select General > Existing Projects into Workspace and click Next >.6. In the Import/Import Projects window, check the Select archive file radio button.7. Browse to the software archive project location, select the archive project file, jesd204b_soc_baremetal_

gnu.tar.gz and click OK. The software archive project file is in the location where you unzipped thereference design, jesd204b_av_soc_ref_design.zip.

8. Verify that the jesd204b_soc_baremetal_gnu check box is checked in the Projects panel and clickFinish. The ARM DS-5 tool restores the archived software project into your workspace.

9. In the Project Explorer tab of the main Eclipse window, expand the jesd204b_soc_baremetal_gnuproject file list and verify that you see all the files listed in the Reference Design Files section.

10.To compile the source code, right-click on the jesd204b_soc_baremetal_gnu project in the ProjectExplorer tab and select Build Project. This action executes the software build project Makefile.

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11.When recompiling the source code after the first compile, right-click on thejesd204b_soc_baremetal_gnu project and select Clean Project before building the project. This clearsthe project workspace of object files and other project executables from the previous project build.

12.Whenever you add or remove any *.c source files from the project, in addition to adding or removingthe file from the Project Explorer window, you must update the source file list in the software buildproject Makefile accordingly. To update the source file list in the Makefile, double-click the Makefilefile under the jesd204b_soc_baremetal_gnu project in the Project Explorer tab. In the Makefile editorwindow, locate the 'EXAMPLE_SRC' variable and add or remove your *.c source file from the list. Savethe file and proceed to build the project.

13.View the build project log in the Console tab and verify that there are no errors during the buildproject operation.

14.To download the project executable file to the ARM HPS and execute the code in semi-hosting debugmode, right-click on the jesd204b_soc_baremetal_gnu project in the Project Explorer tab and selectDebug As > Debug Configurations.

15.In the Debug Configurations window, on the left panel, select DS-5 Debugger >jesd204b_soc_baremetal_gnu. On the right panel, under the Connection tab, in the Select targetpanel, select Arria V SoC > Bare Metal Debug > Debug Cortex-A9_0. Ensure that all the otherconnections settings in the Connection tab are set according to your system configurations.

16.Click Debug. The tool downloads the executable code onto the ARM HPS and launches the Debuggerinterface.

17.Execution of the code is halted on the first executable line of the main.c code. To continue executionwithout interruption until the end of the code, click the Continue button in the Debug Controlwindow. To step through the code line by line, use the stepping buttons in the Debug Controlwindow.

The App Console window is the main user interface portal that you can view printed messages and entercommands to the main execution code.

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Figure 2: ARM DS-5 - App Console GUI

The main execution code executes the JESD204B link initialization sequence and prints a commandprompt for you to enter commands to the ARM HPS. View the printed messages from the JESD204B linkinitialization sequence in the App Console window. Verify that the link is initialized successfully and theTX/RX status registers display the expected values. Tables below describe the expected values of the linkstatus register report.

Table 2: TX Status 0 Register

Bit Name Description Expected Binary Value

[0] SYNC_N value 0: Receiver is not in sync

1: Link is in sync

1

[2:1] Data Link Layer (DLL)state

00: Code Group Synchronization (CGS)

01: Initial Lane Alignment Sequence (ILAS)

10: User data mode

11: D21.5 test mode

10

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Table 3: RX Status 0 Register

Bit Name Description Expected Binary Value

[0] SYNC_N value 0: Receiver is not in sync

1: Link is in sync

1

Others — — Don’t care

The code also reports the status of the pattern checker comparison. Any pattern checker errors that occurduring the initialization period is flagged to the console window. Verify that the console displays thismessage to indicate no pattern checker errors were detected:

INFO: No pattern checker error detected on link 0

Related Information

• Reference Design Files on page 18• User Commands on page 29

For more details on the user commands that you can issue to the ARM HPS control unit.• JESD204B IP Core User Guide

For more details on JESD204B TX/RX status registers.

Reference Design ComponentsThe reference design consists of the following components:

• Qsys system

• ARM HPS control unit and supporting processor peripherals• JESD204B subsystem

• Core PLL• Assembler and deassembler (in the transport layer)• Test pattern generator• Test pattern checker

Qsys SystemThe top level Qsys system (jesd204b_ed_soc.qsys) instantiates the following key components:

• ARM HPS control unit and supporting processor peripherals• JESD204B subsystem

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Figure 3: Qsys System Block Diagram

Base Layer PHY Layer (Transceiver)

TXCSR

RXCSRIRQ

jesd204b_system.qsys

JESD204B IP Core (Duplex)Serial Data To/FromExternal Converter

Avalon-MM BridgeReset

Sequencer

TransceivrReset Controller

Transceiver Reset

System Resets (3)

Transceiver Analog/Digital Resets

IRQ

4

To HPS IRQ In and ILC

Reset In

To All Peripherals Connectedto Avalon-MM Bridge

To HPS IRQ In and ILC

Avalon-MM Bridge

ARM HPSIRQ In

On-ChipMemory

ILC (4)

JTAG-to-AvalonMaster Bridge (10)



IRQ

H2F AXIMASTER (7)

H2F LW AXIMASTER (6)

H2FRESET (5)

F2H AXISLAVE (8)

F2H SDRAMDATA (9)

SYSID (1)

FPGAPIO (2)

PIO (2)

PIO (2)IRQ

JTAGUART

SPIMaster

To/From Terminal Console

To/From External ConverterSPI Interface

To FPGA Control Registers

To LEDs

From FPGA Status Registers

From Push Buttons, DIP Switches

jesd204b_ed_soc.qsys

Avalon Streaming(Avalon-ST) Interconnect

Interrupt Request SIgnals(IRQ)

Legend:Avalon Memory Mapped (Avalon-MM) or Advanced eXtensible Interface (AXI)Interconnect (11)

Notes:(1) System ID peripheral(2) Parallel I/O peripheral(3) System resets comprise of the following resets: Core PLL reset, JESD204B IP core transceiver PHY reset, TX/RX JESD204B IP core base layer CSR resets, TX/RX link resets, TX/RX frame resets(4) Interrupt latency counter(5) HPS-to-FPGA external reset output(6) Lightweight HPS-to-FPGA bridge AXI interface(7) HPS-to-FPGA bridge AXI interface(8) FPGA-to-HPS bridge AXI interface(9) FPGA-to-SDRAM data Avalon-MM interface(10) JTAG-to-Avalon master bridge to facilitate System Console interface for debug purposes(11) The ARM HPS communicates primarily via the Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) bus protocol whereas many Altera peripherals communicate via the Avalon Memory Mapped (Avalon-MM) bus protocol. Qsys automatically translates between the two protocols such that you can connect an Avalon-MM peripheral to the ARM HPS interface directly.

Avalon-ST 32 Bit DataPer Transceiver LaneTo/From Transport layer

The main data path flows through the JESD204B subsystem. In this reference design, the JESD204B IPcore is configured in duplex mode with both TX and RX data paths. On the TX data path, user data flowsfrom the transport layer through the JESD204B IP core base module via a 32-bit per transceiver laneAvalon® Streaming (Avalon-ST) interface and out as serial data to either the external converters or the RXdata path in internal serial loopback mode via the JESD204B IP core PHY module. On the RX data path,serial data flows from the external converters (or from the TX data path, in internal serial loopback mode)to the JESD204B IP core PHY module and out from the JESD204B IP core base module to the transportlayer via a 32-bit per transceiver lane Avalon-ST interface. Since the system is configured to 4 transceiverlanes (L=4), the total bit width of the Avalon-ST interface for both the TX and RX data paths is 128 bits.

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The control path is centered on the ARM HPS control unit that connects to various peripherals via theAdvanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) bus protocol.Altera processor peripherals primarily use the Avalon Memory-Mapped (Avalon-MM) protocol for busconnectivity. The Qsys tool automatically and seamlessly translates between the two protocols such thatyou can connect an Avalon-MM peripheral to the ARM HPS interface directly. An Avalon-MM bridgemodule provides a single memory-mapped interface between the ARM HPS lightweight HPS-to-FPGAbridge AXI interface and Avalon-MM peripherals implemented in the FPGA core fabric.

A secondary control path from the SPI master module links to the SPI configuration interface of theexternal converters via a 4-wire SPI interconnect. The configuration of the external converters is done bythe ARM HPS control unit writing configuration data to the SPI master module. The SPI master modulehandles the serial transfer of data to the SPI interface on the converter end via the 4-wire SPI interconnect.

To view the top level Qsys system in Qsys:

1. Launch the Quartus Prime software.2. On the File menu, click Open.3. Browse and select the jesd204b_ed_soc.qsys file located in the project directory.4. Click Open to view the Qsys system.

Top Level Qsys Address Map

You can access the address mapping of the submodules in the top level Qsys project by clicking on theAddress Map tab in the Qsys window.

Figure 4: Top Level Qsys Address Map

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The Qsys system supports multi-link scenarios (up to 4 links) using the existing address map. To addmore links to the system, add more jesd204b_system.qsys modules to the project, connect them to theAvalon-MM bridge, and adjust the address map accordingly. Bits 16-17 of the Avalon-MM bridge(0x0004_0000 base address) indicate the link number.

Related InformationImplementing a Multi-Link Design on page 53For more details on implementing multi-link designs.

ARM HPS Control Unit and Supporting Processor Peripherals

This section describes the following components:

• ARM HPS control unit• On-chip memory—provides general purpose data memory to the ARM HPS• System ID (sysid)—a simple read-only device that provides the system with a unique identifier. The

ARM HPS uses this module to verify that an executable program is compiled targeting the actualhardware image configured in the target FPGA.

• JTAG UART—transmits information between the ARM HPS and user console• External ports parallel I/O (PIO)—provides memory-mapped access to/from the ARM HPS from/to

external ports. There are three external port PIO modules in the system:

• fpga_dipsw_pio—4-bit input from on-board DIP switches• fpga_button_pio—4-bit input from on-board push buttons• fpga_led_pio—4-bit output to on-board LEDs

• FPGA core control and status parallel I/O (PIO)• SPI master module• Interrupt latency counter (ILC)—measures in clock cycles the time taken from the moment an

interrupt request (IRQ) signal is asserted until the interrupt service routine (ISR) begins• Avalon-MM bridge—provides single memory-mapped interface between the ARM HPS lightweight

HPS-to-FPGA bridge AXI interface and Avalon-MM peripherals in the FPGA core• JTAG-to-Avalon-Master bridge—facilitates System Console interface for debug purposes

ARM HPS Control Unit

The ARM HPS is configured with the following input resets enabled:

• Cold reset• Warm reset• Debug reset

The reset pulses to the ARM HPS are generated by the Altera In-System Sources and Probes (ISSP)module that is instantiated in the top level HDL file. The reset pulses are shaped by the edge detector unit(also instantiated in the top level HDL file) to meet the ARM HPS reset pulse specifications. The ARMHPS in turn generates an output reset signal to the FPGA core fabric via the HPS-to-FPGA external resetport (h2f_reset) and is used by the JESD204B subsystem reset sequencer.

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The ARM HPS communicates with the FPGA core fabric via a set of AXI bridges that are part of the HPS:

• HPS-to-FPGA bridge—64-bit master interface that interfaces to the on-chip memory• FPGA-to-HPS bridge—64-bit general purpose slave interface from the FPGA core fabric to ARM HPS• Lightweight HPS-to-FPGA bridge—32-bit master interface that connects to all Avalon-MM

peripherals that are implemented in the FPGA core fabric

The SDRAM interface protocol setting is configured to DDR3 operating at 533 MHz.

The following peripherals have their interrupt request (IRQ) output ports connected to the IRQ inputport of the ARM HPS (f2h_irq0):

• Push button input PIO module• DIP switch input PIO module• SPI master module• JESD204B IP core TX base layer• JESD204B IP core RX base layer• Reset sequencer

FPGA Core Control and Status PIO

The FPGA core control and status PIO modules provide general purpose I/O access to and from the ARMHPS for elements inside the FPGA core fabric. The FPGA control PIO is a 32-bit output signal from theARM HPS to the FPGA core fabric. The FPGA status PIO is a 32-bit input signal from the FPGA corefabric to the ARM HPS. The signal connectivity is set at the top level HDL file. The tables below describethe signal connectivity for the FPGA control and status registers.

Table 4: Signal Connectivity for FPGA Control Registers

Bit Signal

0 RX serial loopback enable for lane 0 (Link 0)




4-30 RX serial loopback enable for subsequent links, if present

31 Sysref

Table 5: Signal Connectivity for FPGA Status Registers

Bit Signal

0 Core PLL locked

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Bit Signal

1 TX transceiver ready (Link 0)

2 RX transceiver ready (Link 0)

3 Test pattern checker data error (Link 0)

4-31 TX transceiver ready, RX transceiver ready, and test pattern checker data error signals forsubsequent links, if present

SPI Master Module

The SPI master module is a 4-wire, 24-bit width interface that uses the SPI protocol to facilitate theconfiguration of external converters (for example, ADC, DAC, and external clock modules) via astructured register space provided inside the converter device. The SPI master module connects to theARM HPS via the Avalon-MM bridge. The ARM HPS sends the configuration instructions and data toexternal converters during the external converter configuration operation. The software instructions toexecute external converter configuration via the SPI interface is described in the Reference Design Softwaresection.

Related Information

• Reference Design Software• JESD204B IP Core User Guide• Arria V Hard Processor System Technical Reference Manual• Embedded Peripherals IP User Guide

JESD204B Subsystem

The JESD204B subsystem Qsys project (jesd204b_system.qsys) instantiates these modules:

• JESD204B IP core configured in duplex (with TX and RX data paths), non-bonded mode• Reset sequencer• Transceiver PHY reset controller• Avalon-MM bridge

The grouping of modules into a single Qsys subsystem project facilitates easy implementation of multi-link capabilities. For every link that you implement, a jesd204b_system.qsys project is instantiated in thetop level Qsys project and assigned an address as described in the Top Level Address Map section. You canreset and dynamically reconfigure each link independently.

Related InformationImplementing a Multi-Link Design on page 53For more details on implementing multi-link designs.

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JESD204B IP Core

The JESD204B IP core is configured in duplex (with TX and RX data paths), non-bonded mode with thefollowing parameter configuration:

Table 6: JESD204B IP Core Parameter Configuration

Parameter Value Description

Subclass 1 Subclass mode.

L 4 Number of lanes per converter device.

M 2 Number of converters per device.

F 1 Number of octets per frame.

S 1 Number of transmitted samples per converter per frame.

N 14 Number of conversion bits per converter.

N’ 16 Number of transmitted bits per sample.

K 32 Number of frames per multiframe.

CS 0 Number of control bits per conversion sample.

CF 0 Number of control words per frame clock period per link.

HD 0 High Density user data format.

SCR Off Enable scramble.

The JESD204B IP base core connects to the ARM HPS via the Avalon-MM bridge. There are two separateAvalon-MM ports for the JESD204B IP core:

• Base core TX data path—for dynamic reconfiguration of the TX CSR parameters.• Base core RX data path—for dynamic reconfiguration of the RX CSR parameters.

The ARM HPS writes to the JESD204B IP core CSR during a dynamic reconfiguration operation. Thesoftware instructions to execute dynamic reconfiguration of the JESD204B IP core are described in theUser Commands section.

To customize the JESD204B IP core parameters to meet your specifications, follow the instructions in theModifying JESD204B IP Core Parameters section.

Related Information

• User Commands on page 29For more details on the user commands that you can issue to the ARM HPS control unit.

• Modifying JESD204B IP Core Parameters on page 52

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Reset Sequencer

The reset sequencer is a standard Qsys component in the IP Catalog standard library. The reset sequencergenerates the following system resets to reset various modules in the system:

• Core PLL reset—resets the core PLL.• Transceiver reset—resets the JESD204B IP core PHY module.• TX/RX JESD204B IP core CSR reset—resets the TX/RX JESD204B IP core CSRs.• TX/RX link reset—resets the TX/RX JESD204B IP core base module and transport layer.• TX/RX frame reset—resets the TX/RX transport layer, downstream modules.

The reset sequencer has hard and soft reset options. The hard reset port connects to the ARM HPS-generated FPGA reset output signal (h2f_reset). The ARM HPS executes a soft reset by issuing the resetcommand to the Avalon-MM interface of the reset sequencer. When you assert a hard reset or issue thefull sequence reset command, the reset sequencer cycles through all the various module resets based on apre-set sequence. The figure below illustrates the sequence and also shows how the reset sequencer outputports correspond to the modules that are being reset.

Figure 5: Reset Sequence

reset_in0

reset_out0

reset1_dsrt_qual

reset_out1

Qualifying Condition

reset2_dsrt_qual

reset_out2

reset_out5

reset_out3

reset_out4

reset5_dsrt_qual

reset_out7

reset_out6

Global Reset

Core PLL

Core PLL Locked

Transceiver PHY

TX Transceiver Ready

JESD204B TX CSR

JESD204B RX CSR

TX Link Layer

TX Frame Layer

RX Transceiver Ready

RX Frame Layer

RX Link Layer

Reset Type Reset SequencerOutput



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Related InformationUser Commands on page 29For more details on the user commands that you can issue to the ARM HPS control unit.

Transceiver PHY Reset Controller

The transceiver PHY reset controller is a standard Qsys component in the IP Catalog standard library.This module takes the transceiver PHY reset output from the reset sequencer and generates the properanalog and digital reset sequencing for the transceiver PHY module.

Avalon-MM Bridge

All the Avalon-MM peripherals in the JESD204B subsystem connect via the Avalon-MM interconnect toa single Avalon-MM bridge. This bridge is the single interface for Avalon-MM communications into andout of the subsystem. This Avalon-MM bridge connects to the main Avalon-MM bridge in the top levelQsys system to connect to the ARM HPS control unit.

JESD204B Subsystem Address Map

You can access the address map of the peripherals in the JESD204B subsystem by clicking on the AddressMap tab in the Qsys window when the jesd204b_system.qsys project is open.

Table 7: JESD204B Subsystem Address Map

This table lists the memory allocation address map.

Avalon-MM Peripheral Address Map

JESD204B IP core base CSR – TX 0xC000 – 0xC3FF

JESD204B IP core base CSR – RX 0xD000 – 0xD3FF

Reset sequencer 0xE000 – 0xE0FF

Related Information

• Quartus Prime Handbook Volume 1: Design and SynthesisFor detailed description of the reset sequencer module.

• Altera Transceiver PHY User GuideFor detailed description of the transceiver PHY reset controller .

Core PLLThe core PLL generates clocks for the FPGA core fabric. The core PLL uses the device_clk external clocksignal as its reference clock to generate two derivative clocks from a single VCO:

• Link clock—from output C0• Frame clock—from output C1

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http://www.altera.com/literature/hb/qts/qts_qii5v1.pdf

https://documentation.altera.com/#/link/nik1398984401269/nik1398983846907/en-us


Table 8: Core PLL Clock Outputs

Clock Formula Description

Link Clock Serial data rate/40 Clocks the JESD204B IP core link layer and the linkinterface of the transport layer.

Frame Clock Serial data rate/(10 × F) Clocks the transport layer, test pattern generators andcheckers, and any downstream modules in the FPGAcore fabric.

For the frame clock, when F=1 and F=2, the resulting frame clock value can easily exceed the capability ofthe core PLL to generate and close timing. The top level HDL file (jesd204b_ed.sv) defines the frame clockdivision factor parameters, F1_FRAMECLK_DIV (for cases with F = 1) and F2_FRAMECLK_DIV (forcases with F = 2). This factor enables the transport layer and test pattern generator to operate at a dividedfactor of the required frame clock rate by widening the data width accordingly. For this reference design,the F1_FRAMECLK_DIV is set to 4 and F2_FRAMECLK_DIV is set to 2. Based on the default settings ofthe reference design, the frame clock for a serial data rate of 6.144 Gbps and F = 1 equals to:

(6144/(10 × 1)) / F1_FRAMECLK_DIV = 614.4 / 4 = 153.6 MHz

Transport LayerThe transport layer in the reference design consists of an assembler at the TX path and a deassembler atthe RX path. The transport layer for both the TX and RX path is implemented in the top level HDL file,not in the Qsys project.

The transport layer provides the following services to the application layer (AL) and the link layer:

• The assembler at the TX path:

• maps the conversion samples from the AL (through the Avalon-ST interface) to a specific format ofnon-scrambled octets, before streaming them to the DLL.

• reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interfaceduring TX data streaming.

• The deassembler at the RX path:

• maps the descrambled octets from the DLL to a specific conversion sample format before streamingthem to the AL (through the Avalon-ST interface).

• reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interfaceduring RX data streaming.

The transport layer has many customization options and you can modify the transport layer HDL code tocustomize it to your specifications. Furthermore, for certain parameters like L, F, and N, the transportlayer shares the CSR values with the JESD204B IP core. This means that any dynamic reconfigurationoperation that affects those values for the JESD204B IP core will affect the transport layer in the same way.

The software instructions to execute dynamic reconfiguration of the transport layer are described in theUser Commands section.

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Related Information

• User Commands on page 29For more details on the user commands that you can issue to the ARM HPS control unit.

• JESD204B IP Core User GuideFor more details on link clock and frame clock relationships and customizing the transport layer.

Test Pattern GeneratorThe test pattern generator generates one of three patterns—parallel PRBS, alternate checkerboard, orramp wave—and sends the pattern along to the transport layer during test mode. The test patterngenerator has many customization options and you can modify the test pattern generator HDL code tocustomize it to your specifications. Furthermore, for certain parameters like M, S, N, and test mode, thetest pattern generator shares the CSR values with the JESD204B IP core. This means that any dynamicreconfiguration operation that affects those values for the JESD204B IP core will affect the test patterngenerator in the same way. This includes the pattern type (PRBS, alternate checkerboard, ramp) which iscontrolled by the test mode CSR. The software instructions to execute dynamic reconfiguration of the testpattern generator are described in the User Commands section.

Note: The test pattern generator is implemented in the top level HDL file, not in the Qsys project.


Test Pattern CheckerThe test pattern checker checks one of three patterns—parallel PRBS, alternate checkerboard, or rampwave—from the transport layer during test mode. The test pattern checker has many customizationoptions and you can modify the test pattern checker HDL code to customize it to your specifications.Furthermore, for certain parameters like M, S, N, and test mode, the test pattern checker shares the CSRvalues with the JESD204B IP core. This means that any dynamic reconfiguration operation that affectsthose values for the JESD204B IP core will affect the test pattern checker in the same way. This includesthe pattern type (PRBS, alternate checkerboard, ramp) which is controlled by the test mode CSR. Thesoftware instructions to execute dynamic reconfiguration of the test pattern checker are described in theUser Commands section.

Note: The test pattern checker is implemented in the top level HDL file, not in the Qsys project.


Reference Design FilesThe reference design files are included in a ZIP file (jesd204b_av_soc_ref_design.zip). The ZIP file containstwo key components:

• Quartus project archive file (jesd204b_ed.qar)• Software project archive file (jesd204b_soc_baremetal_gnu.tar.gz)

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Table 9: Key Files and Folders in the Quartus Project Archive File

File Type File/Folder Description

Quartus projectfiles

jesd204b_ed.qpf Quartus project file.

jesd204b_ed.qsf Quartus settings file.

output_files Folder containing output files from Quartus compila‐tion (for example, reports or .sof).

Verilog HDLdesign files

jesd204b_ed.sv Top level HDL

jesd204b_ed.sdc Synopsys Design Constraints (SDC) file containingall timing or placement constraints.

ip Folder containing Verilog HDL and source files ofsub-modules instantiated in top level HDL file.

ip/altera_pll Folder containing Verilog HDL and source files ofcore PLL module.

ip/altiobuf Folder containing Verilog HDL and source files ofoutput buffer module.

ip/spi_mosi_oe Folder containing Verilog HDL and source files ofoutput buffer module.

ip/debounce Folder containing Verilog HDL and source files ofswitch debouncer module.

ip/issp Folder containing Verilog HDL and source files ofISSP module.

ip/edge_detect Folder containing Verilog HDL and source files ofedge detector module.

ip/transport_layer Folder containing assembler and deassembler HDL.

ip/pattern Folder containing the test pattern generator andchecker HDL.

Qsys Projectsjesd204b_ed_soc.qsys Top level Qsys system project.

jesd204b_system.qsys JESD204B subsystem

After you have imported the software project archive file (jesd204b_soc_baremetal_gnu.tar.gz) into the SoCEDS ARM DS-5 tool (refer to Setting up the Software Command Line Environment section), verify that thesoftware project contains the source and header files as shown in the table below.

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Table 10: Source and Header Files in Software Project

File Type File Description

Makefiles Makefile Software project compilation Makefile. The ARM DS-5 toolexecutes this Makefile during build project operation.Whenever you add or remove any *.c source files to or fromthe project, you must manually update the source file list inthis Makefile accordingly. See the Setting up the SoftwareCommand Line Environment section for more details.

Headerfiles

system.h Contains base address definitions of the following Avalon-MMperipherals implemented in the FPGA core fabric:

• Avalon-MM bridge• JESD204B IP core TX base layer• JESD204B IP core RX base layer• Reset sequencer• FPGA core control PIO• FPGA core status PIO• SPI master module

The base addresses correspond to the address maps of thejesd204b_ed_soc.qsys and jesd204b_system.qsys projects inQsys. Whenever you make any changes to the address maps inQsys, you must manually update the base addresses in this fileaccordingly.

altera_jesd204_regs.h Contains offsets, masks, and bit position definitions forperipherals in the QSYS system that do not have standardaccess libraries. This includes the following peripherals:

• JESD204B IP core TX base layer• JESD204B IP core RX base layer• Reset sequencer• FPGA core control PIO• FPGA core status PIO

main.h General user parameter definitions. See Software Parameterssection for detailed description of the user parameters.

functions.h Contains function prototype definitions of sub-functions inmain.c.

rules.h Contains function prototype definitions of rule functions inrules.c.

macros.h Contains function prototype definitions of macro functions inmacros.c.

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File Type File Description

Sourcefiles

main.c Main C program. Also contain sub functions.

rules.c Rule checking functions used by the dynamic reconfigurationfunctions.

macros.c JESD204B Qsys system device access macros.

Related Information

• Setting up the Software Command Line Environment on page 5• Software Parameters on page 39

For more details on the software user parameters.• Software Functions Description on page 41

For more details on the functions in main.c, rules.c and macros.c.

FPGA Pin AssignmentsThe interface ports of the top level HDL file (jesd204b_ed.sv) with their corresponding FPGA pinassignments on the Arria V SoC development board are listed in the table below. The table only lists theJESD204B-related pin assignments. For all other board-related and ARM HPS-related pin assignments,refer to the Quartus settings file (jesd204b_ed.qsf).

Table 11: FPGA Pin Assignments on Arria V SoC Development Board

Interface PortName

FPGA PinNumber

I/OStandard

Direction Board Source/Destina‐tion

Description

General Clocksfpga_clk_50 AU32 1.5 V Input 50 MHz on-board

oscillator (X4) viaSL18860DC clockdistribution buffer(U30)

Reference clock for ARMHPS control unit and allperipherals connected viaAXI/Avalon-MM intercon‐nect. The clock frequency is50 MHz.

device_clk AC31 (1)

U31 (2)

LVDS Input FMC Port Aconnector (1)

Si571 ProgrammableOscillator (2) Reference clock for

JESD204B data path. Theclock frequency is 153.6 MHzdevice_clk (n) AC32 (1)

U32 (2)

LVDS Input FMC Port Aconnector (1)

Si571 ProgrammableOscillator (2)

(1) For external converter interoperation.(2) For internal serial loopback only.

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Interface PortName

FPGA PinNumber

I/OStandard


Description

Serial Datajesd204_rx_serial_data[3]

AB39

1.5 VPCML

Input FMC Port A connector

Differential high speed serialinput data.

jesd204_rx_serial_data[3](n)

AB38 Input FMC Port Aconnector

jesd204_rx_serial_data[2]

AF39 Input FMC Port Aconnector


AF38 Input FMC Port Aconnector


Y39 Input FMC Port Aconnector


Y38 Input FMC Port Aconnector


T39 Input FMC Port Aconnector


T38 Input FMC Port Aconnector

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Interface PortName

FPGA PinNumber

I/OStandard


Description

jesd204_tx_serial_data[3]

AA37

1.5 VPCML

Output FMC Port A connector

Differential high speed serialoutput data.

jesd204_tx_serial_data[3](n)

AA36 Output FMC Port Aconnector


AE37 Output FMC Port Aconnector


AE36 Output FMC Port Aconnector


W37 Output FMC Port Aconnector


W36 Output FMC Port Aconnector


R37 Output FMC Port Aconnector


R36 Output FMC Port Aconnector

JESD204B Control Signalsjesd204_sysref_out

E27 LVDS Output FMC Port A connectorSYSREF signal for JESD204BSubclass 1 implementation.jesd204_

sysref_out (n)F27 LVDS Output FMC Port A

connector

jesd204_sync_n_out

J26 LVDS Output FMC Port A connector Indicates a SYNC_N from thereceiver. This is an active lowsignal and is asserted 0 toindicate a synchronizationrequest or error reporting.

jesd204_sync_n_out (n)

K26 LVDS Output FMC Port Aconnector

SPIspi_MISO H27 2.5 V Input FMC Port A connector Output data from a slave to

the input of the masterspi_MOSI N23 2.5 V Output FMC Port A connector Output data from the master

to the inputs of the slaves.spi_SCLK M23 2.5 V Output FMC Port A connector Clock driven by the master to

slaves, to synchronize thedata bits.

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Interface PortName

FPGA PinNumber

I/OStandard


Description

spi_SS_n[0] P27 2.5 V Output FMC Port A connector Active low select signaldriven by the master toindividual slaves, to select thetarget slave.

Interface Port Name FPGAPin

Number

I/OStandard

Direction Description

Avalon-ST User Data (3)

jesd204_avst_usr_din[LINK* TL_DATA_BUS_WIDTH-1:0]

— — Input TX data from the Avalon-ST sourceinterface. The TL_DATA_BUS_WIDTHis determined by the following formulas:

• If F = 1, TL_DATA_BUS_WIDTH =F1_FRAMECLK_DIV*8*1*L*N/N_PRIME


• If F = 4, TL_DATA_BUS_WIDTH =8*4*L*N/N_PRIME


jesd204_avst_usr_din_valid[LINK-1:0]

— — Input Indicates whether data from the Avalon-ST source interface to the transport layeris valid or invalid.

• 0: data is invalid• 1: data is valid

jesd204_avst_usr_din_ready [LINK-1:0]

— — Output Indicates that the transport layer is readyto accept data from the Avalon-STsource interface.

• 0: transport layer is not ready toreceive data

• 1: transport layer is ready to receivedata

(3) The Avalon-ST user data signals are classified as virtual pins and are not explicitly assigned to actualpins. You are expected to connect the signals to the rest of your design.

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Interface Port Name FPGAPin

Number

I/OStandard

Direction Description

jesd204_avst_usr_dout[LINK*TL_DATA_BUS_WIDTH-1:0]

— — Output RX data to the Avalon-ST sink interface.The TL_DATA_BUS_WIDTH isdetermined by the following formulas:





jesd204_avst_usr_dout_valid [LINK-1:0]

— — Output Indicates whether the data from thetransport layer to the Avalon-ST sinkinterface is valid or invalid.

• 0: data is invalid• 1: data is valid

jesd204_avst_usr_dout_ready [LINK-1:0]

— — Input Indicates that the Avalon-ST sinkinterface is ready to accept data from thetransport layer.

• 0: Avalon-ST sink interface is notready to receive data

• 1: Avalon-ST sink interface is readyto receive data

jesd204_avst_patchk_data_error [LINK-1:0]

— — Output Output signal from pattern checkerindicating a pattern check error.

System ParametersThe top level HDL file (jesd204b_ed.sv) includes system parameters that define the configuration of thereference design as a whole. The default values of the parameters are listed in the table below. You canchange the values in the HDL file in order to customize the parameters to your system configuration buteach parameter value must fall within the specified range as indicated in the table. When modifying theJESD204B IP core-related parameters (L, M, F, N, N_PRIME, S, CS), ensure that the correspondingparameter values in the JESD204B IP core located in the jesd204b_system.qsys Qsys project are set tomatch the values that you specified in the HDL file. See Modifying JESD204B IP Core Parameters sectionfor more details.

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Table 12: System Parameters

Parameter DefaultValue

SupportedValues

Description

LINK 1 1, 2, …, n wheren is any positiveinteger

Number of JESD204B links. One linkrepresents one JESD204B instance.

L 4 1, 2, 4, 8 Number of JESD204B lanes per converterdevice.

M 2 1, 2, 4, 8 Number of JESD204B converters perdevice.

F 1 1, 2, 4, 8 Number of JESD204B octets per frame.

N 14 12 – 16 Number of JESD204B conversion bits perconverter device.

N_PRIME 16 16 Number of JESD204B transmitted bits persample.

S 1 1, 2 Number of JESD204B transmitted samplesper converter device per frame.

CS 0 0 - 3 Number of JESD204B control bits perconversion sample.

F1_FRAMECLK_DIV 4 1, 4 Divider ratio for frame_clk when F=1.Refer to Core PLL section for more details.

F2_FRAMECLK_DIV 2 1, 2 Divider ratio for frame_clk when F=2.Refer to Core PLL section for more details.

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Parameter DefaultValue

SupportedValues

Description

POLYNOMIAL_LENGTH 9 7, 9, 15, 23, 31 Defines the polynomial length for the PRBSpattern generator and checker, which isalso the equivalent number of stages for theshift register.

• If PRBS-7 is required, set this parameterto 7.


• If PRBS-15 is required, set thisparameter to 15.



This parameter value must not be largerthan N, which is the output data width ofthe PRBS pattern generator or converterresolution. If an N value of 12-14 isrequired, PRBS-7 and PRBS-9 are the onlyfeasible options. If an N value of 15-16 isrequired, PRBS-7, PRBS-9, and PRBS-15are the only feasible options.

FEEDBACK_TAP 5 6, 5, 14, 18, 28 Defines the feedback tap for the PRBSpattern generator and checker. This is anintermediate stage that is XOR-ed with thelast stage to generate to next PRBS bit.






Related Information

• Modifying JESD204B IP Core Parameters on page 52• Core PLL on page 16

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Reference Design SoftwareThe key feature of the reference design with ARM HPS control unit is the ability to control certain aspectsof the JESD204B system using a C-based, software control flow. Some of the capabilities enabled by thesoftware control flow are:

• System reset—ability to reset individual modules (for example, core PLL, transceiver PHY, JESD204Bbase Avalon-MM interface, link clock domain, and frame clock domain) independently or in sequence.

• Initial and dynamic, real-time configuration of external converter devices via SPI interface.• Dynamic reconfiguration of key modules in the reference design subsystem (for example, JESD204B IP

core base layer, transceiver PHY, core PLL, and so forth).• Error handling via interrupt service routines (ISR).• Status register read back.• Dynamic switching between real-time operation and test mode.

The software C code included as part of the reference design performs basic JESD204B link initializationand brings up the user command prompt, where you can enter commands to perform a wide variety oftasks. Modify the code as necessary to meet your system specifications.

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Figure 6: Main C Code Execution Flow

Complete reset sequence

Set loopback mode (3)

Pulse SYSREF

Wait 10 seconds

Report link status

Reset link

Initialize ISR (4)

START

ERROR

Execute commandEXIT command?

END

Print status

No

Yes

Enter user command

No

Yes

Notes:(1) Disable RX locked to data error enable, phase compensation FIFO full error enable, and phase compensation FIFO empty error enable registers from rx_err_enable CSR register of the JESD204B IP core. Disable transceiver PLL locked error enable, phase compensation FIFO full error enable, and phase compensation FIFO full empty enable registers from tx_err_enable CSR register of the JESD204B IP core.(2) Default setting: Test pattern generator/checker with pattern type set to PRBS.(3) Default setting: Internal serial loopback mode.(4) Interrupt service routine.(5) Read the JESD204B IP core CSR registers for initially configured L and F parameters and store the values into variables to be used by the dynamic reconfiguration function. For the initial value of the frame clock (FC), read the JESD204B IP core CSR registers for initially configured L, M, S, N’ parameters and derive the FC value using the parameters. The FC values are stored into variables to be used by the dynamic reconfiguration function during data rate reconfiguration operation.

HPS Detect is Arria V?

Setup HPS-FPGA bridge

Clean up HPS-FPGA bridge

Disable certain TX/RX error interrupt enable

CSR registers in JESD204B IP core (1)

Clear JESD204B error status register

Clear JESD204B error status register

Initialize JESD204B link

Set test pattern generator/checker

pattern type or user mode (2)

Get initial values for L, F, FC (5)

Print user command prompt

Related InformationSetting up the Software Command Line Environment on page 5For instructions on setting up the software command line in the SoC EDS tool.

User CommandsThe steps in Setting up the Software Command Line Environment section show how you can compile andexecute the software to bring up the App Console window in the SoC EDS tool. After executing thesoftware, the App Console window displays a command prompt where you can enter commands to theARM HPS control unit to perform various tasks. The table below describes the commands that you canissue at the command prompt.

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Table 13: User Commands

Type Command Description

Help h Display menu of available commands.

Reset r [link select #] [p | x |c | l | f | h | r]

Selective/global soft system reset. The [link select #] option selectsthe link that the command will take effect on. If no [link select #]option is indicated, the command will take effect on all linksidentically. The [p | x | c | l | f ] options indicate the specificsubmodule that the reset command will take effect on:

[p] – Core PLL

[x] – TX/RX Transceivers (JESD204B IP core PHY)

[c] – TX/RX JESD204B IP core CSR

[l] – TX/RX link reset

[f] – TX/RX frame reset

If none of the options above are indicated, all submodules are reset.You can indicate multiple options simultaneously to performsimultaneous submodule resets.

The [h | r] options indicate if the reset is asserted and held orreleased from a hold:

[h] – Assert and hold reset

[r] – Release reset

If none of the options above are indicated, the resets are pulsed(asserted and released automatically).

When the [r] option is indicated, the reset is released immediatelywithout checking for any qualifying conditions (for example, thePLL locked or transceiver ready signals). You are responsible toqualify the signals before holding or releasing the resets.

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Reset r [link select #] [p | x |c | l | f | h | r]

(continued)

Depending on the DATAPATH setting in the main.h file, the commandtakes effect on either the TX only datapath (if DATAPATH is set to TXonly), the RX only datapath (if DATAPATH is set to RX only) or bothTX and RX datapaths (if DATAPATH is set to duplex).

Command examples:

• > r : This is a full auto-mode global reset that performs a seriesof initialization steps after global reset. The sequence of stepsare:

1. Global system reset on all links according to the hardwarereset sequence (refer to Figure 1 for timing diagram ofhardware reset sequence).

2. Initialize link (set loopback and source/destination mode todefault mode).

3. Trigger SYSREF pulse (for Subclass 1 configuration).4. Wait 10 seconds.5. Report link status.

• > r 2 h : Assert all submodule resets for link 2 and hold resetsindefinitely.

• > r r : Release all submodules resets for all links immediatelyand concurrently (no pre-set hardware sequence)

Attention: Not recommended as no checking process forqualifying signals.

• > r x l f h : Assert and hold transceiver, link, and frameresets for all links.

• > r x r : Release (deassert) transceiver resets for all links (butkeep other submodule resets on hold if previously held)

• > r 2 l f : Pulse (assert and release) link and frame resets forlink 2 (but keep other submodule resets on hold if previouslyheld)

Load SPI ls [slave select #]<offset> <value>

Loads 8-bit value <value> (in C-style “0x” hexadecimal notation)into the register of external converter module connected to the SPIinterface at offset <offset> (in C-style “0x” hexadecimal notation)indicated by [slave select #]. The maximum bit width of <offset> is16 bits.

Get SPI gs [slave select #]<offset>

Gets the 8-bit value (in C-style “0x” hexadecimal notation) at theregister of external converter module connected to SPI interface atoffset <offset> (in C-style “0x” hexadecimal notation) indicated by[slave select #]. The maximum bit width of <offset> is 16 bits.

Config SPI cs Configure external converter modules via SPI interface.



Send Feedback



Initialize i [link select #] [n] Initialize link indicated by [link select #]. The [link select #] optionselects the link that the command will take effect on. If no [linkselect #] option is indicated, the command takes effect on all linksidentically. By default, the link is initialized to test mode (see ‘Test’command). The optional [n] option initializes the link to user mode(see ‘Test’ command).

Note: When setting to user mode, ensure that the user inputdata valid signal (avst_usr_din_valid) is properlyconnected in the top level HDL file (jesd204b_ed.sv).Failing to do so will result in continuous error interruptsand may cause the system to hang.

The full sequence of steps executed by this command:

1. Set test or user mode (set loopback and source/destinationmode) as per options indicated.

2. Trigger SYSREF pulse (for Subclass 1 configuration).3. Wait 10 seconds.4. Report link status.

Status s [link select #] [t | r] Reports TX and/or RX link status of link indicated by [link select #].Reads back tx_status0 and/or rx_status0 status registers fromthe JESD204B CSR identified by [link select #] and reports linkstatus based on the values in those registers. For example, thecommand can report that the indicated link is not in sync or not inUser Data Mode. In addition, the command reports the status of thepattern checker error signal. The [link select #] option selects thelink that the command will take effect on. If no [link select #]option is indicated, the command takes effect on all linksidentically. The optional [t | r] options indicates the datapath to bereported:

[t] – Report TX path status only

[r] – Report RX path status only

[no option] – Report default path status according to DATAPATHsetting

Depending on the DATAPATH setting in the main.h file, the commandwill take effect on either the TX only datapath (if DATAPATH is set toTX only), the RX only datapath (if DATAPATH is set to RX only) orboth TX and RX datapaths (if DATAPATH is set to duplex).

Loopback lb [link select #] [n] Puts the JESD204B IP core PHY indicated by [link select #] intotransceiver serial loopback mode. This command is only applicablefor links where the JESD204B IP core is configured in duplex mode(TX and RX datapaths present). The [link select #] option selectsthe link that the command will take effect on. If no [link select #]option is indicated, the command takes effect on all linksidentically. The optional [n] option sets the JESD204B IP core PHYindicated by [link select #] into non-serial loopback mode.


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Source/Destination

sd [link select #] [s | d][u | a | r | p]

Selects the source and destination datapath for the Avalon-STinterface of the link indicated by [link select #]. The [link select #]option selects the link that the command will take effect on. If no[link select #] option is indicated, the command takes effect on alllinks identically. The optional [s | d] option indicates whether thesource (TX) or destination (RX) datapath is being selected:

[s] – Source datapath (TX)

[d] – Destination datapath (RX)

[no option] – Default datapath according to DATAPATH setting

Depending on the DATAPATH setting in the main.h file, the commandwill take effect on either the TX only datapath (if DATAPATH is set toTX only), the RX only datapath (if DATAPATH is set to RX only) orboth TX and RX datapaths (if DATAPATH is set to duplex).

The optional [u | a | r | p] option indicates the type of datapath toset to:


[u] – User datapath (no test pattern generator and checker)

[a] – Test pattern generator and checker set to alternate pattern

[r] – Test pattern generator and checker set to ramp pattern

[p] – Test pattern generator and checker set to PRBS pattern

[no option] – Default to test pattern generator and checker set toPRBS pattern

The test pattern generator and checker module has other configu‐rable parameters that you can set. In particular, the patterngenerator and checker derives its M and S values from theJESD204B IP core CSR. Also, there are other parameters such asPOLYNOMIAL_LENGTH and FEEDBACK_TAP that are set during compiletime. Refer to Chapter 5 of the JESD204B IP Core User Guide formore details.



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Test t [link select #] [n] Sets the link indicated by [link select #] to test mode. The [linkselect #] option selects the link that the command will take effecton. If no [link select #] option is indicated, the command takeseffect on all links identically. The test mode is defined by:

• Source and destination datapath set to default (test patterngenerator and checker set to PRBS pattern)

• Transceiver set to serial loopback mode

The optional [n] option negates the test mode (set to user mode).User mode is defined as:

• Source and destination datapath set to user datapath• Transceiver set to non-serial loopback mode


Reinitializa‐tion

ri [link select #] [t | r] Trigger a link reinitialization on links indicated by [link select #].The optional [link select #] option selects the link that thecommand will take effect on. If no [link select #] option is indicated,the command takes effect on all links identically. The optional [t | r]option indicates the type of reinitialization operation:

[t] – TX link reinitialization; TX link transmits K28.5 packetscontinuously until link is out of CGS (Code Group Synchroniza‐tion) phase

[r] – RX link reinitialization; SYNC_N signal is driven low until linkis out of CGS (Code Group Synchronization)

Note: Forcing RX link reinitialization will trigger a TX SYNCNerror interrupt to the processor. The interrupt isautomatically cleared by the software.

[no option] – For DATAPATH setting set to TX only or duplex, defaultto TX link reinitialization. For DATAPATH setting set to RX only,default to RX link reinitialization

For more details on the reinitialization operation, refer to theJESD204B IP Core User Guide.

Sysref sy Pulse SYSREF signal one time (“one-shot”)


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Reconfigu‐ration

rc [link select #]

[l <value>]

[m <value>]

[f <value>]

[s <value>]

[n <value>]

[np <value>]

[cs <value>]

[k <value>]

[hd <value>]

[scr <value>]

[sub <value>]

Dynamically reconfigure link indicated by [link select #] accordingto parameter-value pair option indicated. The optional [link select#] option selects the link that the command will take effect on. If no[link select #] option is indicated, the command takes effect on alllinks identically. The parameters that are dynamically configurableare as follows:

[l] – Lanes per converter device

[m] – Converters per device

[f] – Octets per frame

Note: The Altera test pattern generator and checker do notsupport dynamic reconfiguration of F.

[s] – Samples per converter per frame

[n] – Converter resolution

[np] – Transmitted bits per sample

[cs] – Control bits

[k] – Frames per multi-frame

[hd] – High density user data format

[scr] – Enable scrambler

[sub] – Subclass select

The valid value ranges that can be entered for each parameter aregoverned by rules enforced by software. Refer to the DynamicReconfiguration section for more details.

Command examples:

• > rc l 2 m 2 f 2 : Reconfigure the JESD204B IP core to L=2,M=2, F=2.

• > rc np 16 hd 1 : Reconfigure the JESD204B IP core to N’=16,HD=1.

Dynamic ReconfigurationOne of the key features that the ARM HPS enables is software-controlled dynamic reconfiguration of theJESD204B parameters. You can issue the reconfiguration command (rc) along with the parameters andvalues that you desire at the command prompt. The valid ranges for the values entered for each parameterare governed by certain rules. These rules are a function of:

• JESD204B IP core valid parameter ranges.• JESD204B transport layer valid parameter ranges.• Initially configured values for the JESD204B IP core.

The rule enforcement for valid ranges are implemented as discrete functions in the rules.c file (seeFunctions in rules.c Source File section) and are described in the table below. If you enter an invalid value,the software flags the error to the screen and disallows the change.

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The Altera JESD204B transport layer in the reference design has a more restricted value range for certainparameters compared to the JESD204B IP core. In cases where the parameter value ranges are governedby both the JESD204B IP core and the transport layer, the more restrictive value range will takeprecedence. In the table below, the transport layer rules are indicated by “TL:”.

Note: If you are not using the Altera transport layer, turn off the transport layer rule checking by settingthe ALTERA_TRANSPORT_LAYER parameter in the main.h header file to ‘0‘ (see the SoftwareParameters section).

Table 14: Dynamic Reconfiguration Command Options and Rules

CommandOptions

Parameters Rule

l L The value for L must be an integer within the range of 1-8.

Returns 0 if valid, 1 if invalid.

l L The value for L must not exceed the initially configured value.


l L, F TL: The value for L must be an even number if F = 1.


m M The value for M must be an integer within the range of 1-32.


f F The value for F must be an integer within the range of 1,2, 4-256 (anyinteger value between 1-256 except 3)

TL: The value for F must be an integer of the values 1, 2, 4, 8



f, m, s, np, l F, M, S, N’, L The values for M, S, N' and L must be such that the current value of Fconforms to the formula F(current) = (M * S * N')/(8*L). If a new valueof F is indicated, then F(current) = F(new). If not, then F(current) =F(initially configured).



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CommandOptions

Parameters Rule

f, m, s, np, l F, M ,S, N’, L The value for F must not exceed the initially configured value. Byextension, since F is defined by the formula F = (M * S * N')/(8*L), thevalues for M, S, N' and L must be such that the new value for F notexceed the initial configured value.



s S The value for S must be an integer within the range of 1-32.


n N The value for N must be an integer within the range of 1-32

TL: The value for N must be an integer within the range of 12-16.


n, np N The value for N must adhere to the following range: N ≤ N'.


np N’ The value for N' must be an integer within the range of 4-32.

TL: Only N'=16 configuration is supported. Dynamic reconfigurationof N' parameter is not supported.


cs CS The value for CS must be an integer within the range of 0-3.


k K The value for K must be an integer within the range 17/F ≤ K ≤min(32, floor(1024/F)).


f, k F, K The value of F * K must be divisible by 4.


hd High Density(HD)

The value for HD must be either 0 or 1.


hd, n HD, N TL: The value for HD can be 1 if and only if N=16.


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CommandOptions

Parameters Rule

scr ScramblerEnable

The value for SCR must be either 0 or 1.


sub Subclass The value for subclass must be 0, 1 or 2.


Related Information

• Software Parameters on page 39• Functions in rules.c Source File on page 45• JESD204B IP Core User Guide

For more details on valid parameter ranges for JESD204B IP core and transport layer.

Software Interrupt Service Routines (ISR)One key feature of the ARM HPS control unit is the ability to handle interrupt requests (IRQ) fromperipherals via ISR. The reference design main.c source code defines ISRs for the following peripherals:

• JESD204B IP core TX base layer• JESD204B IP core RX base layer• SPI master module

The ISRs in the reference design main.c source code is a very basic routine that performs these two tasks:

• Clear interrupt request (IRQ) error flag.• Print error type and message (for JESD204B IP core TX and RX base layer ISR only).

The error types and messages printed by the JESD204B IP core TX and RX base layer ISRs respectively arelisted below.

Error types printed by the JESD204B IP core TX base layer ISR:

• SYNC_N error• SYSREF LMFC error• DLL data invalid error• Transport layer data invalid error• SYNC_N link reinitialization request• Transceiver PLL locked error• Phase compensation FIFO full error• Phase compensation FIFO empty error

Error types printed by the JESD204B IP core RX base layer ISR:

• SYSREF LMFC error• DLL data ready error• Transport layer data ready error• Lane deskew error• RX locked to data error• Phase compensation FIFO full error• Phase compensation FIFO empty error

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• Code group synchronization error• Frame alignment error• Lane alignment error• Unexpected K character• Not in table error• Running disparity error• Initial Lane Alignment Sequence (ILAS) error• DLL error reserve status• ECC error corrected• ECC error fatal

The error types correspond to the tx_err, rx_err0, and rx_err1 status registers in the JESD204B IP coreTX and RX register maps respectively. The printing of interrupt error messages to the App Consolewindow is controlled by the PRINT_INTERRUPT_MESSAGES parameter in the main.h header file. Set to‘1’ (default) to print error messages, else set to ‘0’. Refer to the Software Parameters section for moredetails. Modify the ISRs in the source code to customize the interrupt handling response to your systemspecifications.

Related Information

• Software Parameters on page 39• JESD204B IP Core User Guide

For more details on error status registers in the TX and RX register maps .

Software ParametersVarious behaviors of the main.c source code are controlled by software parameters defined in the mainheader file, main.h.

Table 15: Software Parameters

This table lists the software parameters and description.Parameter Description Default Value

DEBUG_MODE Set to 1 to print debug messages, else set to 0. 0

PRINT_INTERRUPT_MESSAGES

Set to 1 to print JESD204B error interrupt messages, elseset to 0.

1

CONFIG_SPI Set to 1 to configure external converters via SPI interfaceat start of main.c execution, else set to 0.

1

PATCHK_EN Set to 1 when test pattern checker is included in theinitial design configuration, else set to 0.

1

ALTERA_TRANSPORT_LAYER

Set to 1 when using Altera transport layer, else set to 0. 1

BONDED Set to 1 when transceivers configured in bonded mode,set to 0 when transceivers configured in unbonded mode.

0

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Parameter Description Default Value

DATAPATH Set to indicate JESD204B IP configuration:

• 1: TX data path only• 2: RX data path only• 3: Duplex data path (TX and RX data path)

3

DATA_RATE_LINK_n Set to indicate the initially configured serial data rate oflink n in Mbps (for example, to set link 0 to 6144 Mbps,DATA_RATE_LINK_ 0=6144). For multi-link scenarios,add additional DATA_RATE_ LINK_n parameters tothe DR_init[] array in main.c.

Note: Data rate reconfiguration is not supported in thisreference design.

6144

DATA_RATE_MIN Set to indicate the minimum serial data rate (in Mbps)supported by the JESD204B IP core for the followingdevice families:

• Arria V GZ, Arria 10, Stratix V: 2000• Arria V: 1000

Note: Data rate reconfiguration is not supported in thisreference design.

2000

MAX_LINKS Set to indicate the number of links in the design (forexample, for dual link, set MAX_LINKS=2)

Note: When using the design as-is, the maximum valueof MAX_ LINKS is 4. To increase the limit,redesign the address map in QSYS.

1

LINE_BUFFER Sets the maximum number of characters that user canenter on command line.

100

MAX_NUM_OPTIONS Sets the maximum number of options per command. 20

MAX_OPTIONS_CHAR Sets the maximum number of characters per commandoption

10

LOOPBACK_INIT Initial value of loopback. Set to 1 for internal serialloopback mode, else set to 0.

1

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Parameter Description Default Value

SOURCEDEST_INIT Initial value of source/destination. Set to indicate testpattern generator/checker type or user mode:

• USER: User mode (no test pattern generator/checkerin data path).

• ALT: Test pattern generator/checker set in alternatecheckerboard mode.

• RAMP: Test pattern generator/checker set in rampwave mode.

• PRBS: Test pattern generator/checker set in parallelPRBS mode.

PRBS

F1_FRAMECLK_DIV Set to the F1_FRAMECLK_DIV parameter as defined inthe top level HDL file (jesd204b_ed.sv).

4

F2_FRAMECLK_DIV Set to the F2_FRAMECLK_DIV parameter as defined inthe top level HDL file (jesd204b_ed.sv).

2

SOC Set to 1 if source code is targeting ARM HPS. Set to 0 ifsource code is targeting soft Nios II processor.

1

Software Functions DescriptionThis section describes the functions used in the main.c and rules.c source code and also the macros libraryin macros.c that facilitates access to the configuration and status registers (CSR) of the JESD204B systemdesign. These functions and macros provide the building blocks for you to customize the software code toyour system specifications.

Functions in main.c Source File

The function prototypes of the functions listed in the table below can be found in the functions.h headerfile.

Table 16: Functions in main.c

Function Prototype Description

void chomp (char * string) Chomps trailing '\n' character from string.int StringIsNumeric (char * string) Tests whether string is numeric.

Returns 1 if true, 0 if false.

int StringIsHex (char * string) Tests whether string is a hexadecimal number.

Returns 1 if true, 0 if false.

void DelayCounter (alt_u32 count) Delay counter. Counts up to count ticks, each tick is roughly 1second (not accurate).

void Get_L_Init (int * L_init) Read initially configured value of L from each JESD204B IP coreCSR in the design and store the value in L_init array.

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void Get_F_Init (int * F_init) Read initially configured value of F from each JESD204B IP coreCSR in the design and store the value in F_init array.

void Get_FC_Init (int * FC_init , int *DR_init)

Calculate initially configured value of the frame rate by readingthe relevant parameters from each JESD204B IP core CSR in thedesign and the serial data rate values stored in DR_init. Storescalculated value in FC_init array.

int Initialize (char * options [][], int *held_resets)

Executes initialize command according to options. This functionperforms the following actions:

• Set link to test mode (source or destination set to PRBS testpattern generator or checker, transceiver set to serialloopback mode) or negate

• Pulse sysref• Wait 10 seconds• Report link status

Returns 0 if success, 1 if fail, 2 if sync errors found, 4 if patternchecker errors found, 6 if both sync errors and pattern checkererrors found.

void Help (void) Prints menu of available commands.int Reset (char * options [][], int * held_resets)

Executes reset command according to options. This functioncalls two other subfunctions depending on options:• Reset sequence (initiate full hardware reset sequence)• Reset force (force individual resets high, low, or pulse

depending on options)Returns 0 if success, 1 if fail.

int LoadSPI (char * options [][]) Executes the load SPI command according to options.Returns 0 if success, 1 if fail.

int GetSPI (char * options [][]) Executes get SPI command according to options.Returns 0 if success, 1 if fail.

int ConfigSPI (int * held_resets , intdnr)

Executes the configure SPI command according to options.Returns 0 if success, 1 if fail.

int Status (char * options [][]) Executes the report link status command according to options.Returns 0 if success, 1 if fail, 2 if sync errors found, 4 if patternchecker errors found, 6 if both sync errors and pattern checkererrors found.

int Loopback (char * options [][], int *held_resets , int dnr)

Executes the loopback command according to options.Returns 0 if success, 1 if fail.

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int SourceDest (char * options [][], int *held_resets , int dnr)

Executes the source or destination datapath selection commandaccording to options.Returns 0 if success, 1 if fail.

int Test (char * options [][], int * held_resets)

Executes the test mode command according to options. Testmode:

• Set source or destination datapath selection to PRBS testpattern generator or checker.

• Set transceiver to serial loopback mode.

Returns 0 if success, 1 if fail.int Reinit (char * options [][], int * held_resets)

Executes the reinit command according to options. Thisfunction performs the following actions:

• Write reinit values to the appropriate registers in theJESD204B IP core CSR to trigger reinit operation

• Pulse sysref• Wait 10 seconds• Report link status

Returns 0 if success, 1 if fail, 2 if sync errors found, 4 if patternchecker errors found, 6 if both sync errors and pattern checkererrors found.

void Sysref (void) Pulse SYSREF signal one time (that is in "one-shot").

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int Reconfig (char * options [][], int * L_init , int * F_init , int * DR_init , int *FC_init , int * current_dr_div , unsignedint link_clk_pll_ counter_val_init ,unsigned int frame_clk_pll_ counter_val_init , unsigned int * xcvr_native_array_ptr [][], unsigned int * xcvr_pll_array_ptr [][], int * held_resets)

Executes dynamic reconfiguration command. This functionperforms three major tasks:

• Parses user options to identify the parameters and values tobe dynamically reconfigured by user

• Performs rule-checking to ensure all values entered conformto valid ranges

• Performs read-modify-writes (RMW) to relevant CSRregisters based on valid options entered by user

There are four categories of the CSR register RMWs performedby the software:

• Write new parameter values to the TX/RX JESD204B CSRilas_data1 and ilas_data2 registers.

• Write to TX/RX JESD204B CSR lane_control_n registersto power-down or power-up lanes in response to changes inL parameter.

Note: This feature is not fully implemented in thehardware.

• Write to the core PLL reconfiguration module in response tochanges in link or frame clock data rate.

• Write to the transceiver reconfiguration interface and/orATX PLL reconfiguration interface in response to changes intransceiver serial data rate.

For more details on dynamic reconfiguration features, refer tothe Dynamic Reconfiguration section.

Returns 0 if success, 1 if fail.

void ResetHard (void) Triggers full hardware reset sequence via PIO control registers.int ResetSeq (int link , int * held) Performs full hardware reset sequence on the indicated link via

software interface .


int ResetForce (int link , int reset_val ,int hold_release , int * held_resets)

Forces reset assertion or deassertion on submodule resets for thelink indicated by reset_val. The function also decides whether toassert and hold (hold_release =2), deassert ( hold_release =1) orpulse ( hold_release =0) indicated resets. The function hasmechanisms (using the global held_resets flag) to ensure thatheld resets that are not the target of the reset force function arenot affected by it.


int Reset_PLL_Release (int link, int *held_resets)

Deassert the core PLL reset signal. Wait until the core PLLlocked signal assert before returning.


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int Reset_X_L_F_Release (int link, int *held_resets)

Deassert the transceiver, link, and frame resets. This functiondeasserts the TX transceiver reset first, waits until the TXtransceiver ready signal asserts, then deasserts the TX link andTX frame resets. The function then repeats the above actionswith the RX data path.


void spiWrite (alt_u16 offset, alt_u8 m_data, alt_u8 slave)

Performs SPI write operation of m_data to SPI slave indicatedby slave number at address offset offset. The maximum bit widthof m_data is 8 bits while the maximum bit width of offset is 16bits.

alt_u8 spiRead (alt_u16 offset, alt_u8slave)

Performs SPI read operation of SPI slave indicated by slavenumber at address offset offset. Returns 8-bit read value. Themaximum bit width of offset is 16 bits.

void spiVerify (alt_u16 offset , alt_u8slave, alt_u8 data)

Performs SPI read operation of SPI slave indicated by slavenumber at address offset offset, compares the read data to data,then reports whether the read data matches the user-given data.The maximum bit width of data is 8 bits while the maximum bitwidth of offset is 16 bits.

void Config_AD9680 (alt_u8 slave) Executes a series of spiWrites to the AD9680 slave to configureit.

void InitISR (void) Initialize the interrupt controllers for the following peripherals:

• JESD204B IP core TX CSR• JESD204B IP core RX CSR• SPI master

The timer and JTAG UART interrupt controllers are disabled.Modify the function to enable it.

Functions in rules.c Source File

The rules enforced by the dynamic reconfiguration function to check validity of the reconfigurationvalues for each JESD204B parameter are coded as discrete functions in rules.c. In the table below, thetransport layer rules are indicated by “TL:”. The function prototypes of the functions listed in the tablebelow can be found in the rules.h header file.

Table 17: Functions in rules.c

Function Prototype Parameters Rule/Function Description

int Min (int val1 , int val2) — Returns the minimum of val1 and val2.int L_Range (int val) L The value for L must be an integer within the range of 1-8.


int L_Max (int val, intinit)

L The value for L must not exceed the initially configuredvalue.


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int L_Even (int L_val, intF_val)

L, F The value for L must be an even number if F = 1.


int M_Range (int val) M The value for M must be an integer within the range of 1-32.


int F_Range (int val) F The value for F must be an integer within the range of 1,2,4-256 (any integer value between 1-256 except 3)

TL: The value for F must be an integer of the values 1, 2, 4,8.


int F_Max (int val, intinit)

F, M ,S, N', L The value for F must not exceed the initially configuredvalue. By extension, since F is defined by the formula F =(M * S * N')/(8*L), the values for M, S, N' and L must besuch that the new value for F not exceed the initialconfigured value.


int F_Equal (int M_val, intS_val, int NP_val, int L_val, int F_val)

F, M, S, N', L The values for M, S, N' and L must be such that thecurrent value of F conforms to the formula F(current) =(M * S * N')/(8*L). If a new value of F is indicated, thenF(current) = F(new). If not, then F(current) = F(initiallyconfigured).


int S_Range (int val) S The value for S must be an integer within the range of 1-32.


int N_Range (int val) N The value for N must be an integer within the range of 1-32.

TL: The value for N must be an integer within the range of12-16.


int N_Max (int val, intmax)

N The value for N must adhere to the range of N ≤ N'.


int NP_Range (int val) N' The value for N' must be an integer within the range of 4-32.


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int CS_Range (int val) CS The value for CS must be an integer within the range of 0-3.


int K_Range (int K_val,int F_val)

K The value for K must be an integer within the range 17/F≤ K ≤ min(32, floor(1024/F)).


int FxK_Div_4 (int FxK_val)

F, K The value of F * K must be divisible by 4.


int HD_Range (int val) High Density(HD)

The value for HD must be either 0 or 1.


int HD_Transport (intHD_val, int N_val)

HD, N TL: The value for HD can be 1 if and only if N=16.


int SCR_Range (int val) ScramblerEnable

The value for SCR must be either 0 or 1.


int SUB_Range (int val) Subclass The value for subclass must be 0, 1 or 2.


int DR_Range (int val) Serial Data Rate The value for DR must be 1, 2, 4. DR value is integerdivisor of initially configured serial data rate. For example,DR=2 means the initially configured data rate divided by2.


int DR_Min (int dr_init,int val)

Serial Data Rate The value for DR must not fall below the minimumallowable range of the target device family. Minimumserial data rate spec:

• Arria V GZ, Arria 10, Stratix V: 2 Gbps• Arria V: 1 Gbps

Refer to the JESD204B IP Core User Guide for the latestinformation on the minimum serial data rate spec. Theminimum data rate value is defined by the DATA_RATE_MIN parameter in the main.h header file. You areresponsible to ensure that the minimum data rate valuefor the target device is correctly set.


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int FC_Range (int val) Frame clock,serial data rate,M, S, N', L

The values of serial data rate, M, S, N' and L must be suchthat the new frame clock value, FC(new) does not exceedthe initially configured frame clock value, FC(initiallyconfigured). Furthermore, the ratio of FC(initiallyconfigured) to FC(new) must be 1, 2, 4 only.


Custom Peripheral Access Macros in macros.c Source File

A set of peripheral access macros are provided for you to access specific information in the CSR of thefollowing peripherals:

• Reset sequencer• JESD204B IP core TX base layer• JESD204B IP core RX base layer• FPGA core control PIO• FPGA core status PIO

The function prototypes of the macros listed in the table below can be found in the macros.h header file.

Table 18: Functions in macros.c


int CALC_BASE_ADDRESS_LINK (intbase , int link)

Calculates and returns the base address based on the linkprovided. In the QSYS system (jesd204b_ed_soc.qsys)address map, bits 16-17 are reserved for multi-linkaddressing. The address map allocation allows for up to amaximum of 4 links to be supported using the existingaddress map. The number of multi-links in the design isdefined by the MAX_LINKS parameter in the main.h headerfile. You are responsible to set the parameter correctly toreflect the system configuration.

int CALC_BASE_ADDRESS_XCVR_PLL(int base , int instance)

Calculates and returns the base address of the TXtransceiver PLL (ATX PLL) based on the instance number.In the JESD204B subsystem (jesd204b_system.qsys) addressmap, bits 12-13 are reserved for multi ATX PLL addressing.The address map allocation allows for up to a maximum offour ATX PLLs per link to be supported using the existingaddress map. The number of ATX PLLs per link in thedesign is defined by the XCVR_PLL_PER_LINK parameterin the main.h header file. You are responsible to set theparameter correctly to reflect the system configuration.

int IORD_RESET_SEQUENCER_STATUS_REG (int link)

Read reset sequencer status register at link and return thevalue.

int IORD_RESET_SEQUENCER_RESET_ACTIVE (int link)

Read reset sequencer status register at link and return 1 ifthe reset active signal is asserted, else return 0.

void IOWR_RESET_SEQUENCER_INIT_RESET_SEQ (int link)

Write reset sequencer at link to trigger full hardware resetsequence.

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void IOWR_RESET_SEQUENCER_FORCE_RESET (int link , int val)

Write reset sequencer at link to force assert or deassertresets based on the val value.

int IORD_JESD204_TX_STATUS0_REG(int link)

Read the JESD204B TX CSR tx_status0 register at link andreturn the value.

int IORD_JESD204_TX_SYNCN_SYSREF_CTRL_REG (int link)

Read the JESD204B TX CSR syncn_sysref_ctrl register atlink and return the value.

void IOWR_JESD204_TX_SYNCN_SYSREF_CTRL_REG (int link , int val)

Write val value into the JESD204B TX CSR syncn_sysref_ctrl register at link link.

int IORD_JESD204_RX_STATUS0_REG(int link)

Read JESD204B RX CSR rx_status0 register at link linkand return value.

int IORD_JESD204_RX_SYNCN_SYSREF_CTRL_REG (int link)

Read JESD204B RX CSR syncn_sysref_ctrl register atlink link and return value.

void IOWR_JESD204_RX_SYNCN_SYSREF_CTRL_REG (int link, int val)

Write val value into the JESD204B RX CSR syncn_sysref_ctrl register at link.

int IORD_JESD204_TX_ILAS_DATA1_REG (int link)

Read the JESD204B TX CSR ilas_data1 register at link andreturn the value.

int IORD_JESD204_RX_ILAS_DATA1_REG (int link)

Read the JESD204B RX CSR ilas_data1 register at link andreturn the value.

void IOWR_JESD204_TX_ILAS_DATA1_REG (int link, int val)

Write val value into the JESD204B TX CSR ilas_data1register at link.

void IOWR_JESD204_RX_ILAS_DATA1_REG (int link, int val)

Write val value into the JESD204B RX CSR ilas_data1register at link.


Read the JESD204B TX CSR ilas_data2 register at link andreturn the value.


Read the JESD204B RX CSR ilas_data2 register at link andreturn the value.






Read the JESD204B TX CSR ilas_data12 register at linkand return the value.


Read the JESD204B RX CSR ilas_data12 register at linkand return the value.





int IORD_JESD204_TX_GET_L_VAL (intlink)

Read the JESD204B TX CSR ilas_data1 register at link andreturn the L value.

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int IORD_JESD204_RX_GET_L_VAL (intlink)

Read the JESD204B RX CSR ilas_data1 register at link andreturn the L value.

int IORD_JESD204_TX_GET_F_VAL (intlink)

Read the JESD204B TX CSR ilas_data1 register at link andreturn the F value.

int IORD_JESD204_RX_GET_F_VAL (intlink)

Read the JESD204B RX CSR ilas_data1 register at link andreturn the F value.

int IORD_JESD204_TX_GET_K_VAL (intlink)

Read the JESD204B TX CSR ilas_data1 register at link andreturn the K value.

int IORD_JESD204_RX_GET_K_VAL (intlink)

Read JESD204B RX CSR ilas_data1 register at link linkand return K value.

int IORD_JESD204_TX_GET_M_VAL (intlink)

Read the JESD204B TX CSR ilas_data1 register at link andreturn the M value.

int IORD_JESD204_RX_GET_M_VAL (intlink)

Read the JESD204B RX CSR ilas_data1 register at link andreturn the M value.

int IORD_JESD204_TX_GET_N_VAL (intlink)

Read the JESD204B TX CSR ilas_data1 register at link andreturn the N value.

int IORD_JESD204_RX_GET_N_VAL (intlink)

Read the JESD204B RX CSR ilas_data1 register at link andreturn the N value.

int IORD_JESD204_TX_GET_NP_VAL(int link)

Read the JESD204B TX CSR ilas_data1 register at link andreturn the NP value.

int IORD_JESD204_RX_GET_NP_VAL(int link)

Read the JESD204B RX CSR ilas_data1 register at link andreturn the NP value.

int IORD_JESD204_TX_GET_S_VAL (intlink)

Read the JESD204B TX CSR ilas_data1 register at link andreturn the S value.

int IORD_JESD204_RX_GET_S_VAL (intlink)

Read theJESD204B RX CSR ilas_data1 register at link andreturn the S value.

int IORD_JESD204_TX_GET_HD_VAL(int link)

Read the JESD204B TX CSR ilas_data1 register at link andreturn the HD value.

int IORD_JESD204_RX_GET_HD_VAL(int link)

Read the JESD204B RX CSR ilas_data1 register at link andreturn the HD value.

int IORD_JESD204_TX_LANE_CTRL_REG (int link, int offset)

Read the JESD204B TX CSR lane_ctrl_* register at linkand return the value.

int IORD_JESD204_RX_LANE_CTRL_REG (int link, int offset)

Read the JESD204B RX CSR lane_ctrl_* register at linkand return the value.

void IOWR_JESD204_TX_LANE_CTRL_REG (int link, int offset, int val)

Write val value into the JESD204B TX CSR lane_ctrl_*register at link.

void IOWR_JESD204_RX_LANE_CTRL_REG (int link, int offset, int val)

Write val value into the JESD204B RX CSR lane_ctrl_*register at link.

int IORD_PIO_CONTROL_REG (void) Read the PIO control register and return the value.void IOWR_PIO_CONTROL_REG (intval)

Write val value into the PIO control register.

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int IORD_PIO_STATUS_REG (void) Read the PIO status register and return thevalue.int IORD_JESD204_TX_TEST_MODE_REG (int link)

Read the JESD204B TX CSR tx_test register at link andreturn the value.

int IORD_JESD204_RX_TEST_MODE_REG (int link)

Read the JESD204B RX CSR rx_test register at link andreturn the value.

void IOWR_JESD204_TX_TEST_MODE_REG (int link, int val)

Write val value into the JESD204B TX CSR tx_test registerat link.

void IOWR_JESD204_RX_TEST_MODE_REG (int link, int val)

Write val value into the JESD204B RX CSR rx_test registerat link.

int IORD_JESD204_RX_ERR0_REG (intlink)

Read the JESD204B RX CSR rx_err0 register at link andreturn the value.

void IOWR_JESD204_RX_ERR0_REG (intlink, int val)

Write val value into the JESD204B RX CSR rx_err0 registerat link.

int IORD_JESD204_RX_ERR1_REG (intlink)

Read the JESD204B RX CSR rx_err1 register at link andreturn the value.

void IOWR_JESD204_RX_ERR1_REG (intlink, int val)

Write val value into the JESD204B RX CSR rx_err1 registerat link.

int IORD_JESD204_TX_ERR_REG (intlink)

Read the JESD204B TX CSR tx_err register at link link andreturn the value.

void IOWR_JESD204_TX_ERR_REG (intlink, int val)

Write val value into the JESD204B TX CSR tx_err registerat link.

int IORD_XCVR_NATIVE_A10_REG (intlink, int offset)

Read the transceiver reconfiguration register at link andaddress offset at offset and return the value.

void IOWR_XCVR_NATIVE_A10_REG(int link, int offset, int val)

Write val value into the transceiver reconfiguration registerat link and address offset at offset.

int IORD_XCVR_ATX_PLL_A10_REG(int link, int instance, int offset)

Read the ATX PLL reconfiguration register indicated by theinstance number instance at link and address offset at offsetand return the value.

void IOWR_XCVR_ATX_PLL_A10_REG(int link, int instance, int offset, int val)

Write val value into the ATX PLL reconfiguration registerindicated by instance number instance at link and addressoffset at offset.

int IORD_CORE_PLL_RECONFIG_C0_COUNTER_REG (void)

Read the core PLL reconfiguration C0 counter register andreturn the value.

int IORD_CORE_PLL_RECONFIG_C1_COUNTER_REG (void)

Read the core PLL reconfiguration C1 counter register andreturn the value.

void IOWR_CORE_PLL_RECONFIG_C0_COUNTER_REG (int val)

Write val value into the core PLL reconfiguration C0counter register.

void IOWR_CORE_PLL_RECONFIG_C1_COUNTER_REG (int val)

Write val value into the core PLL reconfiguration C1counter register.

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Related InformationReference Design Files on page 18

Customizing the Reference DesignThis section contains instructions on how to customize the reference design to various configurations.

Modifying JESD204B IP Core ParametersTo customize the JESD204B IP core parameters to meet your specifications, follow these steps:

1. Launch the Quartus Prime software.2. On the File menu, click Open.3. Browse and select the jesd204b_ed_soc.qsys file located in the project directory.4. Click Open to view the Qsys system in the System Contents window.5. Right-click on the jesd204b_subsystem_0 module and select the Drill into subsystem option. The

jesd204b_system.qsys project opens in the System Contents window.6. In the System Contents window, locate the jesd204b module and double-click it to open the parameter

editor. This brings up the Parameters tab that shows the current parameter settings of the JESD204BIP core.

7. Modify the IP core parameters of the jesd204b module as necessary per your system specifications.When you are done, navigate to File and click Save.

8. Click the Move to the top of hierarchy button to move back to the jesd204b_ed_soc.qsys view.9. Click Generate HDL to generate the HDL files needed for Quartus compilation.10.After the HDL generation completes, click Finish to save your Qsys settings and exit the Qsys window.11.You have to manually change the system parameters in the top level HDL file to match the parameters

that you set in the Qsys project (if applicable). Open the top level HDL file (jesd204b_ed.sv) in any texteditor of your choice.

12.Modify the system parameters at the top of the file to match the new JESD204B IP core settings in theQsys project, if applicable. Refer to the System Parameters section for more details on the systemparameters.

13.Save the file and compile the design in Quartus as per the instructions in the Compiling the HDL andProgramming the Board section.

Related Information

• System Parameters on page 25• JESD204B IP Core on page 14• Modifying the Data Rate or Reference Clock Frequency on page 52• Compiling the HDL and Programming the Board on page 5

Modifying the Data Rate or Reference Clock FrequencyWhen changing the data rate or reference clock frequency, be aware of the relationships between the serialdata rate, link clock, and frame clock as described in the Core PLL section. Change the PLL output clocksettings accordingly to meet the clock frequency requirements. Also note the F1_FRAMECLK_DIV andF2_FRAMECLK_DIV frame clock division factor parameters for cases when F=1 or F=2. Theseparameters further divide down the frame clock frequency requirement so the resulting clock frequency is

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within bounds of timing closure for the FPGA core fabric. See the Core PLL section for more details onclocking requirements and the System Parameter section for more details on the frame clock divisionfactor parameters. Follow the steps below when changing the serial data rate or reference clock frequency.

1. Go through the steps in the Modifying JESD204B IP Core Parameters section to open thejesd204b_system.qsys project in the QSYS window.

2. Double-click the jesd204b module to bring up the JESD204B IP core parameter editor.3. Change the Data rate and PLL/CDR Reference Clock Frequency values as necessary to meet your

system requirements.4. If the clock frequency values for device_clk, link_clk, frame_clk, or mgmt_clk needs to be updated,

double-click the relevant clock source module in the jesd204b_system.qsys System Contents tab andmodify the clock frequency values accordingly.

5. Navigate back to the top level jesd204b_ed_soc.qsys hierarchy.6. If the clock frequency values for device_clk, link_clk, frame_clk, or mgmt_clk needs to be updated,

double-click the relevant clock source module in the jesd204b_ed_soc.qsys System Contents tab andmodify the clock frequency value accordingly.

7. Click Generate HDL to generate the HDL files needed for Quartus compilation.8. After the HDL generation completes, click Finish to save your settings and exit the Qsys window.9. Change the core PLL reference clock or output clock frequency values, if relevant, to match your

system requirements. In the Quartus Project Navigator panel, select IP Components from the pull-down menu and double-click the core_pll entity. This brings up the Altera PLL parameter editor.

10.In the Altera PLL parameter editor, modify the Reference Clock Frequency value under the Generaltab to meet your system requirements. Ensure that the reference clock frequency value matches theones set for the jesd204b module in the Qsys project. Also, change the outclk0 group settings (whichcorrespond to the link clock) and outclk1 group settings (which correspond to the frame clock) ifnecessary. Ensure that the link clock and frame clock values satisfy the frequency requirements asdescribed in the Core PLL section.

11.When you are done with the edits, click Finish to save your settings.12.If the frame clock settings (outclk1 of the core_pll module) are such that F1_FRAMECLK_DIV or

F2_FRAMECLK_DIV values need to be changed, modify the relevant system parameters in the toplevel HDL file, jesd204b_ed.sv as described in the Modifying JESD204B IP Core Parameters section.

13.Save the file and compile the design in Quartus as per the instructions in the Compiling the HDL andProgramming the Board section.

Related Information

• Modifying JESD204B IP Core Parameters on page 52• Core PLL on page 16• Compiling the HDL and Programming the Board on page 5

Implementing a Multi-Link DesignThe reference design Qsys projects, top level HDL, and software source code are designed for easyimplementation of a JESD204B multi-link use case. In the Qsys project, each link in a JESD204B multi-link use case corresponds to a single instantiation of the jesd204b_subsystem module, which includes theJESD204B IP core and other support modules. This section assumes that each jesd204b_subsystem modulein the multi-link design has identical parameter configurations. In the top level HDL, each link in aJESD204B multi-link use case corresponds to an instantiation of a transport layer TX and RX pair and apattern generator and checker pair (assuming duplex data path configuration). The HDL uses the Verilog

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generate statement using the system parameter LINK as an index variable to generate the requisitenumber of instances for the multi-link use case (see System Parameters section for more details). Thissection assumes that each transport layer TX and RX pair and pattern generator and checker pair in themulti-link design has identical parameter configurations. In the software source code, all relevant softwaretasks are coded with multi-link capabilities. The software parameter that defines the number of links inthe design is the MAX_LINKS parameter in the main.h header file (see Software Parameters section formore details). In a multi-link scenario, each software action performs an identical task on each linkstarting with link 0 and proceeding sequentially until the link indicated by the MAX_LINKS parameter.

Figure 7: Multi-Link Use Case (Data Path Only) Block Diagram

This figure illustrates the block diagram of a multi-link use case. Only the data path is shown in the figure.

PatternGenerator

Avalon-ST User Data(Link 0)




Test PatternGenerator

Test Pattern

Top-Level Qsys Systemjesd204b_ed_soc.qsys

Assembler(Transport

Layer)


Layer)

JESD204BSubsystem

tx_serial_data (Link 0)

rx_serial_data (Link 0)

tx_serial_data (Link 1)

rx_serial_data (Link 1)

Top-Level RTL (jesd204b_ed.sv)

Avalon-ST

Avalon-ST


lane


lane

PatternGeneratorTest Pattern

Generator

Test Pattern

Assembler(Transport

Layer)


Layer)

JESD204BSubsystem

Avalon-ST

Avalon-ST


lane


lane

(Link 0)

(Link 1)

Checker

Checker

To implement a multi-link design, perform these procedures:

1. Edit the Qsys project.2. Edit the top level HDL file.3. Edit the software source code.

The following sections describe these procedures in detail.

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Editing the Qsys Project

1. Open the top level Qsys project (jesd204b_ed_soc.qsys) as per the instructions in the Qsys systemsection.

2. Each JESD204B link is represented by a single jesd204b_subsystem instantiation. To implement multi-links in Qsys, duplicate the jesd204b_subsystem instantiations. In the System Contents tab, right-clickon the jesd204b_subsystem_0 module and select Duplicate. This duplicates the jesd204b_subsystem_0module to a new module called jesd204b_subsystem_1.

3. Connect the jesd204b_subsystem_1 ports as shown in the table below. Any ports not described in thetable below should be exported. To export a port, double-click on the Double-click to export label inthe Export column of the System Contents tab.

Table 19: Port Connections of jesd204b_subsystem_1 Module

Ports of jesd204b_subsystem_1Module

Connection

device_clk device_clk.clk

do_not_connect_reset_0 mgmt_clk.clk_reset



frame_clk frame_clk.clk

jesd204b_jesd204_rx_int hps_0.f2h_irq0

ILC.irq

jesd204b_jesd204_tx_int hps_0.f2h_irq0

ILC.irq

link_clk link_clk.clk

mgmt_clk mgmt_clk.clk

mgmt_reset mgmt_clk.clk_reset

mm_bridge_s0 fpga_only_master.master

mm_bridge_0.m0

reset_seq_irq hps_0.f2h_irq0

ILC.irq

reset_seq_pll_reset Do not connect

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Ports of jesd204b_subsystem_1Module

Connection

reset_seq_reset_in0 mgmt_clk.clk_reset

4. Adjust the IRQ port count of the ILC module to accommodate new interrupt ports of thejesd204b_subsystem_1 module. Double-click the ILC module in the System Contents tab. In the ILCmodule Parameters tab, adjust the IRQ_PORT_COUNT parameter to 9.

5. Adjust the interrupt priorities of the interrupt ports (for example, jesd204b_jesd204_rx_int ,jesd204b_jesd204_tx_int, reset_seq_irq) of the new jesd204b_subsystem_1 module as necessary to meetyour system specifications. Click on the priority number of the relevant interrupt ports in the IRQcolumn of the System Contents tab and edit accordingly. The lower the number, the higher thepriority.

6. Assign the address map of the jesd204b_subsystem_1 module. Refer to the Top Level Qsys Address Mapsection for more details on the top level Qsys project address map. Bits 16-17 of the Avalon-MMbridge (0x0004_0000 base address) indicate the link number. Assign the address map of thejesd204b_subsystem_1 module as shown in the figure below.

Figure 8: Multi-Link Address Map

Notice that bits 16-17 of the address map denote the link indicator. For subsequent links, incrementthe link indicator accordingly. Up to 4 links can be supported in this manner.

Attention: Do not exceed the maximum number of links (4) that the address map can support.

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7. Repeat steps 2 – 6 for subsequent links in your design.8. Click Generate HDL to generate the HDL files needed for Quartus compilation.9. After the HDL generation completes, click Finish to save your Qsys settings and exit the Qsys window.

Editing the Top Level HDL File

1. Open the top level HDL file (jesd204b_ed.sv) in any text editor of your choice.2. Modify the LINK system parameter to reflect the number of links in your design.3. Replace the single-link jesd204b_ed_soc instance with the multi-link one generated from Editing the

QSYS Project section above.4. Reconnect in a similar way all the ports that are similar between the single-link jesd204b_ed_soc

instance and the multi-link one.5. The ports that are new in the multi-link jesd204b_ed_soc instance are the ports associated with the

jesd204b_subsystem_1 module. Connect the ports that have jesd204b_subsystem_1_* prefix as shown inthe example below:

.jesd204b_subsystem_1_jesd204b_txlink_rst_n_reset_n(tx_link_rst_n[1]),

6. Repeat step 5 for subsequent links in your design.7. Save the file and compile the design in Quartus as per the instructions in the Compiling the HDL and

Programming the Board section.

Ensure that any additional pins that are available from the addition of multi-links (for example,tx_serial_data and rx_serial_data pins) have the proper pin assignments in the Quartus settings file(jesd204b_ed.qsf).

Related Information

• Implementing a Multi-Link Design on page 53For more details on implementing multi-link designs.

• Compiling the HDL and Programming the Board on page 5

Editing the Software Source Code

1. Open the main.h header file in any text editor of your choice.2. Change the MAX_LINKS parameter to match the number of links implemented in your design and

save the file.

Attention: Do not exceed the maximum number of links (4) that the address map can support.3. Compile and execute the source code as per the instructions in the Setting up the Software Command

Line Environment section.

Related Information

• Compiling the HDL and Programming the Board on page 5• Setting up the Software Command Line Environment on page 5• Top Level Qsys Address Map on page 10• JESD204B Subsystem Address Map on page 16• System Parameters on page 25

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AN 755 Document Revision HistoryDate Version Changes

December 2015 2015.12.30 Initial release.

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