Bao Cao Tuan 3_dsPIC TV

8/2/2019 Bao Cao Tuan 3_dsPIC TV

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dsPIC

digital signal controller


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Part I :

Gii thiu v kin trcca dsPIC30F


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Nhng im kin trc ni bt

Cc chc nng MCU & DSP tch hp trong 1CPU

C kiu kin trc bus Harvard c sa i

Cu lnh 3 ton hng : A = B + C

Nhiu ch nh a ch

16x16bit general purpose register set p ng ngt nhanh


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Cc thanh ghi c bn


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T chc b nh chng trnh*


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T chc b nh d liu

B nh d liu 64 KB khng gian nh

C th nh byte hoc word

16-bit t nh word

D liu c sp xp theo dng little endianLower (even) address stores LS byte

Higher (odd) address stores MS byte


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Bn d liu nh*


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Cu lnh DSC-MAC trong bn b nh d liu*


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Tng quan v cu lnh

84 cu lnh ( Bao gm c DSC) Gn nh tt c l mt t (24 BITs) C 4 cu lnh 2 t

Hu ht cc cu lnh u chim 1 chu k, loi tr: Thay i th t ca chng trnh (2 cycles) Lnh s dng bng (2 cycles) Lnh di chuyn kp (2 cycles) Lnh DO (2 cycles)

Lnh chia (18 cycles) Cu lnh 3 ton hng

A = B + C Tng hiu sut ca vit code (Assembly or C)


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Cc nhm cu lnh

Cc cu lnh MOVE

Cc cu lnh MATH

Cc cu lnh LOGIC

Cc cu lnh ROTATE/SHIFT

Cc cu lnh thao tc vi BIT

Cc cu lnh COMPARE/SKIP

Cc cu lnh PROGRAM/FLOW

Cc cu lnh SHADOW/STACK

Cc cu lnh CONTROL

Cc cu lnh DSC


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Cc ch nh a ch Cc ch nh a ch :

C hu NOP, RESET, PUSH, POP, Bng ch Thanh ghi Mng thanh ghi W (16x16 Bit)

Trc tip b nh Gin tip thanh ghi Truy cp hu nh ton b 64KB With pre-inc or pre-dec With post-inc or post-dec

With signed literal offset Ch s thanh ghi :Thanh ghi c s v ch s thanh ghi Ch c bit

Modulo (s dng trong b nh m vng)Bit-Reversed (for FFT) (sp xp d liu trong khai trin Furie)


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S khi CPU ca dsPIC30F


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Part II :

Nhng c trng ca hthng tch hp


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Interrupts

Quyn u tin v Vector ngt C hn 45 ngun ngt (khng bao gm traps and

reset)

C 7 mc u tin ngt

c b tr c nh trong : 5 cycles (fromIRQ to IRS entry)

PC v byte thp ca thanh ghi trng thi c ctgi


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Interrupts

Stack ngt c b tr trn SRAM vi s tng kim tra bin gii

S xp lng ngt Ngt c mc u tin caohn c th ngt ngt c mc u tin thp hn

Cu lnh DISI c th treo ngt trong N chu k

Mt cch nhanh chng bo v nhng on codenguy kch

Cm cc ngt c mc u tin t 06


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Bng Vector ngt


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Alternate Interrupt Vector Table

C th t ging nh IVT

C th gi vi s thit lp a ch ISR khc.Cho php ngi lp trnh s dng con tr th 2 tn dng ngoi vi vi cch khc.

C th c s dng vi mc ch chun onphn mm. VD mun chng trnh UART gid liu test ln PC trong khi test ng dng


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Traps(Gi CPU) Oscillator Failure Trap

Xung nhp chnh b sai (dng dao ng trong RC) Address Error Trap:

D liu nm ngoi vng khng gian nh

Su truy nhp nm ngoi khng gian chng trnh D liu c v ghi khng tng thch

Stack error trap Lp trnh trn thanh ghi gii hn Stack pointer nm trong vng thanh ghi c bit

Math error trap Chia cho s 0

Trn thanh ghi tch ly


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Reset h thng Reset khi bt ngun

Thi gian tr c th lp trnh : 0, 4, 16, 64 ms

MCLR (External Reset Pin) Thc hin cu lnh Reset Watchdog Timer (WDT) Reset

Thc hin t chnh dao ng RC ca n Thi gian gii hn : 2ms 16s

Brownout Reset (BOR) Mc in p c th lp trnh

Reset khi vn hnh chng trnh sai Tm thy cu lnh sai

S dng W lm con tr a ch m ko nh ngha


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Ngun xung


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Qun l nng lng Thc thi cu lnh PWRSAV :IDLE mode :

CPU dng hot ng, nhng xung h thng vn chy

Ngoi vi vn tip tc chy (tr phi b lm cho ngng)

Hot ng tr li : WDT, thay i tn hiu vo chn,interrupt, reset

Sleep mode :

CPU v xung h thng u dng Ngoi vi cng b dng

Hot ng tr li : WDT, thay i tn hiu vo chn,chn ngt ngoi, reset, hoc s kin ngoi vi no


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Part III :

Module so snh tngt(AnalogComparator)


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Analog Comparator

Mt s c im : chnh xc +/- 1% ( trong di in p Vdd )

01,2V Ref or Avdd/2 or ngun chun bn ngoi

1024 bc ( i.e. 1,2mv, 2,4mv, .., 1,2V)

Tr so snh : ~20 ns


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Analog Comparator

Mi b so snh tng t u c 2 thanh ghiiu khin :


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S khi ca b so snh tc cao


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Part IV :

Module ADC (Analogto Digital Converter)


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ADC

10 bit , chnh xc +/- 1 bit 2 triu ln trch mu/ 1s (2 MSPS)

612 knh u vo

Di u vo tng t : 0 5V

4 u vo K Sample/Hold (S/H) u vo 2 v 4 c th lm vic ng thi

S dng ngun chun bn trong hoc bnngoi


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S hot ng ca ADC

S bin i lun din ra trong mt cp u votng t (AN0,AN1), (AN2,AN3) , Mi cpmiu t in p v dng in o lng

Yu cu ngt c to ra trn mt cp c bn.Yu cu ngt c th c to ra khi hon thnhln bin i th 1 hoc th 2 ca cp

Mi chn u vo tng t u c lin ktvi thanh ghi d liu u ra. B m d liu(cc thanh ghi) th khng thc hin nh FIFO.

Chng c s hu duy nht bi mi u vo


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S khi ca ADC


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Thanh ghi iu khin ADC

ADC module c 2 thanh ghi iu khin :


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Thanh ghi trng thi ADC

Module ADC c mt thanh ghi trng thi

Thanh ghi trng thi ch cho bit cp no bin ixong (p = pair)

Nu chn EIE = 1 th ngt c th c to ra trc

khi chn PxRDY tng ng c lp = 1


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Cp u vo ADC

Mi cp u vo c thanh ghi iu khin vtrng thi 8 bit

Mi thanh ghi ADCPCx iu khin v chtrng thi ca 2 cp u vo


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Part V :

Module PWM


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Cc ch PWM

Chun ( Standard)

B, b xung (Complementary)

y ko ( push pull ) Nhiu pha ( Multi phase )

Pha c th thay i ( Variable phase )

Current reset Current limit


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Thanh ghi iu khin c s

thi gian chnh (PTCON)


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Thanh ghi Period

nh ngha thi k thi gian c s chnh chovic pht pwm. 3 bit thp nht khng cdng


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Thanh ghi SEVTCMP

SEVTCMP lu gi gi tr c so snh vi cs thi gian chnh cho s pht PWM. Khi gitr SEVTCMP bng gi tr thi gian chnh mt

s kin t bit pht xung c to ra. Xungny b chia bi thang t l c bit trc khic a ti ADC


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Thanh ghi MDC

MDC( Master Duty Cycle) c th s dng bibt k b pht PWM no nh l ngun chodutycycle.(D = /T)


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Thanh ghi PWM control

Cho php ngt vo bo co trng thi. N cngiu khin ngun cho dutycycle, cho php ch thi gian c s c lp, v nh ngha s

vn hnh ca logic thi gian cht.


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Thanh ghi Duty Cycle

Mi b pht pwm c mt thanh ghi DutyCycle ca chnh n

Gi tr duty cycle c th c update bt klc no trong chu k pwm nu bit IUE trongthanh ghi PWMCONx = 1.

Ch r thi gian ON trong tn hiu PWM


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Thanh ghi Phase

Gi tr phase lm tn hiu PWM sm hn mtkhong thi gian

C th c update bt k thi gian no trongchu k PWM. Gi tr phase mi c hiu lckhi kt thc mt chu k PWM.


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Thanh ghi Dead Time

iu khin s tng hay gim ca gc PWM

Mi thanh ghi DTRx v ALTDTRx ch rkhong thi gian cht cho s ln xung cagc tn hiu PWM

Hai bit thp nht khng c dng


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Thanh ghi iu khin I/O

iu khin quyn s hu v cc tnh ca chnPWM, v ch u ra ca b pht pwm (pushpull, b, )

iu khin gi tr d liu u ra trn chnPWM trong s kin fault, current limit.

Ngi lp trnh cng c th iu khin u rapwm qua IOCONx


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Part VI :

Mch np


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Mch np ICD2 USB

L mch np thng dng cho dng dsPIC

C th giao tip vi MPLAB debug trctip trn bo

n gin, d ch to


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Mch np PG2C

Np qua cng ni tip

S dng chng trnh np winpic800

S dng phng php np ICSP ( In CircuitSerial Programming )

Khng c kh nng debug trn bo

Rt n gin


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Part VII :

Chng trnh dch


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MPLAB

Khi vit chng trnh cho dsPIC, ta s dngmi trng MPLAB.

Nhiu thng tin thit lp cho cc cng vic linquan c t trc trong MPLAB gip qunl c vic vit chng trnh, m phng, npchng trnh vo chip mt cch thng nht

Trong mi trng MPLAB ph bin s dnghai ngn ng ASM : ASM30 .

C : C30, CCS


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Bao Cao Tuan 3_dsPIC TV