Bản đã dịch của trang TAI LIEU DICH KT

8/6/2019 Bn dch ca trang TAI LIEU DICH KT

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HT: inh Th Tuyt MaiHV: K20 HTTTNgy 02/07/2011

Bn dch ca trang TAI LIEU DICH KT & MANG MT.docx

Chng 3: Kin trc b vi x l

3.1 Gii thiu

Khi tranh lun v khi nim "kin trc my tnh" a ra mt khinim, t khng c nh ngha chun no cho cc chuyn gia. Tm kimqua cc ti liu c th tm thy mt s nh ngha v khi nim ca mytnh: kin trc. Myers a ra khi nim [Myrs 82] da trn vic xy dngIBM ban u:

Kin trc my tnh l mttrngtru tng ca mt h thng mytnh vt l nh c bit bi mt chng trnh ngn ng my hoc mtngi bin dch. Ni cch khc, kin trc my tnh cp n nhng khacnh ca mt h thng my tnh c hin th cho cc lp trnh tinh xonht, iu hnh mc bo v c quyn c li nht (nu mc ththc hin). Bao gm tt c cc iu khin truy cp bi bt k thit lp chdn no, ch dn v nh dng d liu, cc ch a ch v cc chi titkhc cn thit vit bt k chng trnh trn h thng c xem xt.

Nhiu ngi nhn xt rng khi nim trn l khng ng; tuy nhin,cho n nay, khng ai a ra mt khi nim r rng. Cho n khi khinim mi c xy dng bi Myers v c s dng. S la chn khinim l ch c cp trong chng ny, i vi kin trc ca bvi x l: thit lp ch dn, nh dng d liu, nh dng ch dn, v phngthc gii quyt.

Tri ngc vi kin trc my tnh, t chc my tnh cp n vicsp xp vt l v kt ni cc thnh phn trong mt h thng my tnh, vc im ca nhng thnh phn . Cc chi tit ca t chc my tnh c

th rt r rngcho cc lp trnh vin. V d, mt ch mc tm np trc(prefetch)rt r rng cho ngi dng.

C h thng con my tnh c th c hoc khng thuc v kin trctrong h thng my tnh khc. Trong nhiu h thng b nh cache qun l

bi phn cng v thm ch khng c mt ch dn iu khin b nh cachehoc nh hng trc tip bng bt k cch no. l hon ton minh bchcho ngi dng. Trong trng hp b nh cache l difitely mt phn ca


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t chc v khng phi ca kin trc. Mt khc, mt s h thng hin i,chng hn nh M88000, khng c ch dn m nh hng n b nhcache.Trong trng hp ny, b nh cache tr thnh mt phn ca kintrc my tnh, hin th cho cc lp trnh vin. Thc t, bt k b phn noca mt h thng my tnh c th c to nn mt phn ca kin trc camt thit k hp l ca cc ch dn cho php cc chng trnh iukhin b nh cache v nh hng n ni dung . Cc tp lnh l mtkha cnh quan trng ca bt k h thng my tnh, t xc nh ng vspecifieschnh xc nhng g h thng ny l kh nng thc hin. Cc biu khinvi x l c ni n trong phn tip theo. c gi quen thucvi nhng kha cnh c bn ca kin trc my tnh c th b qua chngny.

3.2 Tp lnh

Tp lnh thc s l mt trong nhng tnh nng chnh ca kin trc mytnh, xc nh v m t kh nng ca bt k h thng my tnh no baogm cc b vi x l. To thnh mt tp cc hot ng c th m mt hthng c th thc hin c. Chng ta c th phn bit cc loi ch dn:

1. Lnh di chuyn d liu2. Lnh s hc v logic3. Lnh Shift v xoay4. Lnh kim sot iu khin5. Lnh thao tc vi bit

6. Lnh iu khin h thng7. Lnh Floating-point8. Lnh n v chc nng c bit

Cc loi lnh trn s c ni chi tit hn trong phn tip theo.

Lnh di chuyn d liu thc hin vic di chuyn thng tin t mt vng nvng khc trong mt h thng my tnh. Vic di chuyn c th

Thanh ghinthanh ghi

B nh ti thanh ghi hoc thanh ghi n b nh

B nh n b nh

"thanh ghi " c hiu l bt k thanh ghitrong file thanh ghi CPU. "bnh" c hiu l bt k vng no trong khng gian b nh chnh.

Lnh di chuyn d liu thng c hin th di dng hp ng:


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mov source, destication

or

MOV scr, dst

src (source) l ton t a ch ngun v dst (im n) l ton hng a chch. Cc a ch trn c th va tham chiu n mt thanh ghi trong tpthanh ghiCPU hoc mt a ch trong b nh.

Trong mt s h thng c s phn bit gia ton t iu khin trn cckch thc khc nhau ca d liu. Kch thc d liu thng l:

B byte 9 bits

H Halfword 16 bits

W Word 32 bits

D Doubleword 64 bits

i vi mi lnh MOV trn c th c th hin:

MOVB: di chuyn mt byte

MOVH: di chuyn mt halfword

MOVW: di chuyn mt t

MOVD: di chuyn mt doubleword

Cn lu trong mt s h thng (c bit l nhng ci tin t 16-bitsn phm) t gii hn p dng cho mt mc d liu 16-bit, v mt mc 32-

bit c gi l mt doubleword hoc longword. Nhng khc bit s tr nnr rng trong cc tranh ci ca cc b vi x l c bit t phn 2 n 4.

Cc lnh di chuyn d liu bao gm cc ton t u vo v u

ra. Trong nhiu b vi x l mt phn ca khng gian a ch b nh ldnh ring cho u ra - u vo (I /O) v cc thit b v b giao din. iuny constutes b nh nh x I/O. Trong trng hp ny ton t I/O cthc hin bi cc lnhtruy cp b nh thng xuyn(MOV). Cc h thngkhc (Intel, xem Phn 2) cng c mt khng gian a ch I/O v iu khinI/O c bit, chng hn IN v OUT (xem Phn 2), ngoi ra c b nh-nhx I/O capability.


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Mt s h thng thc hin truy cp b nh t CPU bng cch sdng LOAD v lnh STORE. Cc lnh LOAD

LOAD madr, ... ... ..

Ti mt mc d liu t mt vng b nh, ti a ch "madr" vo mt CPU

register. Lnh STORE

STORE ... ... ...

Kho ni dung ca cc CPU register ri vo mt vng b nh ti a ch"madr".

Lnh lin quan n thao tc chng ton t, nh PUSH v POP, cngri vo cc th loi ca lnh chuyn d liu. Trong mt s h thng, nhMotorola, ngn xp c ch tc vi cc lnh MOVEMENT, s dng mt

s kt hp c bit ca ch addressing (xem phn 3). Bin th khc cadi chuyn d liu s c tho lun cng vi cc v d c th ca b vi xl t phn 2 n 4.

Trang 5

Lnh s nguyn c cu trc nh sau:

1. Lnh hai ton t:

... ... ... ... ... ... ... ... ... ... ... ... ....

Trong trng hp lnh chia (DIV) mt im n thng l tng gpi lu tr thng v phn d.

2. Lnh ba ton t:

... ... ... ... ... ... ... ... ... ... ... ... ... .. (Mo khong doc duoc)

"," th hin bt u ca mt ch thch, (x) th hin ni dung ca x, src,

src1, src2 l v tr ca cc ton t ngun, v dst hin th ch. a ch cacc ton t c th c th hin trong mt lot cc cch gii quyt vn ,c ni trong phn 3.5.

Vic s dng kt qu lnh ba ton t trong mt m nh gn hn. iuny d thy t v d n gin di y. HLL th hin:

C: = A + B; C {A} + {B}


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thc hin cng vi mt lnh hai ton t, chng ta cn:

ADD A, B; {A} + {B} E

STORE B, C; {B} C

Vi lnh ba ton t, c th c thc hin trong mt dng lnh n:

ADD A, B, C

Trong mt s b vi x l c mt phin bn ring bit ca lnh s hc chocc loi d liu khc nhau, nh byte, halfwords, v word. Nh lnh MOV,cc k hiu c th tng ngl Adde, ADDH, v ADDW.

Trong nhiu h thng c php nhn v chia khng du v c du. Cc khiu trong nhng trng hp ny c th c MULS v divs, v Mulu v

DIVU cho cc ton t khng du.

Trong mt s trng hp, ty chn khc nhau ph thuc vo kch thcton t nhn v chia. Trong trng hp ny

Trang 6

16 x 16 bit operands, 32 bit product



B vi x l mi nht l 32 hoc 64 bit tng ng vi 32 - v 64 - bit CPUregister. Nu h thng 64-bit, mt v tr ch l c cung cp.

V d: Trong Motorola MC68030 32x32-bit, sn phm 64-bit k kt (xemphn 3)

MULS l src, DMDL; {src x {DL}} {..}

L indecates ton t 32-bit (longword), v Dh v DL l 32-bit register dliu. ng k nht 32 bit ca sn phm 64-bit vo Dh, v t nht 32 bit voDL (trong c ccton t khi to)

Php chia cng c th c c trng cho kch thc ton hng khc nhau,nh


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Ton hng 32/16 bit, 16 bit dnh cho thng (kt qu ca php chia), 16bit dnh cho phn d.

Ton hng 32/32 bit, 32 bit cho thng, 32 bit phn d




V d: Trong MC 68030 (phn 3), 64-bit, c lu tr trong hai 32-bit dliu register (Dr, Dq) c chia php chia c du ca s chia theo a chsrc:

.src, Dr; Dq; {Dr, Dq} src dr(remainder; Dq (quotient))

Trong tt c cc trng hp khi kch thc ca mt ton t hoc kt quln hn kch thc ca CPU register chun , kin trc nn cung cp aim thch hp, nh minh ha trong v d trc, hoc bt k cchno. Trong mt s h thng, nhiu thanh ghi CPU c xc nh trc cth c vnh vin c ton t nhn v chia cc v kt qu, v n c thchin trong b intel 80x86 (phn 2).

Ton t iu khin logic two -ton t thng c thit k mt cch tngt nh cc lnh ADD hay SUB:

AND src, dst; src AND dst dst

OR src, dst; src OR dst dst

XOR src dst; src XOR dst dst

XOR l c quyn ton t OR. Tng t nh ADD hay SUB, cc ton tlogic cng c th c ba ton t trong mt s h thng nh

AND src1, src2, dst; src1 AND src2 dstTrong nhiu h thng cng b sung hoc ton t iu khin nNOT:

NOT dst; . dst

Trang 7


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ni t # i t nhng s b sung h l ca dst nh vy l 0# = 1, 1 # =0.

Ch dn so snh thng c phn loi nh l mt ch dn logic, mc dt thc chtl thc hi n . Bi u hi n cbn ca n l

C M Src1, src2; {src2} - {src1}, cbthay i.

Kt qu ca php tr l khng lu tr bt c ni no, v c so snh vigi tr ban u, src1 v src2, khng thay i. Cc cthay i nh sau:

Nu (src2) = (srcl), ckhng Z c thitlp.

Nu (src2) < (src1), l du hi u cS c thit lp, t s khc bi tlti u cc.

Cc ki m tra sau khi cc ch dn so snh bng cch s dng c i uki nch dnoranch, c tho lun sau trong phn ny.

Trong cc th h trc ca my tnh [Hays 88, chng 1] thay i v hotng c thc hin ti mt thi i m, tri hoc phi. Nhi ub vi x l hin i c mt h thng ph logic thm vo trongC , nh mtl i shi t r[Prot 88], cho php thay i nhanh bi nhi u bit c th (ln ti 31) ti mtthi im. C hailoi dch chuyn cbn [Wake 89]:

1. Thay ilogic:ton hng c chuyn sang tri hoc phi bi n bit,

vs khng c chuyn vo cc vtr n b trng. Thng thng, cnhCl mt phn ca hot ng nh minh ha trong hnh 3. 1.

2. Chuyn i s hc:Cc ton hng thay i c coil du hiu 2sthms. Mt s hc chuyn tri ca mi bittng ng vi mt php nhn vi2, v mt s hc phithay i bng cch mi bittng ng vi chia cho


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2. Cc hot ng dch chuyn s hc c minh ha trong hnh 3.2. S hc phi thay i (SAR) m rng bit du [bit quan trng nht (MSB) bnphi mt vi bit thay i. S thay i tri l ging c bn nh s chuyndch tri logic.

C 2 ton hng xc nh cho mt ch dn thay i. Mt ch nh c th

mt s bit c chuyn i, v ch nh khc ton hng c thay i.

V d

SLL Dc, Ds; thay i logic li ni dung ca thanh ghi Ds bimt s bitbng vi ni dung thanh ghi Dc.

B m SLR, Ds; s thay i logic ng ni dung thanh ghi ca Dsngaylp tc mt s bit c xc nh bi "b m".

Trong nhiu h thng c th xc nh mt lot a ch thay v s dng Ds,bao gm vng trong b nh. Cng c th xc nh kch thc ca tonhng cchuyn (byte, halfword; word) bng cch gn thm k t thchhp ch dn, chng hn nh SARB, SARR. SARW


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Cch quay, minh ha trong hnh 3.3, c biu th mt cch tng t:

R L Dc, Ds, xoay Ds tri bi (Dc) bit.

R RDc, Ds; xoay Ds phi bi (Dc) bit.

Kim sot ch dn chuyn giao bao gm ch yu

1. Nhy hocnhnh

2. Gi chng trnh con

3. Tr v t chng trnh con

Tt c ton hng trn c th c iu kin hoc khng iu kin. Nhnhkhng c iu kin v chng trnh con c gi c dng


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BRA addr

CALL subname

addr v subname l nhng a ch trong b nh: C hai a ch c th lbiu tng; subname cng l tn ca chng trnh con c gi. S tr li

t ch dn chng trnh con thng c dng

RET

Mt s h thng cng tr li c bit t ch dn ring (RTE)

Nhnh c iu kin thng c da trn trng thi ca c, chng hn

C, c nh c thit lp nu thc hin t mt php ton ALU.

Z, Zero c thit lp nu kt qu ca php ton cui cng l khng.S, c du c thit lp nu kt qu ca php ton cui cng l m.

V, c trn c thit lp nu php ton trn

Nhnh c iu kin c dng:

BZ addr; branch to addr nu Z = ..

BNZ addr; branch to addr nu Z = .

V tng t cho cc c khc: BC, BNC, BS, BNS, BV, BNV. C th ciu kin phc nh

BBE addr; nhnh trn hoc di, nhnh addr nu C OF Z = 1

BBE thng c a ra sau khi cc ch dn (so snh) CMP (xem trn). Nu (src2)


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Offset, trong bit

Kch thc chiu rngca trng c th ca bit, v phn b v tr catrng trong mt t. Phn b c o bt u vi cc bit t quan trng(LSB) 0. Tt nhin, trong mt s h thng phn b c th c nh nghatheo mt cch khc nhau. Trong v d minh ha trong hnh 3.4, rng

trng bitl 5 bit v phn b l 10 bit. Trong hp ng, iu ny c th khiu l:

5

Cch khc, ngita c th titrc haithng s trn (5 v 10 bit) vo cctrng c th ca mtthanh ghiCPU, ni rng, Rb, v sau s dng Rbnh ton hng trong mt ch dn thao tc bit. Chiu rng v phn b cctrng trong thanh ghiRb c th 5 bit, 25 = 32, v chiu rng v phn bc gii hn nh hn 31.Tuy nhin, c h thngphn b c o t mta ch c th, trong trng hp gi tr c th cao hn nhiu.

Cc ch dn c thc hin trn cc trng bit ca cc loi sau y:

Kim tra, nh hng n cLm sch

Thitlp

Ly ra v chuyn n ni khc

Ly ra v mrng du

v nhng ci khc. Ch dn ca trng bit c th s c trnh by cngvi cc h thng thc (xem phn 2 n 4), bt c ni no thc hin.

Ch dn iu khinh thng cho php ngi s dng nh hng trctip hot ng ca b vi x l v h thng ph khc nh MMU v b nhcache. Tt c cc h thng c mt ch dn HLT (tm dng) dng hot ngca b x l. Nhiu h thng c ch dn m tun ra hoc lm mt hiu lctrong b nhcache hoc TLB.Trong mt s h thng c ch dn cho phpti cc mc TLB. Mt sh thng c mt ch dn KHA c bit nhm


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ngn chn cc h thng khc s dng cc h thng bus.N gy ra mt tnhiu kim sot KHA c kch hot. Bus b kha cc h thng khccho n khi tn hiu LOCK ngng hot ng. Cc tn hiu chm dt hotca KHA c thc hin bng phn cng hoc s dng mt ch dnUNLOCK c bit, nh thc hin trn Intel 80860 (xem phn 41). Chdnd liu di chuyn hoc t thanh ghi iu khin c coi l ch dn iukhin h thng trong mt s trng hp.

Hng dn du chm ngc thc hin trn cc trn chip FPD. Cc thh trc ca b vi x l s dng mt off-CPU du chm ngcoprocessor. Nhm hng dn ny bao gm chuyn d liu du chm ng(FMOVI), s hc (FADD, FSUB. FMUL, FDIV), so snh (FCOMP), cn

bc hai (FSQRT), gi tr tuyt i (fabs), v cc chc nng siu vit (FCOS, FSIN) v nhng chc nng khc, ty thuc vo h thng (xem phn2 n 4). Phn bit gia diadic, hai ton hng (FADD, FMUL, v php

ton 1 ngi (fabs, FSIN) hng dn.Hng dn chc nng c bit thc hin cc hot ng c th ca khichc nng c bit (SFU), ty thuc vo bn cht ca n. V d, Inte180860 ca SFU (xem Phn 4) l mt khi ha. N c 10 hng dn linkt vi n, chng hn nh

Faddp thm bng cch trn im nh

Pfaddp thm ng ngbng cch trn im nh

Mt loi hng dn c bit c gi l hng dn chi tit c s dngtrong vic qun l semaphores, iu khins truy cp vo cc b phnquan trng trong a x l[AlGo 89, Hwan 93, Ston 93. Tabk 90a]. Nhnghng dn ny to nn mt s kt hp ca vic di chuyn d liu v s hchoc hng dn logic. Nhiu b vi x l hin i c thit k trc chovic thc hin a x l, v nhng hng dn bao gm hng dn chitit. m bo thc hin chnh xc semaphores, cc hot ng x lchng phi c lin tc. Hng dn nh vy gi l chi tit.

Mt dng chung ca mt hng dn chi tit thc hin trn nhiu h thngthc l hot ng th nghim v f (TAF) [thut ton 89], f (V, E) l mt shc hoc hm logic ca hai gi tr V v e. Mt trng hp c th ca tonhng TAF, s dng rng ri, f = OR (V, TRUE), e = TRUE. Ton hngny c gi l th nghim V thit lp (TAS). TAS l hng dn lin tip(chi tit), hot ng vi mt chu k c-sa-vit (RMW). c gi tr casemaphore nm trong b nh, kim tra l 0 hay 1, v t nhng trngthim c thch hp (c mt phn ca chu k). Sau , kt qu thu c


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thit lp gi tr semaphore (thay i mt phn ca chu k) v lu n trli v tr ban u ca n trong b nh (Lu mt phn ca chu k). Khngc b x l no c th truy cp vo h thng bus v semaphore trong chuk RMW lin tc. Nh vy truy cp c c th thc hin, cc kim tra cth mang li kt qu sai, do lm gin on cc hot ng.

Mt dng khc ca mt hng dn chi tit l So snh v hon i (CAS),s dng cp nht chia s d liu trong mt a x l. Mt mc chia s dliu b kho phn u ca vic thc hin so snh v hon i, so vini dung ca mt thanh ghi so snh, thit lp trng thi m c thch hp, vsau c cp nht bng cch di chuyn vo ni dung ca thanh ghicp nht. Sau , truy cp vo cc mc chia s d liu c c m kha,v vic thc hin so snh v hon ic hon tt. Vic thc hin cchng dn nh TAS v CAS trong mt h thng my tnh cung cp cc hthng vi kh nng ng b ha cho hot ng a x l [thut ton 89,

Hwan 93, Ston 93, Tabk 90A]. Hng dn ca loi ny thc s cthc hin trn nhiu b vi x l tin tin (xem Phn 2-4).

3,3 Cc nh dng d liu

Mt tp hp in hnh ca nh dng d liu s nguyn nh thc hnhtrong b vi x l hin i c th hin trong hnh. 3.5. l

1. Du v khng du

Byte 8 bitHalfword 16 bit

word 32 bit

Doubleword 34 bit


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2. K t ASC , mi kt 8 bit

3. Dng thc thp phn ng gi v dng thc thp phn mgi (BCD),mi s 4 bit.

Tuy nhin cn lu , trong mt s h thng, c bit l pht trin t snphm 16-bit (xem phn 2, 4), mt word l 16 bit v mt mc d liu 32-bitc gil mt doubleword hoc longword. Trong trng hp mc dliu 64-bit c gil mt quadword. Tuy nhin, xu hng gn y l sdng "word" mc d liu32-bit, nh minh ha trong hnh 3.5.. Thut ngthch hp s c s dng cng vi mi dng b vi x l c th trong phntip theo.

D liu 32-bit c 4 byte v chim 4 a chtrong b nh, c hai cch tcc a ch byte trong mt word:

1. Little-endian, LSB c a ch thp hn. Ni cch khc, cc byte c ach 3,2,1,0 t MSB xung.

2. Big-enaian, LSB c a ch cao hn. Ni cch khc, cc byte c a ch0, 1 2, 3, t MSB xung.


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B M TIU CHUN V TRAO I THNG TIN CA M (ASCII)k t mi 8 bit theo tiu chun. Bn k t c th c ghptrong mt t32-bit, nh trong hnh 3.5. Mt bng k t ASCII c a ra trong hnh3.5. Bng cc k t ASCII c a ra trong Ph lc 1.A

S thp nh phn c th c lu tr bng hai cch (xem hnh 3,5):

1. Gii nn, vi 4-bit s BCD chim cc 4 bit thp ca mi byte (Thngthng mi byte l mt a ch ring bit)

2. ng gi, hai s thp nh phn BCD trn byte. Tm s nh vy c thc ng gi vo mt t 32-bit.

Khi cn thit, mt bit du khc c t t mt chui cc s thp nh phnBCD. Trong mt s trng hp, 4 bit pha trn ca t ny (N7 trong hnh3.5) c th cha mt bit du, vi 3 bit khc khng s dng (thng l xa).

Cc nh dng d liu du chm ng th hin trong hnh 3.6. Cc n (32 bit) v chnh xc kp (64-bit) nh dng theo chun IEEE 754-1985[HaVZ 90, Hays 88, IEEE 81, IEEE 85]. 80 bit m rng chnh xc nhdng c th khc vi cc hng sn xut khc nhau. Mt th hin tronghnh 3,6 c thc hin bi Intel (Phn 2).

Cc bit du quan trng nht (s) biu din du ca cc s du chm ngton b: 0 ldng, 1l m . Gi nh cc k hiu sau y:

e thin v s m: cc numoe ~ actua]] y xut hin trong trng s m

E s m thc

Ne S bit trong s mtrng


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Cc s m thin v c nh ngha nh sau:

hoc biu thc s m thc, xt v s m thin v:

Eu tin: b = 2 (ne - 1) - 1. Ba loi chnh xc, th hin trong hnh 3.6, cc gitr u tin l

Tiu chun IEEE gi tr du chm ng l

s l gi tr bit du (0 l bit dng, 1 l bit m) v m lphn nh tr hoc hs bit nh phn:

Trng hp p l tng s bittrong phn nh tr. Ta c:

"1" trong Eq (3.3) l n v khng s dng trong phn nh tr. Mt khc,"1" khng s dng n 63 bittrong phn nh dng mrng (Fig.3.6); do


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p = 63 (khng phi 64 khiktthctheo ng tiu chun IEEE trong nhdng mrng).

Chuyn cc dy s thnh s thp phn, ta c:

cho c s m v dng

Chuyn sang s nh phn: 178,125 = 1.0110010001x (10) 111 (cs2). utin: 127 (thp phn) hoc 0111 1111 (nh phn). Cc s m l thin v:

T "1"l n v khng c nh dng, biu di n nh phn cui cng

ca 178,125 trong chnh xc n theo nh dng du chm ng:

Cc s khng ng u trong phn nh tr c th i din cho mtskhng c chun ha[Hays 88. HaVZ 90J. Tuy nhin, nh n "1",

khng lu tr nhng gi s l c (3.3). Cc con s c chun habng khiu ny l ln hn hoc bng 1 v nh hn 2.

T iu ny, l trng hp khc khi ni n "tiu chun IEEE". Tiu chunIEEE 754-1985 c gi nh [IEEE 85]

3,4 dngch dn


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nh dng ch dn khc nhau nhiu gia cc b vi x l khc nhau. Trongmt s h thngch dn c hnh thnh trong khi byte, trong mt strong khi16-bit halfwords (tuy nhin, trong mt s h thng chng cgil "words"), v trong h thng khc trong khi 32-bit. Thng tin cbn

bao gm trong mt nh dng ch dn ch yu l

1. Hng dn m php ton

2. a ch ca ton hng

Ty thuc vo h thng xem xt, cc chi tit khc c th gp li. C ththy r khitho lun v h thng c th, nh s c thc hin trong phn2 n 4.

M php ton bao gm 8 bit (1 byte), 256 m ha chc nng khc. Trongmt s h thng dng 2 byte, mc d byte th hai s khng c tn dng

ht cho m php ton (khng c h thng vi 216 m php ton). Thc t,thng ch c mt vi bit ca m php ton byte th hai s c s dngcho phn mrng m php ton (xem phn 2).

Mt s hng dn, chng hn nh "clear accumulator" hoc "return (tchng trnh con), khng cn ch nh bt k ton hng no, mt m phpton byte n c kh nng ch r ca chng. Nhiu hng dn cn phi xcnh ton hng. B vi x l hin i c th c n hai hoc ba ton hngtheo quy nh ca mt lnh. Trong h thng hai ton hng, mt trong cc

ton hng phc v nh mt ngun (src) v hai ton hng l mt ngun thhai v ch (dst), trong kt qu ca hot ng ny c lu gi. Trongh thng ba ton hng 2 ton hng to thnh hai ngun, src1 v src2, v th

ba l ch. Trng hp c bit, mt ngun c th ging vi ch. V d,xt mtlnh b sung trong mt h thng haiton hng:

Tng ng vi ni dung ca thanh ghi r1 x r2, kt qu lu vor1. Tng t nh vy, i vi mt h thng ba ton hng:

Mt v d khc:

Tng ng vi cc php tonsau trong mt h thng 2 ton hng:


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ADD r0, r1

Nh ch ra, vic s dng lnh ba ton hng tt hn mt m nn (hotng tng t c th c thc hin vi t lnh hn).

Cc ton hng c th l thanh ghi CPU, tng t v d trc, cc gi tr

c lu trong b nh, hoc cc gi tr ang dng. Khi s lng thanh ghiCPU l nh 8, 16, hoc 32, ch cn trng 3, 4, hoc 5 bit xc nhchng. C 2 v d v dng b vi x l RISC loi (m rng kh nng b xl kin trc (SPARC)], Chap 16 v Am29000 [Tabk 90b]), c s lngthanh ghi a ch trc tip CPU > 32. Ln nht l thanh ghi 192 voAm29000, m mt trng cn 8-bit.

a ch b nh c trng thi khc nhau. B vi x l hin i c mt a ch 32-bit (v mt s c nhiu hn), m rng 232 = 4 Gbyte a ch. Chngl byte a ch. Mt s h thng, nh Intel 80386 (xem phn 2), cung cp246 byte khng gian a ch o. S xut hin ca h thng mi 64-bit (DECAlpha, MIPS R4000, phn 4), khng tn thi gian nh a ch 64bit l ph

bin. Tuy nhin, hn ch vic tho lun 32 bit a ch, cn 32 bits chomt biu din trc tip ca mt a ch b nh trong mt lnh. Nh vymt ch a ch chc chn c s dng trong nhiu h thng; tuynhin, vic s dng c xu hng tng kch thc ca ch dn v chngtrnh. Gy ra vic s dng nhiu b nh hn lu tr cc chng trnh vtng chi ph ca h thng. Do , nhiu ch a ch b nh gin tipc m rng. c tho lun trong phn tip theo.

Nhiu nh dng ch dncho h thng 32-bit (hnh 3.7). Gi s h thng baton hng. Cc nh dng th hin thnh mt v d in hnh v khngtng thch chnh xc vi bt k nh dng ca cc h thng thc. Cc nhdng cho cc h thng c th s c trnh by trong phn 2-4.

nh dng thanh ghi (hnh 3.7 a) thit k ch yu chohot ngthanh ghin -thanh ghi. C hai ton hng hot ng v kt qu l ch trong cctpthanh ghi CPU.


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8 bit cho mitrngthanh ghiRS1, RS2, v rd.C kh nng ca a chlnn 256 thanh ghi (ln nht 192 trn Am29000, m t trong [Tabk90b]).Hu ht cc b vi x l nh hn thanh ghi a dng 32 CPU, cn 5 bitcho a chtrc tip. Ngoira 3 bit ca trng thanh ghi 8-bit c th cs dng cho mc ch khc, nh cc ch m ha a ch (3 bit mha 8 ch a ch). Nu ch c 16 thanh ghi, sau thanh ghi c thc chia u: 4 bit cho a chthanh ghi v 4 bit m ha ln n 16ch a ch.

Cc nh dng thanh ghi c s dng cho a ch b nhgin tip, c

tho lun trong phn tip theo. Cc nh dng thanh ghi - b nh(hnh 3.7b), thanh ghi- b nh, b nh-thanh ghi, v b nh-b nh. Trongthanh ghi- b nh hot ng chnh trong mt thanh ghi CPU v ch ltrong b nh: v d, mtlnh lu tr chuyn d liu t mtthanh ghiCPUvo mt v tr trong b nh. Trong lnh chuyn t b nh - thanh ghi,ngun l trong b nh v chthanh ghi CPU, nh trong mt lnhti. Trong hot ng b nhn b nhc hai ngun v ch n l trong

b nh.

V d

madr1 v amdr2 l a ch mang tnh biu tng trong b nh. c dliu trong cc vng ny l transterred ti P , v kt qu clu timadr2. c d liu madr1 khng i.

Trng a ch b nh(19 bit) (hnh 3.7 (6)) cha mttrngthanh ghi, mha mt ch a ch, v/hoc gi tr s c s dng trong tnh ton a


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ch ton hng trong b nh. Nu a ch trc tip s dng a ch 32-bitc thc hin, cn thm t m rng32-bit, cha a ch y v r rngtrong b nh. Bi v cc a ch tng thch, nh dng thanh ghi cng cth c s dng c ch dn lin quan n ton hng b nh.

Nhnh (hoc jump) v gi l nh dng, (hnh. 3.7 (c)), l lnh a ch

n. nh dng 32 - bit c th c s dng cho a ch gin tip hoc ach trc tip nh hn 24 bit (ln n 16 MB). Nu a ch trc tip 32-bitc s dng, c th m rng n 32-bit. i vi nhnh c iu kin hocchng trnh con gi mt trng iu kin m rng c thm vo. Huht cc tnh nng b vi x l hin i ln n iu kin 16 nhnh, cntrng iu kin ca 4 bit. ng nhin, mt t 32-bit m rng c thc thm vo ch dn nhnh c iu kin l tt.

C nhiu cn bng lin quan n vic a ch ton hng trong b nh. Nu

chng ta cho php a ch b nh ca ton hng trong hng dn iuhnh(chng hn nh cng, nhn), CPU truy cp b nh cho cc gi tr tonhng trong chu k thc hin. Mt khc, nu hot ng cathanhghinthanh ghi l cht ch, cc ton hng c nh du t cc tp tinthanh ghiCPU, truy cp nhanh hn nhiu so vi b nh. Ngay c khi ccton hng ang b nh cache on-chip, cn mt chu k b sung cungcp a ch hon chnh cho b nhtruy cp cache (tho lun trong chap6). Trong cc h thng lm vic vi mt hot ng cathanh ghi-thanhghi(h thngRISC, chng 6), truy cp b nh c thc hin ch bnghot ngti v lu tr. Tt nhin, nu thanh ghi- b nh hoc hot ng

ca b nh -thanh ghi c php, mt s hot ng ti hoc lu tr clu li, cho php nn m tt hn. Mt on m nn tt hn c th t cnu chng ta cho php b nh - b nh hot ng. Tuy nhin, c s thayi ln trong kch thc v thi gian hng dn thc hin. Hn na, truycp b nh theo kiu tht c chai c th pht trin. Do , b nh - b nhhot ng c khng c s dng trong h thng thi gian thc. Hu htcc h thng hin i (m ch yu l loi RISC, xem Phn 4) s dng hotng thanh ghi-thanh ghi v ti /lu tr truy cp b nh.

3.5 Gii quyt ch The addressing modes found in most modern microprocessors aredescribed in the foilowlng paragraphs.

Thanh ghi


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The operand is stored in one of the CPU registers. This mode is also calledregister direct. The assembly notation is Ri or ri. An example of a two-operand instruction using the register mode is

ADD

Ngay lp tc

The operand is a part of the instruction. In some systems, such as theM68000 family (Part 3), an immediate value is denoted by writing the " "sign in front of it. For example ,

ADD =50; 50.

The deciImal number 50 is added to the content ofthe CPU data registerDl. In most systems the numbers are considered to be decimal by default.

For other number representations an extra letter is added:

H for hexadecimal

B for binary

O for octal

For example, the following operations are equivalent:

ADD 255, rlADD FFH, rl

ADD l111 1111B, r1

ADD 3770, r1

Although widely used, the above notation is not univers al. For instance,the symbol "$ in front of the number is used in the M68000 family (seePart 3) for hexadecimal values . A symbolic notation, defined elsewhere inthe program. may be used instead of an explicit number in manyassemblers.

Direct (or absolute)

The address of the operand in memory is a part of the instruction. Usually asymbolic name is used, although explicit addresses can be given as well.Some examples:


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LOAD madr, r2; (madr) r2

CALL subr1

JMP AAFOH

Memory locations are specified by the symbolic names "madr" and "subrl"in the first two instructions, while an explicit hexadecimal address AAF0 isgiven in the third.

Register indirect (or indirect)

The address of the operand in memory is stored in one of the CPu registers.A possible assembly notation is

which means: move a data item whose address in memory is in the CPUregister r7 , into register r1. In this instruction the source operand isspecified by the register indirect, and the destination by the registeraddressing mode.

Register indirect with postincrement

Basically this mode works like the r egister indirect, except that the contentof the register is incremented after the use of the address in it by an integer

equal to the number of bytes of the operand. The notation is

(Ri) + or (ri) +

Move a 32-bit (4 byte) word from memory at the address, equal to thecontent of r1, to register r3. After the address in r1 is used to accessmemory, the content of r1 is incremented by 4, since the operand is 4 byteslong. The register indirect with postincrement mode permits automatic a

dvancing in loops, accessing byte, halfword, or word arrays of operands.Assume in the above example that rl is pointing to an element in an arrayof word-size (4 bytes) operands. After the execution of the aboveinstruction, rl will point to the next element in the array.

Register indirect with predecrement


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The content of the register is decremented by an integer equal to thenumber of bytes in the operand and is then used as an in direct address.The notation is

(Ri) or

V d

The content of register r6 is decremented by 2 (since the operand is a half;2 bytes), and then it is used as an address in memory, from which ahalfword operand is transferred to the reglster r11.

This mode can be used ta scan an array in the direction of decreasingindices. l. after dealing with element j of the array, element j will be

dealt with.

Register indirect with displacement

The effective address (EA) of the operand is the sum of the content of aCPU register and a value, called displacement, specified in the instruction.The notation is

d(Ri) or d ( ri ) , where d is the displacement

the displacement may be an immediate constant or a symbolic value,defined elsewhere in the program.

V d

The coment of a memory location, whose address IS the content of registerr2 plus 125, is added to the content of register r4. The sum will be in r4.

In this case the displacement is represented by a symbolic value DISP,which should be defined elsewhere in the program. The assembler will

place the appropriate specific value instead of DISP. The EA of the sourceoperand is obtained as in the preceding example.

In some systems this mode is denoted as the base mode and the registerinvolved is called the base register.


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Indexed and scaled indexed

The indexed mode works essentially as the indirect. Similarly to theindirect with displacement, there is also an indexed with displacementmode, defined in an identical way. The CPU register containing the addressin the indexed mode is called index register or simply index.

The main difference between the indirect and the indexed is that thecontent of the index register can be scaled by a factor of 1, 2, 4, 8, or 16,depending on the system. If the index is scaled. the mode is called scaledindexed. The scaling number is called the scale factor. Of course, when thescale factor is 1, there is no difference between the indirect and the indexedmodes. In the scaled indexed mode the content of the index register ismuitiplied by the scale factor co form the EA.

V d

The content of a memory location, whose address is four times the contentof r2 is moved to register r5. In this example, r2 is the index register, andthe scale factor is 4

The motivation for the indexed mode is the extra flexibility given to theuser when it is used in conjunction with the indirect mode, as exemplifieci

by the next two addressing modes. The availabiiity of the scale factor,along with the index, permits scanning of data structures of any size, at anydesired step.

Indirect scaled indexed:

The EA is the sum of the content of the indirect (or base) register and thescaled content of the index register. The notation is

..

where Ri or ri is the indirect (or base) register, Rj or rj is the indexregister,and SC is the scale factor.

In this example, r5 is the in direct register, r7 is lhe index register, and thescale factor is 2. The EA of the source operand in memory is the sum of thecontent of r5


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Indirect scaled indexed with displacement

This mode is essentially as the indirect scaled indexed, except that adisplacement is added to fonn the EA. The notation is similarly

d(Ri, Rj*SC) or d(ri, rj*SC)

where d is the displacement

V d

PC-relative

The PC-relative mode is similar to the register indirect with displacement.

The difference is that the program counter (PC) serves as the registerindirect (or the base register ). After an instruction is fetched, the PC isincremented to point to the next instruction (in systems with 32bit, or 4

byte uniform instruction size, the PC will be incremented by 4). This iswhat we call the updated PC, and it is the content of the updated PC that isused in the PC-relative mode. The PC-relative mode is used automaticallywith program control instrUctions in many systems.

Example Given a system wnere the PC-relative mode is used automatically with any branch (BR) instruction. Thus, only the displacement

must be given explicltly. It is assumed that all instructions are 4 bytes long.The instruction with its address is:

400 BR 400H: 4000 is tt-e hexadecimal : address of the instruction.

4004 next instruction

After the branch instruction is fetched, the updated PC value is 4004. Thehexadecimal displacement value 400H is added to the updated PC value toform the branch target address:

4004 + 400 = 4404

The addressing mode defined above are found in most modemmicroprocessors. Some variations of the above may exist, and in somesystems a different terminology may be used. The details of the addressingmodes, as implememed in actual systems, are presented in Parts 2 to 4.


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3.6 Concluding comment

Main architectural features of microprocessors, such as instructions sets,data formats, instruction formats, and addressing modes, were presented inthe preceding sections of this chapter. The presentation was general; thearchitectural features discussed were not associated with any specific

product, except in a few examples. Later on, in subsequent parts, whenarchitectural features of specific products are presented, the reader willrecognize the features presented in this chapter, or some features which arevery similar. This chapter was primarily intended for the benefit of readersnot sufficiently familiar with architectural features of microprocessors .

Architectural features , discussed in this chapter, are closely connectedwith the concepts of data storage in memory and its addressing. The nextchapter will discuss in detail the subject of memory orgamzation in

microprocessors, stressing the concept of memory hierarchy and itsdifferent levels, such as the register file, the cache, main memory, andsecondary memory. Naturally, readers familiar with the above aspects ofmemory organization may skip the next chapter.

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