C4, Ambiance Orion , Hadosiddapura, Sarjapur Road off, Bangalore - 560034 : (+91)9902930667

: ssbalamurugans@yahoo.co.in

Balamurugan SExperience : 8.5 YearsCurrently working for Infosys Technologies , Bangalore , Karnataka From March 2012

Client : Cisco

Designation : Technology Analyst

Worked for BEL Bangalore From Feb 2008 to Feb 2012

Designation : Deputy engineer

Skills

Skilled in High Speed Board design, Schematic, layout check, BOM creation Board Bring up, Validation and Testing.

Failure Analysis and Sustenance for products failed in the field.

FPGA design using Altera devices and tools, SOPC design using Nios II cpu

Validation of DDR3, PCIE, I2C Signals using High end Digital Oscilloscope

Validation of PSU for SOA, Static and Dynamic Load, Overload test in cycles.

Programming using VHDL, Verilog and C

Validation of System for EMI/EMC, Environmental, Surge, ESD certification.

Automation of board testing using Perl,TCL and Unix

Tools Worked

Concept HDL, DX Designer, Orcad, Quartus II, Qsys, Modelsim and Questasim, Eclipse,

40G DSO, Logic Analyzer, Spectrum Analyzer, Data Logger, I2C/SPI Analyzer

Chipsets Worked

Freescale’s P2020, T1042, Intel’s Atom C3000, Atmel’s AT89s52, Altera’s EP3C25F324,

EPAGX1152, Broadcom’s QAX88470,BCM59121, Vitesse’s VSC8251, TPS40XX, LT256X etc

Project#1: Development of ASR920- StrikerDeveloped For : CiscoTools Used: DX Designer, Concept HDL, Allegro , LT Spice

Roles and Responsibilities: Hardware Engineer Board bring-up, debugging and testing PSU Validation , SOA, Static and Dynamic load test, ON/OFF test with Multiple Voltage at

different intervals and slew rate Executed Design Validation test for DDR3, SGMII, PCIE and GigE interfaces. Failure Analysis and Sustenance for the customer returned systems DVT, EMI/EMC, ESD and Thermal validation

Project#2: Development of ASR920- CreteDeveloped For : Cisco

Roles and Responsibilities: Hardware Engineer Board bring-up, debugging and testing Executed Design Validation test for DDR3, SGMII, PCIE and GigE interfaces. DVT, EMI/EMC, ESD and Thermal validation.

Project #3: Development of IP Gateway Exchange (IPGX)Developed For : Bharat ElectronicsTools Used : Quartus II 10.1, NIOS II IDE, and Microsoft Visual C

Roles and Responsibilities: Design Engineer Board design of Main card with ARIAGX EPAGX90E11527I FPGA and various Interfaces

like GigE, Serial and E1/STM-1 Schematic creation. Guidance to PCB team, Board Bring up, RTL coding, Synthesis, Floor

planning. Timing Constraint development and I/O Signal assignment using assignment editor. System design of Exchange for giving interface to different type of subscribers like POTS,

TDM based ISDN Exchanges, VOIP Phones, Stars V radio, GSM, CDMA phones.

Project #4: Development of Tactical RouterDeveloped For : Bharat ElectronicsTools Used : Quartus II 10.1, NIOS II IDE, and Microsoft Visual C

Roles and Responsibilities: Design Engineer Architecture design and finalization which involves memory allocation for packet

processing, switching table, routing table and Mac table. Processing speed, Interface design for backplane communication, Ethernet Packet handling

(Control and data). Implementation of ICMP, ARP, IP, UDP, IGMP and Multi-cast Protocol using VHDL and C.

EDUCATION

2007Bachelor of Engineering in Electronics and CommunicationAnna University, Chennai, IndiaAggregate: 74.47%

2003Higher Secondary Examination (XII)SGHSS, PNK, TamilNaduAggregate: 81.75%

2001Secondary School Examination (X)KAHSS, TamilnaduAggregate: 83.4%

Personal Details

Father’s Name : S.Selvaraj

D.O.B : 25-Aug-1986

Passport No. : G2895631

Declaration

I do hereby declare that the information stated above is true to the best of my knowledge.

BALAMURUGAN S