Bach SOM Reference Manual

Bach SOM

Reference Manual

Date: November 13, 2015

Revision: 1.1

Disclaimers and Restrictions

© 2015 COVELOZ®

Revision History

Version Date Author Description

1.0 September 2015

Jane Biggs Initial Release.

1.1 November 2015

Nathan Phillips

Added TDM interface and board ID details.

Draft: June 2015 Page 4 of 30

Table of Contents

Chapter 1: Overview ......................................................................................................... 8

1.1 General Description .............................................................................................................. 8

1.2 Features ..................................................................................................................................... 8

1.3 Component Blocks ............................................................................................................... 8

1.4 Block Diagram ........................................................................................................................ 9

1.5 Handling the SOM Board ................................................................................................ 10

Chapter 2: SOM Board Components ............................................................................ 10

2.1 SOM Board Overview ........................................................................................................ 10

2.2 Edge Connector ................................................................................................................... 12

2.3 Cyclone V SoC ..................................................................................................................... 15

2.3.1 I/O Resources ............................................................................................................. 16

2.3.2 FPGA Bank Voltages ................................................................................................ 16

2.3.3 FPGA Clock Inputs and Outputs ......................................................................... 17

2.4 FPGA Configuration ........................................................................................................... 17

2.4.1 FPGA Programming over External USB-Blaster .......................................... 17

2.4.2 HPS Boot from MicroSD FLASH ......................................................................... 18

2.4.3 HPS Boot from QSPI FLASH ................................................................................ 18

2.5 Test Points ............................................................................................................................. 19

2.6 Setup Elements ................................................................................................................... 19

2.6.1 FPGA Configuration Mode ..................................................................................... 19

2.6.2 HPS Configuration Mode ....................................................................................... 20

2.6.3 Resets on the Edge Connector ............................................................................ 21

2.7 Clock Circuitry ..................................................................................................................... 21

2.8 HPS Interfaces ..................................................................................................................... 22

2.8.1 RGMII ............................................................................................................................. 22

2.8.2 I2C Interfaces ............................................................................................................. 22

2.8.3 SPI interface ................................................................................................................ 23

2.8.4 UART .............................................................................................................................. 23

2.8.5 CAN ................................................................................................................................. 23

2.8.6 USB 2.0 ......................................................................................................................... 24

2.9 FPGA Interfaces ................................................................................................................... 24


2.9.1 RGMII ............................................................................................................................. 24

2.9.2 AUDIO GPIO ................................................................................................................ 24

2.9.3 Timing ............................................................................................................................ 27

2.10 Memory ................................................................................................................................ 28

2.10.1 DDR3 SDRAM .......................................................................................................... 28

2.10.2 EPCQ FLASH ............................................................................................................ 28

2.10.3 QSPI FLASH .............................................................................................................. 28

2.11 Power .................................................................................................................................... 29

2.11.1 Input Power .............................................................................................................. 29

2.11.2 Power Rails and Current ..................................................................................... 29

2.11.3 FPGA Bank Voltages ............................................................................................. 29

Chapter 3: Additional Information ............................................................................... 30

3.1 Board Revision History .................................................................................................... 30

3.2 How to Contact Coveloz ................................................................................................... 30


Index of Figures

Figure 1-1: Bach SOM Board Block Diagram .............................................................................. 9

Figure 2-1: Bach SOM Board Features ........................................................................................ 11

Figure 2-2: SOM Board Edge Connector Block Diagram ..................................................... 13

Figure 2-3: JTAG Chain ....................................................................................................................... 18

Figure 2-4: I32S TDM Signaling ...................................................................................................... 25

Figure 2-5: TDM 32-bit Channel Block Transmit .................................................................... 25


Index of Tables

Table 2-1: Bach SOM Board Components ................................................................................. 11

Table 2-2: Board-Specific Edge Connector ................................................................................ 13

Table 2-3: Edge Connector Pinout ................................................................................................. 13

Table 2-4: SOM Board Features of the Low-Cost Variant .................................................... 15

Table 2-5: SOM Board Features of the High-Performance Variant ................................. 15

Table 2-6: Cyclone V SoC I/O Pin Count ..................................................................................... 16

Table 2-7: FPGA Bank Voltages ...................................................................................................... 16

Table 2-8: FPGA Clock Inputs and Outputs ............................................................................... 17

Table 2-9: Board-Specific Test Points .......................................................................................... 19

Table 2-10: FPGA Configuration Mode Resistors .................................................................... 20

Table 2-11: HPS Configuration Mode Resistors ...................................................................... 20

Table 2-12: Board Specific Clock Circuitry ................................................................................ 22

Table 2-13: Board ID I2C Slave Registers .................................................................................. 23

Table 2-14: Board Specific DDR3 SDRAM ................................................................................. 28

Table 2-15: Board Specific QSPI Flash ........................................................................................ 28

Table 2-16: Board Specific Power ................................................................................................. 29

Table 2-17: Power Consumption .................................................................................................... 29

Table 2-18: I/O Power Rails .............................................................................................................. 30

SOM Reference Manual Chapter 1: Overview


Chapter 1: Overview

This document describes the hardware features of the Bach SOM board, including the detailed pin-out and component reference information required to design custom AVB and AES67 endpoints.

1.1 General Description

The Bach SOM Board provides a low cost, scalable, high performance platform for implementing an AVB or AES67 endpoint. The Bach SOM Board is referred to in this document as the SOM Board.

The SOM Board can be used to prototype solutions as well as deploy solutions in volume. It can be integrated with the Bach Pro-Audio Development Board.

1.2 Features

The features of the Bach SOM Board are:

• Flexible IO Mapping

• 48 programmable GPIO for audio interfaces including o TDM (default)

o A 256+256 channel TDM interface is standard on the Bach-SOM o MADI o I2S o AES3 (AES/EBU)

• Dedicated pins to and from FPGA PLLs

• 3 RGMII Interfaces o 1 connected to the HPS o 2 connected to the FPGA fabric

• 2.5V Differential IO Pairs for MADI TX/RX

• Clock reference inputs including: o Word Clock In/Out o PPS In/Out o Grandmaster Input

1.3 Component Blocks

The SOM Board features the following major component blocks:

• One Cyclone V SoC (5CSEA5U23C8) in a 623-pin UBGA package:

SOM Reference Manual Chapter 1: Overview


o FPGA JTAG interface o QSPI FLASH connected to HPS

• Clocking circuitry: o 25-MHz for HPS o 50-MHz to FPGA fabric

• Memory: o Two 256Mbyte (MB) HPS DDR3 SDRAM at 16-bits each, total

bandwidth in excess of 20Gbps o One 1-Gigabit (Gb) Quad Serial Peripheral Interface (QSPI) FLASH

• 144-pin Edge connector compatible with standard SODIMM connectors

• Dimensions: o 65x67.5mm

1.4 Block Diagram

Figure 1-1 shows a block diagram of the SOM Board.

Figure 1-1: Bach SOM Board Block Diagram

SOM Reference Manual Chapter 2: SOM Board Components


1.5 Handling the SOM Board

Without proper anti-static handling, the SOM Board can be damaged. Always use anti-static handling precautions when touching the SOM Board.

Chapter 2: SOM Board Components

This chapter introduces the major components on the Bach SOM Board.

A complete set of schematics, a physical layout database and fabrication files for the development board are available upon request.

Refer to the Bach Development Kit User Guide for more information about powering up and configuring the Development Board.

2.1 SOM Board Overview

This section provides an overview of the SOM Board including an annotated board image and component descriptions. Figure 2-1 shows an overview of the board features.

The SOM Board comes in two variants to meet both high performance and low cost solutions. The high-performance variant has two DDR modules and a large FPGA with dual ARM A9 cores. The low-cost variant has a smaller FPGA a single DDR module and a single ARM A9 core.

Figure 2-1shows the SOM Board features.



Figure 2-1: Bach SOM Board Features

Table 2-1 describes the components and lists their corresponding SOM board references.

Table 2-1: Bach SOM Board Components

Board Reference

Type Part Number Description

Featured Devices

U7 SoC 5CSEBA5U23C8 Cyclone V SoC in a 623-pin UBGA package

Setup Elements J1 JTAG TPS51200 FPGA interface U6 QSPI Flash N25Q00AA13GSF40G HPS interface Clock Circuitry X2 50 MHz ECS-3963-500-B-TR Connected to FPGA X1 25 MHz ECS-3963-250-BN-TR Connected to HPS General User Input / Output

J2 EDGE connector

N/A 144-pin Edge connector compatible with standards SODIMM connector



Board Reference

Type Part Number Description

Memory Devices

U6 QSPI flash N25Q00AA13GSF40G One 1-Gigabit (Gb) quad serial peripheral interface (QSPI) flash

U2, U3 DDR3 memory MT41J256M16HA-125 Two 256Mbyte (MB) HPS DDR3 SDRAM at 16-bits each, total of 32-bits

Power

U8 DC/DC convertor

IC-LXDC55FAAA 1.1V from 5V input

U9 DC/DC convertor


U1 DC/DC convertor


U4 Voltage Regulator

IC-MIC39102-SO8 2.5V from 3.3 rail

2.2 Edge Connector

The Edge Connector has 144 pins and provides interfaces to the following:

• HPS ARM communications o RGMII o I2C interface x2 o SPI interface o UART o CAN o USB 2.0

• FPGA communications o RGMII x2 o GPIO (up to 48)

• FPGA timing o Grandmaster input o PPS input and output o Word clock input and output o Audio master clock input

• FPGA audio o TDM x16 (up to 256ch) o I2S x48 (up to 96 ch) o MADI x2 (up to 128 ch) o AES/EBU x48 (up to 96 ch)

• SOM power o Single 5-6V supply to SOM

Table 2-2 lists the SOM Board specific Edge connector references, names and their functional descriptions.



Table 2-2: Board-Specific Edge Connector

Board Reference

Schematic Name I/O Standard

Description

J2 JTAG 5V JTAG Edge connector interface

Figure 2-2 illustrates the SOM Board and the Edge connector interfaces.

Figure 2-2: SOM Board Edge Connector Block Diagram

Table 2-3 lists the Edge connector pinouts.

Table 2-3: Edge Connector Pinout

Pin Name Direction Voltage Pin Pin2 Voltage Direction Pin Name2 5V Input 5 1 2 5 Input 5V 5V Input 5 3 4 5 Input 5V 5V Input 5 5 6 5 Input 5V SYS_RESETn Input 3.3 7 8 3.3 Output HPS_FLASH_CS AUD_BCLK Bidir 3.3 9 10 3.3 Output HPS_I2C1_SCL HPS_I2C1_SDA Bidir 3.3 11 12 3.3 Bidir HPS_SPI_MISO HPS_UART_RX Input 3.3 13 14 3.3 Output HPS_UART_TX HPS_I2C_SDA Bidir 3.3 15 16 3.3 Output HPS_I2C_SCL HPS_CAN_RX Input 3.3 17 18 3.3 Output HPS_CAN_TX GND Ground 3.3 19 20 3.3 Output HPS_SD_CLK HPS_SD_CMD Output 3.3 21 22 3.3 Bidir HPS_SD_D0 HPS_SD_D1 Bidir 3.3 23 24 3.3 Bidir HPS_SD_D2 HPS_SD_D3 Bidir 3.3 25 26 3.3 Ground GND



Pin Name Direction Voltage Pin Pin2 Voltage Direction Pin Name2 HPS_ENET_RESETn Output 3.3 27 28 3.3 Input HPS_ENET_INTN HPS_ENET_TXD0 Output 3.3 29 30 3.3 Output HPS_ENET_TXD1 HPS_ENET_TXD2 Output 3.3 31 32 3.3 Output HPS_ENET_TXD3 HPS_ENET_TX_EN Output 3.3 33 34 3.3 Output HPS_ENET_GTX_CLK HPS_ENET_RXD0 Input 3.3 35 36 3.3 Input HPS_ENET_RXD1 HPS_ENET_RXD2 Input 3.3 37 38 3.3 Input HPS_ENET_RXD3 HPS_ENET_RX_DV Input 3.3 39 40 3.3 Input HPS_ENET_RX_CLK HPS_ENET_MDIO Bidir 3.3 41 42 3.3 Output HPS_ENET_MDC GND Ground 3.3 43 44 3.3 Bidir HPS_USB_D0 HPS_USB_D1 Bidir 3.3 45 46 3.3 Bidir HPS_USB_D2 HPS_USB_D3 Bidir 3.3 47 48 3.3 Bidir HPS_USB_D4 HPS_USB_D5 Bidir 3.3 49 50 3.3 Bidir HPS_USB_D6 HPS_USB_D7 Bidir 3.3 51 52 3.3 Input HPS_USB_CLK HPS_USB_STP Output 3.3 53 54 3.3 Input HPS_USB_DIR HPS_USB_NXT Input 3.3 55 56 3.3 Ground GND GND Ground 3.3 57 58 3.3 Output FPGA_ENET0_RESETN FPGA_ENET0_INTn Input 3.3 59 60 3.3 Output FPGA_ENET0_TXD0 FPGA_ENET0_TXD1 Output 3.3 61 62 3.3 Output FPGA_ENET0_TXD2 FPGA_ENET0_TXD3 Output 3.3 63 64 3.3 Output FPGA_ENET0_TX_EN FPGA_ENET0_GTX_CLK Output 3.3 65 66 3.3 Input FPGA_ENET0_RXD0 FPGA_ENET0_RXD1 Input 3.3 67 68 3.3 Input FPGA_ENET0_RXD2 FPGA_ENET0_RXD3 Input 3.3 69 70 3.3 Input FPGA_ENET0_RX_DV FPGA_ENET0_RX_CLK Input 3.3 71 72 3.3 Bidir FPGA_ENET0_MDIO FPGA_ENET0_MDC Output 3.3 73 74 3.3 Ground GND FPGA_ENET1_RESETN Output 3.3 75 76 3.3 Input FPGA_ENET1_INTN FPGA_ENET1_TXD0 Output 3.3 77 78 3.3 Output FPGA_ENET1_TXD1 FPGA_ENET1_TXD3 Output 3.3 79 80 3.3 Output FPGA_ENET1_TXD3 FPGA_ENET1_TX_EN Output 3.3 81 82 3.3 Output FPGA_ENET1_GTX_CLK FPGA_ENET1_RXD0 Input 3.3 83 84 3.3 Input FPGA_ENET1_RXD1 FPGA_ENET1_RXD2 Input 3.3 85 86 3.3 Input FPGA_ENET1_RXD3 FPGA_ENET1_RX_DV Input 3.3 87 88 3.3 Input FPGA_ENET1_RX_CLK FPGA_ENET1_MDIO Bidir 3.3 89 90 3.3 Output FPGA_ENET1_MDC GND Ground 3.3 91 92 3.3 Input AUDIO_WCLK_IN AUDIO_WCLK_OUT Output 3.3 93 94 3.3 Bidir FPGA_SPARE I2S_LRCK Bidir 3.3 95 96 3.3 Bidir I2S_SCLK TDM_SCLK Bidir 3.3 97 98 3.3 Bidir TDM_FSYNC GND Ground 3.3 99 100 3.3 Input TDM_I2S_IN0 TDM_I2S_IN1 Input 3.3 101 102 3.3 Input TDM_I2S_IN2 TDM_I2S_IN3 Input 3.3 103 104 3.3 Input TDM_I2S_IN4 TDM_I2S_IN5 Input 3.3 105 106 3.3 Input TDM_I2S_IN6 TDM_I2S_IN7 Input 3.3 107 108 3.3 Ground GND TDM_I2S_OUT0 Output 3.3 109 110 3.3 Output TDM_I2S_OUT1 TDM_I2S_OUT2 Output 3.3 111 112 3.3 Output TDM_I2S_OUT3 TDM_I2S_OUT4 Output 3.3 113 114 3.3 Output TDM_I2S_OUT5 TDM_I2S_OUT6 Output 3.3 115 116 3.3 Output TDM_I2S_OUT7 AES3_RSTN Output 3.3 117 118 3.3 Input AES3_IN_SCLK AES3_OUT_SCLK Output 3.3 119 120 3.3 Input AES3_IN_SD AES3_OUT_LRCK Output 3.3 121 122 3.3 Input AES3_IN_LRCK AES3_OUT_MCLK Output 3.3 123 124 3.3 Input AES3_OUT_INT AES_IN_MCLK Output 3.3 125 126 3.3 Input AES3_IN_RMCK GND Ground 3.3 127 128 3.3 Output AES3_OUT_SD CS2000_CLK_OUT Input 3.3 129 130 3.3 Output CS2000_CLK_IN MADI_TX_P Output 2.5 131 132 3.3 Input CS2000_AUX_OUT MADI_TX_N Output 2.5 133 134 2.5 Input MADI_RX_P AUD_XCK Output 3.3 135 136 2.5 Input MADI_RX_N AUD_ADCLRCK Bidir 3.3 137 138 3.3 Bidir AUD_DACLRCK AUD_DACDAT Output 3.3 139 140 3.3 Input AUD_ADCDAT GRAND_MASTER_IN Input 3.3 141 142 3.3 Input PPS_IN PPT_OUT Output 3.3 143 144 3.3 Ground GND



2.3 Cyclone V SoC

The SOM Board features a Cyclone V SE device in a 623-pin UBGA (U23) package that includes a hard processor system (HPS) with integrated ARM® Cortex™-A9 MPCore processor.

The SOM Board is available in two different FPGA population options:

A low-cost variant:

• 5CSEBA2U23C8SN

A high-performance variant:

• 5CSEBA5U23C8N

Table 2-4 describes the features of the low-cost variant of the Cyclone V SoC device.

Table 2-4: SOM Board Features of the Low-Cost Variant

Resource 5CSEBA2U23C8SN LE (K) 25 ALM 9,434 Register 37,736

Memory (Kb) M10K 1400 MLAB 138

18-bit x 18-bit Multiplier 72

PLLs FPGA 5 HPS 3

Table 2-5 describes the features of the low-cost variant of the Cyclone V SoC device.

Table 2-5: SOM Board Features of the High-Performance Variant

Resource 5CSEBA5U23C8N LE (K) 85 ALM 32.075 Register 128,300

Memory (Kb) M10K 3,970 MLAB 480

18-bit x 18-bit Multiplier 174

PLLs FPGA 6 HPS 3



2.3.1 I/O Resources

The Cyclone V SoC device has 145 general purpose FPGA I/O pins and 181 HPS I/O pins.

Table 2-6 lists the Cyclone V SoC I/O pin count and usage by function on the board.

Table 2-6: Cyclone V SoC I/O Pin Count

Function I/O Standard I/O Count HPS clock inputs 3.3-V LVCMOS 2 HPS resets 3.3-V LVCMOS 2 HPS UART 3.3-V LVCMOS 2 HPS I2C bus 3.3-V LVCMOS 4 HPS SPI bus 3.3-V LVCMOS 4 HPS QSPI flash 3.3-V LVCMOS 6 HPS SD card 3.3-V LVCMOS 6 HPS USB OTG 3.3-V LVCMOS 12 HPS Gigabit Ethernet 3.3-V LVCMOS 16 HPS CAN bus 3.3-V LVCMOS 2 HPS DDR3 1.5-V SSTL 71 FPGA Oscillator Inputs Mixed 5 FPGA Dual Gigabit Ethernet 3.3-V LVCMOS 32 FPGA Differential IO 2.5V LVDS 4 FPGA Clock Synchronization 3.3-V LVCMOS 5 FPGA Audio Interfaces 3.3-V LVCMOS 38 Total I/O Used: 211

2.3.2 FPGA Bank Voltages

Table 2-7lists the FPGA bank voltages I/O count.

Table 2-7: FPGA Bank Voltages

Bank I/O Voltage I/O Count 3A 2.5-V 16 3B 3.3-V 32 4A 3.3-V 68 5A 3.3-V 16 5B 3.3-V 0 6A 1.5-V 56 6B 1.5-V 44 7A 3.3-V 19 7B 3.3-V 22 7C 3.3-V 12 7D 3.3-V 14 8A 3.3-V 13



2.3.3 FPGA Clock Inputs and Outputs

Table 2-8 lists the FGPA clock functions and their inputs/outputs.

Table 2-8: FPGA Clock Inputs and Outputs

Function Pro-Audio Development Board CLK0n,FPLL_BL_FBn No connection CLK0p,FPLL_BL_FBp ENET0_RX_CLK FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn ENET1_GTX_CLK FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB ENET0_GTX_CLK CLK1n No connection CLK1p ENET1_RX_CLK CLK2n No connection CLK2p 50MHz Oscillator CLK3n CS2000_AUX_OUT CLK3p CS2000_CLK_OUT CLK7p 50MHz Oscillator CLK7n No connection FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB CS2000_CLK_IN FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn No connection CLK6p,FPLL_TL_FBp No connection CLK6n,FPLL_TL_FBn No connection

2.4 FPGA Configuration

This section describes the FPGA and flash memory, programming methods supported by the Pro-Audio Development Board.

The Pro-Audio Development Board supports the following configuration methods:

• External USB-Blaster for configuring the FPGA when you connect the external USB-Blaster to the JTAG header (J23).

• Flash memory download by the HPS for configuring the FPGA using stored images in the QSPI FLASH.

• Flash memory download by the HPS for configuring the FPGA using stored images in microSD card.

2.4.1 FPGA Programming over External USB-Blaster

The JTAG chain header provides a method for configuring the FPGA using an external USB-Blaster device with the Quartus II Programmer running on a PC.

Figure 2-3 illustrates the JTAG chain.



Figure 2-3: JTAG Chain

2.4.2 HPS Boot from MicroSD FLASH

When plugged into the Development Board the HPS BOOSEL configuration specifies booting from microSD FLASH. The HPS follows the steps below:

1. CPU resets and it points to the preloader, which is located on the external SD card

2. Preloader runs, finishes and it jumps to the u-boot (bootloader). 3. Uboot loads the FPGA bitstream from the SD card into main memory, and

configures the FPGA. 4. After configuring the FPGA, Linux kernel is loaded. 5. Linux kernel brings up other applications, and brings up all the necessary

devices for the system to work 6. After everything is done, a login prompt is available to the user to interact

with the kit using a command line interface.

2.4.3 HPS Boot from QSPI FLASH

By default the BOOTSEL configuration on the SOM selects booting from QSPI FLASH. The HPS follows the boot steps below:

1. CPU resets and it points to the preloader, which is located on the QSPI FLASH

2. Preloader runs, finishes and it jumps to the u-boot (bootloader).



3. Uboot loads the FPGA bitstream from the QSPI FLASH into main memory, and configures the FPGA.

4. After configuring the FPGA, Linux kernel is loaded. 5. Linux kernel brings up other applications, and brings up all the necessary

devices for the system to work 6. After everything is done, a login prompt is available to the user to interact

with the kit using a command line interface.

2.5 Test Points

Table 2-9 lists the SOM Board specific test point references, names and their functional descriptions.

Table 2-9: Board-Specific Test Points

Board Reference


Description

TP1 Test Point 1 1.5V Power TP2 Test Point 2 2.5V Power TP3 Test Point 3 3.3-V FPGA TP4 Test Point 4 3.3-V FPGA TP5 Test Point 5 3.3-V FPGA TP6 Test Point 6 1.1V Power TP7 Test Point 7 1.1V Power TP8 Test Point 8 5V Power

2.6 Setup Elements

The development board includes resistor population options for configuring the FPGA and HPS boot modes:

• FPGA MSEL Configuration

• HPS BOOT_SEL Configuration

2.6.1 FPGA Configuration Mode

The FPGA configuration mode resistors define the mode to use to configure the FPGA. The default MSEL resistor populations configure the FPGA for configuration via the HPS.

Table 2-10 lists the FPGA configuration mode resistor settings names and their functional descriptions.



Table 2-10: FPGA Configuration Mode Resistors

Resistor Schematic Signal Name

Description

R51, R77 MSEL0 R51 DNP, R77 1k = Pull-up R51 1k, R77 DNP = Pull-down





2.6.2 HPS Configuration Mode

The HPS resistor options define the bootstrap options for the HPS—boot source, mode and peripherals selection.

Table 2-11 lists the HPS configuration mode resistor settings names and their functional descriptions.

Table 2-11: HPS Configuration Mode Resistors

Schematic Signal Name

Description

HPS_SPI_SS Selects the boot mode and source for the HPS: − Bootsel0



Schematic Signal Name

Description

HPS_BOOSEL[2:0]

Selects the boot mode and source for the HPS: − 0x0—Reserved − 0x1—FPGA (HPS-to-FPGA bridge) − 0x2—1.8 V NAND flash − 0x3—3.0 V NAND flash − 0x4—1.8 V SD/MMC flash memory with external − transceiver − 0x5—3.0 V SD/MMC flash memory with internal

transceiver − 0x6—1.8 V SPI or quad SPI flash memory − 0x7—3.0 V SPI or quad SPI flash memory

Schematic names: BOOTSEL0 = HPS_SPI_SS

− R38 Pulldown, default DNP − R36 Pullup, default 10k

BOOTSEL1 = HPS_FLASH_CS − R21 Pullup, default 10k

BOOTSEL2 = HPS_BOOTSEL2 − R41 Pulldown, default DNP − R71 Pullup, default 10k

By default BOOTSEL[2:0] = 0x7 on HPS bootup. This sets the boot scheme to 3.0V QSPI FLASH. When the SOM is inserted into the Pro-Audio development kit, the HPS_FLASH_CS (BOOTSEL1) is pulled to GND for a configuration of BOOTSEL [2:0] = 0x5. This sets the boot scheme to microSD card FLASH memory.

HPS_CLKSEL[1:0]

Schematic names: CLKSEL0 = HPS_CAN_TX

− R39 Pulldown, default 1k − R43 Pullup, default DNP

CLKSEL1 = HPS_UART_TX − R40 Pulldown, default 1k − R37 Pullup, default DNP

By default CLKSEL[1:0] is set to 0x0 on HPS bootup. This sets the clock scheme to 25MHz oscillator.

2.6.3 Resets on the Edge Connector

The SOM 144-pin Edge Connector has a SYS_RESETn input on pin 7. When toggled low, this reset initiates a full FPGA and HPS reconfiguration and re-boot. This reset should be connected to the host board power on reset generator (POR).

2.7 Clock Circuitry

This section describes the SOM Board’s clock inputs and outputs.

Table 2-12 lists the SOM Board specific clock circuitry references, names and their functional descriptions.



Table 2-12: Board Specific Clock Circuitry

Board Reference


Description

X1 25 MHz 3.3V Clock circuitry to HPS core X2 50 MHz 3.3V Clock circuitry to FPGA interface

2.8 HPS Interfaces

This section describes the HPS ARM interfaces which are available on the SOM 144-pin edge connector:

• RGMII

• I2C interface

• SPI interface

• UART

• CAN

• USB 2.0

2.8.1 RGMII

The HPS has a dedicated RGMII Gigabit Ethernet interface connected directly to the ARM cores. This interface is used for Host access for debug or control.

The interface supports any RGMII compatible PHY to provide 10/100/1000Mbps Ethernet access to the HPS.

2.8.2 I2C Interfaces

The HPS has two independent I2C interfaces, one is a master and one is a slave. Each I2C bus consists of two signals, using LVTTL 3.3V levels:

• HPS_I2C_SCL – Slave clock intput • HPS_I2C_SDA – Slave bidirectional data • HPS_I2C1_SCL – Master clock output • HPS_I2C1_SDA – Master bidirectional data

2.8.2.1 Board ID I2C Slave

The HPS_I2C interface is an I2C slave which allows a board host device to read IDs from the Bach-SOM including firmware and hardware version IDs.



The interface operates in I2C fast mode, at 400kHz. It does not have on-board pull-ups, so the host hardware must include pull-up resistors to 3.3V on both the SCL and SDA lines.

The interface uses 7-bit addressing and the interface address is 0x55.

The address map for the slave interface is:

Table 2-13: Board ID I2C Slave Registers

Address Name Access Description 0x01 BoardID Read-Only The 8-bit Board ID Value 0x02 FirmwareVersionMajor Read-Only The firmware version: MM.mm.nn 0x03 FirmwareVersionMinor Read-Only The firmware version: MM.mm.nn 0x04 FirmwareVersionNano Read-Only The firmware version: MM.mm.nn

2.8.2.2 Peripheral Control I2C Master

The HPS_I2C1 is an I2C master controlled by the HPS and can be used to control I2C peripherals. When used with the Bach Development Kit, this interface configures the SSM2603 audio codec.

2.8.3 SPI interface

There is a SPI interface connected to the HPS that shares pins with the HPS_I2C1 bus. If the SPI interface is used, then HPS_I2C1 is not available:

• HPS_SPI_MISO – master data in, slave data out • HPS_I2C1_SDA/SPI_CLK – clock out • HPS_I2C1_SCL/SPI_MOSI - master data out, slave data in

2.8.4 UART

The HPS has a dedicated UART port which is normally used as a debug console interface to the embedded linux OS running on the ARM cores:

• HPS_UART_TX • HPS_UART_RX

2.8.5 CAN

The HPS has a dedicated CAN bus interface available:



• HPS_CAN_TX • HPS_CAN_RX

2.8.6 USB 2.0

A UST2.0 OTG (on-the-go) controller is supported by the HPS. It has the following standard signals to interface with an external USB transceiver:

• HPS_USB_D[7:0] • HPS_USB_STP • HPS_USB_NXT • HPS_USB_DIR • HPS_USB_CLK

2.9 FPGA Interfaces

This section describes the FPGA interfaces:

• 2x RGMII

• Audio GPIO

• Timing

• LVDS

2.9.1 RGMII

The FPGA has a two RGMII Gigabit Ethernet interfaces connected directly to the FPGA fabric. These interfaces are intended for audio/video streaming. The dual interface also allows redundancy.

The interface supports any RGMII compatible PHY to provide 10/100/1000Mbps Ethernet access to the HPS.

2.9.2 AUDIO GPIO

The Bach SOM has 48 GPIO signals connected to the FPGA. These GPIOs are customizable to provide flexible audio interfaces capable of carrying up to 512+512 channels of audio. The standard GPIO configuration for the Bach SOM supports the Bach Pro-Audio Development board which includes the following audio interfaces:

• TDM using I32S for a total of 256+256 channels



• ADC and DAC audio codec with I2S • MADI differential RX and TX pairs • AES3/EBU input and output using external AES encoder and decoder ICs

The sections that follow explain the default configuration of the audio interfaces for the standard Bach SOM.

2.9.2.1 Audio I32S TDM Interface

The default Bach-SOM firmware supports a TDM audio interface of 256+256 channels with 32-bit samples at 48kHz sampling rate.

It uses 8 lines of I32S output and 8 lines of I32S input for a total of 8x32=256 channels both in and out of the device.

Figure 2-4: I32S TDM Signaling

The interface uses 32-bit sample blocks to carry up to 24-bit audio samples. The MSB audio bit is transported first and any unused LSB bits are padded with zero. The figure below shows a 24-bit audio sample with 8-bits of padding.

Figure 2-5: TDM 32-bit Channel Block Transmit

The TDM output interface is a clock master and the input is a clock slave, though the output clock can be used to drive the input if needed.

The sampling clock is 49.152MHz (48kHz x 32-bits x 32-channels). Data is sent from the FPGA on the falling edge of SCLK and should be sampled by the receive



device on the rising edge. Incoming data is sampled on the rising edge of SCLK. The sampling edges are configurable.

The TDM pins are outlined in Table 2-3: Edge Connector Pinout.

The TDM output signals include:

• TDM_SCLK – Output clock of 49.152MHz • TDM_FSYNC – Output Frame Synchronization pulse • TDM_I2S_OUT[7:0] – Output TDM signals using I32S mapping

The TDM input signals include:

• I2S_SCLK – Input clock of 49.152MHz • I2S_LRCK – Input Frame Synchronization pulse • TDM_I2S_IN[7:0] – Input TDM signals using I32S mapping

2.9.2.2 MADI LVDS

Two pairs of pins on the SOM connector can be used as differential transmit and receive interfaces, such as LVDS. This allows them to drive and terminate a MADI interface directly in the FPGA.

The MADI differential IO signals are:

• MADI_TX_N/P – LVDS differential pair for MADI audio output • MADI_RX_N/P - LVDS differential pair for MADI audio input

2.9.2.3 External AES3 Interface

The Bach SOM connector has a group of signals called AES3_* currently assigned to control Cirrus Logic AES3 transmit and receive ICs on the Bach Dev Kit.

The interface to the IC consists of I2S in and out along with clocks and synchronization signals.

These signals can be customized to meet specific audio interface requirements or connected to a similar IC on a customer board.

2.9.2.4 Audio Codec Interface

The Bach SOM connector has a group of signals called AUD_* currently assigned to control an SSM2303 audio codec (ADC and DAC) on the Bach Dev Kit.



The interface to the IC consists of I2S in and out along with clocks and synchronization signals.


2.9.3 Timing

The FPGA supports a mixture of timing inputs and outputs for both media clocks and PTP synchronization.

2.9.3.1 Audio De-jittering PLL

A CS2000 Audio De-Jittering PLL is available on the Bach Development Kit board as an option for recovering a very low jitter media clock. This is not required for customer designs.

The Bach SOM standard configuration has 3 signals dedicated to interfacing with this external PLL:

• CS2000_CLK_OUT • CS2000_CLK_IN • CS2000_AUX_OUT


2.9.3.2 Word Clock

The AUDIO_WCLK_OUT is driven by the internal media clock of the device and can be measured to provide information on the sampling frequency, jitter and phase synchronization.

AUDIO_WCLK_IN is provisioned for future use as a “house clock” for use in synchronizing devices to an external sampling reference.

2.9.3.3 PPS and GrandMaster

The Bach Endpoints support operation as a GrandMaster if desired. A GrandMaster is a special highly accurate PTP Master that references a known high quality clock, typically from a GPS receiver. The high quality clock outputs a 10HMz signal and PPS output which are connected to the Bach SOM GRAND_MASTER_IN and PPS_IN respectively.



The PPS_OUT signal is provided as a reference to compare against other PTP masters or slaves in the system to observe the phase lock between devices.

2.10 Memory

2.10.1 DDR3 SDRAM

Table 2-14 lists the SOM Board specific DDR3 SDRAM references, names and their functional descriptions

Table 2-14: Board Specific DDR3 SDRAM

Board Reference


Description

U2, U3 DDR3 SDRAM 1.5V Two 256 MB HPS DDR3 SDRAM at 16 bits each, total of 32 bits

The SOM can be populated with one or both DDR3 components. If only one is used, then the effective bandwidth is reduced by half due to the x16 DDR3 bus per component.

The pinout is also compatible with various sizes of DDR3 modules module 128MByte per chip up to 512MByte.

2.10.2 EPCQ FLASH

The EPCQ FLASH is not populated on the SOM since FPGA configuration is intended to be performed by the HPS with FPGA bitfiles stored in either the QSPI or MicroSD FLASH.

2.10.3 QSPI FLASH

Table 2-15 lists the SOM Board specific QSPI Flash references, names and their functional descriptions.

Table 2-15: Board Specific QSPI Flash

Board Reference


Description

U6 Flash memory 3.3V 1Gb QSPI flash

The QSPI FLASH footprint is compatible with a wide variety of QSPI FLASH devices and sizes (from 64Mbit to 1Gbit in size).



2.11 Power

You can power up the SOM Board from a single 5-6V power supply.

Table 2-16 lists the SOM Board specific power references, names and their functional descriptions.

Table 2-16: Board Specific Power

Board Reference


Description

U8 IC-LXDC55FAAA 1.1V From a 5V input U9 IC-LXDC55FAAA 3.3V From a 5V input U1 IC-LXDC55FAAA 1.5V From a 5V input U4 IC-MIC39102 2.5V From a 3.3 rail

2.11.1 Input Power

Input power must be between 5V and 6V with a minimum current of 1.0A. Power is supplied via pins 1-6 of the 144-pin edge connector.

2.11.2 Power Rails and Current

The SOM generates 4 power supply voltages for on-board needs and is described in Table 2-17.

Table 2-17: Power Consumption

Voltage Rail

Current to ICs

Current to Child Regulators

Total Pout (mW)

Efficiency Pin (mW)

Vin Iin Pdiss

3.3 200 250 450 1485 80% 1856 6 309 371 1.1 850 0 850 935 80% 1169 6 195 234 1.5 800 0 800 1200 80% 1500 6 250 300 2.5 250 0 250 625 LDO 825 3.3 250 200

Total

Iin: 754mA

Total

Pin: 4525mW

2.11.3 FPGA Bank Voltages

Table 2-18 lists the I/O power rails.

SOM Reference Manual Chapter 3: Additional Information


Table 2-18: I/O Power Rails

Bank I/O Standard SOM Board Voltage 3A 16 2.5 3B 32 3.3 4A 68 3.3 5A 16 3.3 5B 0 0 HPS 6A 56 1.5 HPS 6B 44 1.5 HPS 7A 19 3.3 HPS 7B 22 3.3 HPS 7C 12 3.3 HPS 7D 14 3.3 8A 13 3.3

Chapter 3: Additional Information

This section provides additional information about the SOM Board, this document and Coveloz.

3.1 Board Revision History

The following table lists the versions of all releases of the Bach SOM Board.

Release Date Version Description June 2015 Initial release for ??

3.2 How to Contact Coveloz

For any questions or support issues contacts are found at Coveloz’s website, http://coveloz.com/contact-us/ .

Documents

Bach SOM Reference Manual