B. Hall June 14, 2001Pixel ReadoutPage 1 Goals Look at two word synchronization techniques. Look at signal integrity of LVDS transmission at receiving

B. Hall June 14, 2001 Pixel Readout Page 1

Goals

• Look at two word synchronization techniques.

• Look at signal integrity of LVDS transmission at receiving end of 34’ cable for 177Mbps and 139Mbps data rates.

• Determine if DC balancing cable is necessary.

• Quantify timing margins based on measured results and assumptions.


Word Sync Method A

7 6 5 4 3 2 1 0

1

Ad d a le a d ing '1' fo r wo rd m a rk

23 b its d a ta p a ylo a d , 24 b its e nc o d e d .

23 22 21

7 6 5 4 3 2 1 0

1

Ad d a le a d ing '1' fo r wo rd m a rk

23 b its d a ta p a ylo a d , 30 b its e nc o d e d .

29 28 27

No DC Ba la nc ing

DC Ba la nc ing (e .g . 4B/5B)


Word Sync Method A

DCBa la n c eEnc o d e r

23 29 SSR

SC LK

23 b it Wo rd @ RC LK

Ad dWo rd M a rk

Bit

SSR

Re tu rn C LK

Se rDa ta 5

Se rDa ta 6

5

4

SSR Se rDa ta 45

SSR Se rDa ta 35

5

SSRSe rDa ta 2

5

SSRSe rDa ta 1

5

RC LK = SC LK/5

Implementation of Word Sync Method A with DC balancing:

With RCLK = 34.72Mhz, SCLK = 173.6Mhz (~174Mbps serial links)


Word Sync Method A

23 SSR

SC LK


Ad dWo rd M a rk

Bit

SSR

Re tu rn C LK

Se rDa ta 5

Se rDa ta 6

4

3

SSR Se rDa ta 44

SSR Se rDa ta 34

4

SSRSe rDa ta 2

4

SSRSe rDa ta 1

4

RC LK = SC LK/4

Implementation of Word Sync Method A with NO DC balancing:

With RCLK = 34.72Mhz, SCLK = 138.88Mhz (~139Mbps serial links)


Word Sync Method A

• Simple to Implement

• Receiver FPGA looks for leading ‘1’ to mark word boundaries.

• FPGA can check for out of sync signs: illegal column address, more or less than 24 (or 30 in DC balance case) bit long words.

• FPIX should transmit a sync word while data out of the core is idle.

• Will need handshaking protocol allowing the receiver FPGA to request sync word transmission from FPIX.


Word Sync Method B

7 6 5 4 3 2 1 0

1

29 28 27

1000

Un iq ue 5 b it he a d e r le a d s e a c h wo rd

23 b it d a ta p a ylo a d is e nc o d e d in to 25 b its m a king these q ue nc e “00 011” im p o ssib le to a p p e a r. In a d d itio n the e nc o d ing DC b a la nc e s the line a llo w ing no m o re tha n 4 se q 0 s o r 1s. D a ta is tra nsm itte d N RZI.


Word Sync Method B

• A bit more complicated to implement:

9B/10BTYPE A

9B/10BTYPE B

9B/10BTYPE A

14B/15B

5B/5B

A (Up p e r 5 b its)

B (Lo we r 5 b its)

C

D (Up p e r 5 b its)

E (lo we r 5 b its)

F

G

23

9

9

5

9

9

9

95

5

5

5

10

5

5

15

5



Word Sync Method B

6 serial lines would look like:

SSR

SC LK

SSR

Re tu rn C LK

Se rDa ta 5

Se rDa ta 6

SSR Se rDa ta 4

SSR Se rDa ta 3

SSRSe rDa ta 2

SSRSe rDa ta 1

5A

5B

5D

5E

5G

5“000 11”

RC LK = SC LK/5


Word Sync Method B

One serial line configuration:

SSR

SC LK

Re tu rn C LK

Se rDa ta 1

3000 011

RC LK = SC LK/30

FC


Word Sync Method B

• More logic required to implement.

• Word sync every word…very fast recovery from transmission errors…should be very robust.

• Must use 30 bits per word…177Mbps serial links.

• Encoding also DC balances by allowing no more than 4 consecutive 0s or 1s (with NRZI).


Signal Edge Skew Sources

SC LK

FPIXPERIPHERY

FEEDTHRU C ABLE DC B FPG A IO B

FPIXPa d to Pa d

De la y

Tra c e Ske w Pro p a g a tio nDe la y

C a b le C ha rg ingSke w

Tra c e Ske w FPG APin to Pin

De la y

Se ria l Line 1

Se ria l Line 2

Se ria l Line 3

Se ria l Line 4

Se ria l Line 5

Se ria l Line 6

Re turn C LK


Data Edge Skew Sources

Da ta C o m b ine r Bo a rdC a b le C ha rg ing Effe c t

C a b le Pro p De la yFe e d thru Bo a rd

Pa d to Pa d De la y

FPG A Pin to Pin De la y

FPG A La tc h Se tupRe q uire m e nt

Id e a lEd g e

Ed g e Ske w Fa c to rs

Da ta Ed g e @ Rc vr

Re turn C LKEd g e


Skew Due to Cable Charging

• Use 34’ pleated foil flat cable (baseline for pixel system).

• Inject LVDS signal at 177Mbps and 139Mbps.

• Use pattern generator to transmit pattern with no DC balancing (up to 23 seq 0s or 1s) or a pattern with DC balancing (up to 4 seq 0s or 1s).

• Look at received (LVDS to 3.3V CMOS) data and measure the signal edge movement due to cable charging.


Cable Charging – 177Mbps No DC Balance


Cable Charging – DC Balance: upto 4 seq 0s or 1s


Cable Charging – 139Mbps No DC Balance


Cable Charging – 139Mbps DC Balance: upto 4 seq 0s or 1s


Cable Charging Conclusions

• With 34’ cable @ 177Mbps or 139Mbps, DC balancing not critical.

• @177Mbps and No DC balancing: skew = 2.53ns

• @177Mbps and DC balancing: skew = 2.33ns

• @139Mbps and No DC balancing: skew = 1.69ns

• @139Mbps and DC balancing: skew = 1.69ns


Other Contributions

• FPIX pad to pad delay: 250ps (assumption)

• Feedthrough board: 0ns (assumption)

• Cable propagation delay variation (pair to pair): 1.3ns (previous study)

• Cable charging: 1.69ns (@139Mbps, DC Balanced or not), 2.53ns (@177Mbps, No DC Balance), or 2.33ns (@177Mbps, DC Balanced up to 4 seq 0s or 1s)

• Data combiner board: 0ns (assumption)

• FPGA pin to pin delay: 250ps (assumption)

• FPGA latch setup requirement: 800ps (Specification).


Timing Margins (Clock Sampling Window)

• With 177Mbps and No DC Balancing: 520ps

• With 177Mbps and DC Balancing (4 seq): 720ps

• With 139Mbps and No DC Balancing: 2.9ns

• With 139Mbps and DC Balancing (4 seq): 2.9ns

Also need to consider jitter of the clock itself.


Conclusions/Discussion

• 177Mbps has a good chance of not working.

• 139Mbps has a good chance of working.

• FPIX multiple serial line skew should be as tight as possible.

• Word sync method A (leading 1 technique) will have to be used for 6 serial line configuration with 139Mbps.

• Word sync method B (leading “00011” technique) can still be used for 1,2, or 3 serial line configurations (@139Mbps).

Documents

B. Hall June 14, 2001Pixel ReadoutPage 1 Goals Look at two word synchronization techniques. Look at signal integrity of LVDS transmission at receiving