AXI Overview

8/17/2019 AXI Overview

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© 2010 Wipro Ltd - Confidential

AXI Overview

Upscale Training


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© 2010 Wi ro Ltd - Confidential2

© 2010 Wipro Ltd - Confidential2

Advanced Microcontroller Bus Architecture – On-chip bus protocol from ARM

• On-chip interconnect specification for the connection and management offunctional blocks including processor and peripheral devices

– Introduced in 1996

– AMBA is a registered trademark of ARM Limited – AMBA is an open standard

AMBA


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Evolution of AMBA Standard


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This presentation outlines the specific topics/sections that need to beunderstood.For each of the topic corresponding section number in the AMBA®AXI™ and ACE™ Protocol Specification (Issue E, Date 22 February 2013)is provided.

This has been divided into 3 parts: – Part A: AMBA AXI3 and AXI4 Protocol Specifications – Part B: AMBA AXI4-Lite – Part C: ACE Protocol Specification

Please go through the details in the AMBA specification.

Course Summary


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Introduction to AXI Protocol – Features (A1.1)

– Revisions (A1.2) – AXI Architecture (A1.3)

Signal Descriptions – Global Signals (A2.1) – Write Address Channel Signals (A2.2) – Write Data Channel Signals (A2.3) – Write Response Channel Signals (A2.4) – Read Address Channel Signals (A2.5)

– Read Data Channel Signals (A2.6) – Low Power Interface Signals (A2.7)

Signal Interface Requirements – Clock and Reset (A3.1) – Basic read and write transactions (A3.2) – Relationship between channels (A3.3) – Transaction Structure (A3.4)

Transaction Attributes

– Transaction Attributes (A4.1) – AXI3 memory attribute signaling (A4.2) – AXI4 changes to memory attribute signaling (A4.3) – Memory Types (A4.4) – Mismatched memory attributes (A4.5) – Transaction Buffering (A4.6) – Access Permissions (A4.7) – Legacy Considerations (A4.8)

Multiple Transactions – AXI Transaction Identifiers (A5.1)

– Transaction ID (A5.2) – Transaction Ordering (A5.3) – Removal of Write Interleaving Support (A5.4)

AXI4 Ordering Model – Definition of the ordering model (A6.1) – Master Ordering (A6.2) – Interconnect Ordering (A6.3) – Slave Ordering (A6.4)

– Response before final destination (A6.5) – Ordered write observation (A6.6)

Atomic Accesses – Single Copy Atomicity Size (A7.1) – Exclusive Accesses (A7.2) – Locked Accesses (A7.3) – Atomic Access Signaling (A7.4)

AXI4 Additional Signalling

– QoS Signaling (A8.1) – Multiple Region Signaling (A8.2) – User defined Signaling (A8.3)

Low Power Interface – About Low Power interface (A9.1) – Low Power Clock Control (A9.2)

Default signaling and Interoperability – Interoperability principles (A10.1)

– Major interface categories (A10.2) – Default Signal Values (A10.3)

Part A: AMBA AXI3 and AXI4 Protocol Specifications


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Definition of AXI4-Lite (B1.1)Interoperability (B1.2)Defined Conversion Mechanism (B1.3)Conversion, Protection and Detection (B1.4)

Part B: AMBA AXI4-Lite


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© 2010 Wi ro Ltd - Confidential7 © 2010 Wipro Ltd - Confidential7

About ACE (C1)Signal Descriptions (C2)Channel Signaling (C3)Coherency Transactions on Read and Write Address Channels (C4)Snoop Transactions (C5)Interconnect Requirements (C6)Cache Maintenance (C7)Barrier Transactions (C8)Exclusive Accesses (C9)

Optional External Snoop Filtering (C10)ACE-Lite (C11)Distributed Virtual Memory (C12)Interface Control (C13)

Master Design Recommendations (C14)

Part C: ACE Protocol Specification


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Part AAMBA AXI3 and AXI4 Protocol Specifications


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AMBA AXI protocol is targeted at high-performance, high-frequency system designs

AXI key features – Support for separate channels for:

• Read Address• Read Data• Write Address• Write Data and•

Write Response – Support for unaligned data transfers using byte strobes – Ability to issue multiple outstanding addresses – Out of order (OO) transaction completion – Support for data interleaving – Advanced system cache support

• Specify if transaction is cacheable/bufferable• Specify attributes such as write-back/write-through

– Enhanced protection support• Secure/non-secure transaction specification

– Exclusive access (for semaphore operations) – Register slice can be easily added for timing-closure

Advanced eXtensible Interface (AXI):


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AXI System Components


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Read address channel and Write address channel – Conveys address and other control information – Variable length burst: 1 ~ 16 data transfers

• Exception: In AXI4, INCR bursts can have lengths upto 256 transfers.

– Burst with a transfer size of 8 ~ 1024 bits (i.e.1Byte ~ 128Bytes)

Read data channel – Convey data and any read response info. – Data bus can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide – Read response is signaled per transfer.

Write data channel – Data bus can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide

Write response channel – Write response info, signaled for the entire burst.

NOTES:Each channel is independent and uses a 2-way flow-control.

5 Independent Channels


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AMBA AXI Read Channels


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13 © 2010 Wipro Ltd - Confidential13


Independent





Give me some data

Independent


15/91© 2010 Wi ro Ltd - Confidential15 © 2010 Wipro Ltd - Confidential15

AXI Read Channels

Give me some data

Here you go

Independent



AXI Read Channels

Give me some data

Here you go

Independent

channels synchronized with ID #or “tags”



AXI Write Channels



AXI Write Channels

Independent

Independent



AXI Write Channels

I’m sending data. Please store it.

Independent

Independent



AXI Write Channels


Here is the data.

Independent

Independent



AXI Write Channels


Here is the data.

I received that data correctly.

Independent

Independent



AXI Write Channels


Here is the data.

I received that data correctly.

Independent

Independent

channels synchronized with ID #or “tags”



AXI Flow-Control • AXI uses a valid/ready

handshake acknowledge• Each channel has its own

valid/ready

• Information moves only when: – Source has Valid information and – Destination is Ready

• On each channel the master orslave can limit the flow

• Flexible signaling functionality – Inserting wait states – Always Ready – Same Cycle Acknowledge

Inserting Wait States

Always Ready

Same Cycle Acknowledge



AXI Flow-Control

Transfer

Inserting Wait States

Always Ready

Same Cycle Acknowledge

• AXI uses a valid/ready

handshake acknowledge• Each channel has its own

valid/ready

• Information moves only when: – Source has Valid information and – Destination is Ready

• On each channel the master orslave can limit the flow

• Flexible signaling functionality – Inserting wait states – Always Ready – Same Cycle Acknowledge



AXI Read

Read Address Channel

Read Data Channel




Read Burst Operation

Read requestis initiated

Read requestis accepted

Slaveis ready

1st datais transferred

The last datais transferred

Note: data transfer only when valid = ready = 1




Separation of address and data channel – Master provides only the start address of burst – Slave needs to generate the remaining addresses based on

burst type (FIXED, INCR, WRAP)

One Address for Burst

A2

D2D 2 D 3 D 4

A3

D22 D23 D3

ADDRESS

DATA




Overlapping Read Bursts

Read request Ais accepted Read request B

is accepted via AR channelwhile data A(0) is

transferred via R channel




AMBA AXI Write

29

Write Address Channel

Write Response Channel

Write DataChannel




Write Burst Operation

Write request Ais accepted

Response completeswrite operation

Dependencies between Channel Handshake




To prevent a deadlock situation, you must observethe dependencies that exist between the handshakesignalsIn any transaction: – The VALID signal of one AXI component must not

be dependent on the READY signal of the othercomponent in the transaction

– The READY signal can wait for assertion of the VALIDsignal

Dependencies between Channel HandshakeSignals (AXI3)

WLAST

Dependencies between Channel Handshake [AXI4]


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The AXI3 protocol requires that the write response for all transactionsmust not be given until the clock cycle after the acceptance of the last datatransferIn addition, the AXI4 protocol requires that the write response for alltransactions must not be given until the clock cycle after address

acceptance

Dependencies between Channel HandshakeSignals (AXI4)

AXI3

AXI4

WLAST

[AXI4]


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AXI gives an ID tag to every transaction

Use of IDs

Write AddressChannel

Write

DataChannel

WriteResponseChannel

Read AddressChannel

ReadDataChannel


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Real implementation – Transaction ID = – Channel ID = original AXI transaction id – Master ID is needed to identify the initiating master among all the masters

Transaction ID Implementation

CPUVideo

Decoder

3DGraphic

s

LCDControl

VideoProcess Mixer DMA

Interconnect

Memory

Controller

ID: 3 ID: 2 ID: 3 ID: 0 ID: 3 ID: 2 ID: 4

ID: 4 + ceil(log 27)=7 bits


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Multiple Outstanding Addresses: – By using IDs, a master can issue transactions without waiting for earlier

transactions to complete.

Write Data Interleaving in AXI3 Slaves: – With Write Data Interleaving, an AXI3 slave can accept interleaved write-data

with different AWID values. – This feature is not supported in AXI4

• All Write Data for a transaction must be provided in consecutive transfers on thewrite data channel.

• WID signal is not supported in AXI4

Out of Order completion – Transactions with the same ID are completed in order – Transactions with different IDs can be completed out of order – Fast-responding slaves respond in advance of earlier transactions with slower

slaves – This is not a required feature. Simple masters and slaves can process one

transaction at a time in the order they are issued

Use of IDs


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Ordering by transaction ID – Slave can handle data transfers with different transaction IDs out-of-

order – The order within a single burst is maintained

Out-of-Order Transaction

A

D D 2 D 3 D 4

A2

D2 D22 D23

ADDRESS

RDATA

A3

D3


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Write request and data – The write data can appear at an interface before the write

address that relates to it

Two relationships that must be maintained are: – Read data must always follow the address to which the

data relates – A write response must always follow the last write

transfer in the write transaction to which the writeresponse relates

Ordering Rules #1: Request and Response


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No ordering restrictions between read and write transactions with thesame AWID and ARID. If a master requires an ordering restriction thenit must enforce the ordering.

Ordering Rules #2: Read & Write Transactions with Same ID


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The data for a sequence of read

transactions with the sameARID must be returned inorder that: – When reads with the same ARID

are from the same slave then theslave must ensure that the readdata is returned in the same orderthat the addresses are received

– When reads with the same ARIDare from different slaves, theinterconnect must ensure thatthe read data is returned in thesame order that the master issuedthe addresses in.

Ordering Rules #3: Multiple reads with same ARID

SlaveIP

MasterIP

SlaveIP 1

SlaveIP 2

Inter-connect

MasterIP


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Interleaving rule – Write Data with different ID can be interleaved. – This is supported only in AXI3 – The order within a single burst is maintained

Ordering Rules #4: Write Interleaving

A

D D 2 D 3 D 4

ADDRESS

WDATA

A2

D2 D22 D23

A3

D3

[AXI4]


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No support of write interleaving in AXI4

Master must ensure same order for write data as that of address

Removal of WID in AXI4, why? – Write data with different AWIDs follow their address order + no write

interleaving no need of WID! – Responses to multiple writes with different IDs can be out-of-order from

address order BID remains!

Write Interleaving in AXI4


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OKAY◦ Normal access success/Exclusive access failure/Exclusive access to non-

supporting Slave

EXOKAY◦ Exclusive access success

SLVERR◦ Slave generates error response/unsupported transfer size/WR access to

RO/timeout condition in slave/access to address where no registerpresent/access to disabled or powered-down function

DECERR◦

Can not Decode Slave Access then default slave gives DECERR(Note: For a write transaction, there is just one response given for the entire

burst and not for each data transfer within the burst. In a read transaction,the slave can give different responses for different transfers within aburst.)

AXI Protocol Responses


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AXI enables the insertion of a register slice in any channel at the cost of

an additional cycle latency – Trade-off between latency and maximum frequency

Register slice can be used at any channel independentlyRegister slice incurs one cycle latency per insertion

Register Slice for Timing Isolation

AXI

Master

AXI

Slave

Write data

WREADY

Read data

RREADY

Response

BREADY

Write Address/Control

AWREADY

Read Address/Control

ARREADY


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A single clock signal, ACLK.◦ All input signals sampled on the rising edge of ACLK. All output signal changes

must occur after the rising edge of ACLK.◦ Must be no combinatorial paths between input and output signals on both

master and slave interfaces.

Single Active low reset ARESETn.

Some More things to know

dd l


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Transaction burst type determines address bus behavior – Fixed, increment, or wrap

Unaligned Access◦ Master uses lower address bits; byte lane strobe must be consistent to lower

address bits information

Optional address Lock signals facilitates exclusive and atomic accessprotection

System cache supportProtection unit support

AXI Additional Features

h Si d


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Burst Length, Size and Type

D B U N T f


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In a Narrow Transfer, the address and control (WSTRB) determine which bytelanes the transfer uses.WSTRB[n:0] signals, when high specify which byte-lanes are used

Example 1: A narrow transfer with 8-bit transfers – Burst has 5 transfers – Starting address is 0 – Transfer size is 8-bits – Data bus-width is 32-bit – Burst type is INCR

Example 2: A narrow transfer with 32-bit transfers

– Burst has 3 transfers – Starting address is 4 – Transfer size is 32-bit – Data bus-width is 64-bit – Burst type is INCR

Data Bus Usage: Narrow Transfers

U li dT f


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AXI Support Unaligned Transfers

– Unaligned Transfer is a transfer inwhich the 1 st byte accessed isunaligned with the naturaladdress boundary

– e.g. A 32-bit transfer that startsat address 0x1002 is not alignedto the natural 32-bit addressboundary

Master can: – Use low-order address lines to

signal an unaligned start addressOR

– Provide an aligned address anduse byte-lane strobes to signalthe unaligned start address

Unaligned Transfer

U li d T f (C ’d)


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Unaligned Transfer (Cont’d)

INCR burst case

U li d T f (C ’d)


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Wrapping burst case – The wrap boundary is aligned to the total size of the data to be transferred• That is, to ( (size of each transfer in burst) x (number of transfers in burst) )

– After each transfer, the address increments same as for INCR Burst – If incremented address is ( (wrap boundary) + ( total size of data to be

transferred) ), then the address wraps around to wrap-boundary.

Unaligned Transfer (Cont’d)

B t L th (AXI4)[AXI4]


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AR(W)LEN[7:0] allows INCR burst of 256 beatsBurst in AXI3 protocol: – Early termination of bursts is not supported. – A burst must not cross a 4-kbyte boundary. This ensures that a burst is

only destined for a single slave.

AXI4 protocol longer burst support: – Bursts longer than 16 beats are only supported for the INCR burst

type. Both WRAP and FIXED burst types remain constrained to amaximum burst length of 16 beats.

– Exclusive accesses are not permitted to use a burst length greater than16.

Burst Length (AXI4)

System Cache Support [AXI3]


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AxCACHE[3:0] signals define thetransaction attributes of atransferTransaction attributes control:

– How a transaction progressesthrough the system – How any system-level cache handles

the transaction

y ppARCACHE[3:0] / AWCACHE[3:0]

L1 Data Cache

L1 InstructionCache

Unified L2Cache

RF Memory

Memory

Memory

MemoryCPU

System Cache Support [AXI3]


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Bufferable bit (B): AxCACHE[0] – The interconnect or any component can delay the transaction for any number of cycles. This is

usually only relevant to writes. – Transaction response may not be from the final destination, but from the intermediate point,

like Cache. The cache is then responsible to update the memory.

Cacheable bit (C): AxCACHE[1] – The characteristics of the transaction at the final destination does not have to match the

characteristics of the original transaction. – For writes this means that a number of different writes can be merged together. – For reads this means that a location can be pre-fetched or can be fetched just once for

multiple read transactions. – To determine if a transaction should be cached this bit should be used in conjunction with the

Read Allocate (RA) and Write Allocate (WA) bits.

Read Allocate bit (RA): AxCACHE[2] – If ‘1’, the transaction should be looked -up in the cache

– In case of read miss, it is recommended to allocate an entry in the cache – If C=low, RA=low

Write Allocate bit (WA): AxCACHE[3] – If ‘1’, the transaction should be looked -up in the cache – In case of write miss, it is recommended to allocate an entry in the cache – If C=low, WA=low

y ppARCACHE[3:0] / AWCACHE[3:0]

Ch g t T ti Att ib t Sig li g[AXI4]


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The AxCACHE[1] bits are renamed: – From ‘Cacheable’ to ‘Modifiable’ – to better describe the required functionality – Actual Functionality is unchanged

Ordering requirements are defined for Non-Modifiable transactions

– Ordering between transactions should be maintained, if the transactions satisfyall of the following conditions:

• Transactions are Non-Modifiable• Transactions use the same ID• Transactions target the same slave device

Meanings of RA and WA bits are updated: – One bit indicates if an this transaction should be allocated in Cache – Other bit indicates if an allocation could have been made due to another

transaction

Changes to Transaction Attribute Signaling

RA andWA Bits[AXI4]


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For Read Transactions: – RA bit means the same: The location could have been previously allocated inthe cache. It is recommended that this transaction is allocated in cache.

– WA bit is redefined: The location could have been previously allocated in thecache because of other transaction – Either Write transaction or Transactionby other master

For Write Transactions: – WA bit means the same: The location could have been previously allocated in

the cache. It is recommended that this transaction is allocated in cache. – RA bit is redefined: The location could have been previously allocated in the

cache because of other transaction – Either a Read transaction or Transactionby other master

This change means: – For a same location, a read and a write transfer may have different values for

AxCACHE

RA and WA Bits

Protection Support


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Normal or Privileged Mode: AxPROT[0]◦

Indicates whether an access was done by a Master in Privilege Mode orin Unprivileged Mode◦ LOW indicates an access done by a Master in Unprivileged Mode◦ HIGH indicates an access done by a Master in Privileged Mode

A privileged processing mode typically has a greater level of access within asystem.

Secure or Non-secure: AxPROT[1]◦ LOW indicates an Secure access◦ HIGH indicates an Non-secure access

Used where a greater degree of differentiation between processing modes isrequired.

Instruction or data, AxPROT[2]◦ LOW indicates a data access◦

HIGH indicates an instruction access.

pp(AWPROT[2:0], ARPROT[2:0])

Atomic Access


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Normal access, AxLOCK[1:0]=b00

Exclusive access, b01 – Exclusive read – Exclusive write – If no intervening write to the address

region, EXOKAY response. If not,OKAY response. – Usually used for read-modify-write

Locked access, b10 – Start with b10, and end with b00 – During the period, only the lock

initiating master can access theaddress region

(ARLOCK[1:0], AWLOCK[1:0])

ExclusiveAccess


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Semaphore type operation without requiring bus to remain locked to aparticular master for the duration of the operation

Usually used for read-modify-write kind of operations

Slave must have additional logic to support exclusive access.

The basic process for an exclusive access is: – A master performs an exclusive read from an address location. – At some later time, the master attempts to complete the exclusive operation

by performing an exclusive write to the same address location. – The exclusive write access of the master is signaled as:

• Successful (EXOKAY) if no other master has written to that location between the

read and write accesses.• Failed (OKAY) if another master has written to that location between the read and

write accesses. In this case the address location is not updated

Exclusive Access

time

E.RD 0x100 WR 0x100

Master 1 Master 2

E.WR 0x100

Master 1

OKAY

Slave 1

LockedAccess[AXI3]


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Interconnect must ensure that only that master is allowed access to theslave region until an unlocked transfer from the same master completesMaster should have no other outstanding transactions waiting to completebefore issuing locked sequenceFinal transaction effectively removes the lock

Locked Access

time

0x100 0x100

Master 1 Master 2

0x100

Master 1

Lock Unlock

Atomic Access in AXI4[AXI4]


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No support of locked access

All locked accesses from AXI3 masters need to be converted to normalaccesses

Atomic Access in AXI4

Additional Signaling (Optional)[AXI4]


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Quality of Service Signaling (AxQOS[3:0])

– AxQOS 4-bit signals sent on address channel for each transaction – This protocol does not specify exact use of QoS identifiers – Recommendation: Can be used as a priority indicator for that transaction – Default value of b0000 indicates no participation in QoS scheme

Region Identifier Signals ( AxREGION[3:0] ): – 4-bit signals can uniquely identify upto 16 different regions – The region identifier provides a decode of higher order address bits – Using regional identifiers, a single Physical Interface on a slave can mimic multiple (upto

16) logical interfaces, each with a different location in the system address map – Interconnect should produce AxREGION signals when performing the address decode

function for a signle slave that has multiple logical interfaces

User Signals on each AXI Channel for ‘User Defined’ Signaling – ( AWUSER, WUSER, BUSER, ARUSER, RUSER ) – Specification recommends not to use them, to avoid interoperability issues

Additional Signaling (Optional)

Low Power Interface (C channel)


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Optional Extension to AXI protocol – Uses 3 level signals for handshake between the system-clock-controller and

the peripheral

Signals: – CACTIVE: (driven by peripheral)

• High => Peripheral requires a clock signal. Clock-Controller must enable the clockimmediately.

• Low => Peripheral does not require the clock

– CSYSREQ: (driven by clock-controller)• Low => Request for the peripheral, to enter a low-power state•

High => Request for the peripheral, to exit a low-power state

– CSYSACK: (driven by peripheral)• Low => Low-power entry request acknowledged by peripheral• High => Low-power exit request acknowledged by peripheral




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The peripheral can accept or deny the request, from the system-clock-controller, to enter low-power state.

The level of the ‘CACTIVE’ signal when the peripheral acknowledges the

request by driving CSYSACK low indicates the acceptance or denial of therequest.




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Acceptance of low-power request

Denial of low-power request

AXI4 Updates overAXI3: Summary


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Additional QoS Signaling: AxQOS[3:0]Additional 4-bit interface signals AxREGION

◦ allows 16 different regions to be uniquely identified◦ Region identifier should be constant in 4kB address space

Added USER signals – AxUSER, RUSER,WUSER,BUSER

Removes support for locked transfers so AxLOCK signal is single bit

(Normal/Exclusive)Removal of Write Interleaving support – Removes WID signal

Write response requirements are updated:◦ AXI3: clock cycle after last data transfer◦

AXI4: clock cycle after address acceptanceSupport of upto 256beats of burst lengths (for INCR bursts)AWCACHE and ARCACHE signaling is updated

AXI4 Updates over AXI3: Summary


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Part BAMBA AXI4-Lite

AXI4 Lite


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AXI4-Lite is a subset of the AXI4 protocol intended for communicationwith simpler, smaller control-register style interfaces in components.AXI4-Lite is a simpler AXI4 for onchip devices requiring a more powerfulinterface than APB.Features:

All transactions with burst length of 1all data accesses are the same size as the width of the data bussupport for data bus width of 32-bit or 64-bitall accesses are equivalent to AWCACHE or ARCACHE equal to b0000(i.e. non-modifiable and non-bufferable)

exclusive accesses are not supported.AXI IDs not supported – All transactions must be in orderSo signal list reduced

AXI4 Lite

AXI Lite Signal list


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Subset of AXI signal setSimple traditional signalingTargeted applications: simple, low-performance peripherals – GPIO – Uart

Signals not-supported in AXI-Lite: – AWLEN, ARLEN – AWSIZE, ARSIZE – AWBURST, ARBURST – AWLOCK, ARLOCK – AWCACHE, ARCACHE – WLAST, RLAST

AXI Lite Signal list


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Part CACE Protocol Specification

Coherency Problem


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Two problems for systems thatcontain caches:

1) Memory may be updated (byanother master) after a cachedmaster has taken a copy

• The cache no-longer containsup-to-date data

2) In systems that contain write-back caches, if the master writes

to local cached copy• The memory no-longer contains

up-to-date data.• A 2nd master reading from

memory will see stale data.

Coherency Problem

Interconnect

Master1 Master2

Cache Cache

MainMemory

Master3

Cache

Hardware based Coherency Approaches


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Snooping Cache Coherency Protocols – Transactions to a shared- region are ‘broadcast’ to all masters – All masters ‘listen -in’ to all shared data -transactions originating from other

masters – When the master detects a read transaction for which it has the most up-to-

date data, it provides the data to the other master requesting it; or in the caseof a write, it invalidates it’s own copy.

Directory based Cache Coherency Protocols

– A single ‘directory’ is maintained, which contains a list of where every cachedline within the system is held. – A master initiating a transaction first consults the directory to find where the

data is cached and then directs cache coherency traffic to only those masterscontaining cached copies.

Hardware based Coherency Approaches

Features


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ACE is an extension to AXI

Aims at providing Hardware based cache coherency

Adds 3 new Snoop Channels:

Adds additional signal to existing AXI channels

Also adds barrier support to enforce ordering of multiple outstandingtransactions

Features

Specification


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ACE Protocol is realized using:

– A 5-State Cache Model to define the state of a Cache Line in the coherent system – Additional Snoop Channels that enable communication with a cached master whenanother master is accessing a shared address location

• Read Channels: (AR, R)• Write Channels: (AW, W, B)• Snoop Channels: (AC, CR, CD)

– Additional Signaling on the existing AXI4 channels that enables new transactions andinformation to be conveyed

ACE Supported Policies – 100% Snoop – Directory Based

– Anything in-between (Snoop Filter)

ACE adds following to the AXI – Support for hardware coherency – Support for cache maintenance

– Support for Barriers

Specification

ACE Cache Line States


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Terms used to describe the state of a cacheline are:

Unique: – The cache line resides ONLY in this cache

Shared – The cache line MAY be in other cache

Clean – The cache controller does not have to

update the main memory

Dirty – The cache controller is responsible to

update the main memoryInvalid – The cache line is not being used for

caching data

Devices are not required tosupport all 5 states internally

ACE Cache Line States

Shareability Domains defined in ACE


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Non-Shareable – The domain contains a single master

Inner Shareable – The domain can include additional masters

Outer Shareable – The domain contains at least all masters in the inner domain – Can include additional masters

System – This domain includes all masters in the systems

Shareability Domains defined in ACE

Example of Shareability Domains

Use of Shareability Domains


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For Coherency Transactions: – A master uses a shareability

domain to determine whichother masters might have a copyof the addressed location in their

local cache – Interconnect uses this

information to determine, for anygiven transaction, which othermasters must be snooped

For Barrier Transactions: – The domain of a barrier

transaction can be used todetermine how far a barriertransaction must propagate

Use o S a eab ty o a s

Additional Snoop Channels


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Snoop Channels enable communication with acached master when another master is accessing a

shared address location

AC Channel (Coherent Address Channel): Input toMaster – ACADDR used for sending the address of snoop

request to a cached master, accompanied withcontrol signals

CR Channel (Coherent Response Channel): Outputfrom Master – CRRESP is used by the master to signal the

responses to snoop to the interconnect – A narrow, 5-bit response indicating whether an

associated data transfer is expected on the CD

channelCD Channel (Coherent Data Channel): Outputfrom Master – CDDATA, used by the master to provide the data in

response to a snoop. – Optional for write-through caches

p

Additional Signals to Existing AXI Channels


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ACE adds additional signals to existing AXI Channels:

– Read Address Channel and Write Address Channel• ARSNOOP [3:0] / AWSNOOP[2:0 ]

- Indicate the type of snoop transactions for shareable transactions• ARBAR [1:0] / AWBAR [1:0]

- Are used for barrier signaling•

ARDOMAIN [1:0] / AWDOMAIN [1:0]- Indicates which masters should be snooped for snoop transactions

and which masters must be considered for ordering of barriertransactions

– Read Data Channel and Write Data Channel• RRESP [3:2]

- Additional response bits, for shared read transactions that areindirectly driven by CRRESP outputs from a snooped master

• RACK / WACK

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ACE Protocol Design Principles


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In ACE, snoop requests must be responded inorder (as it doesn’t have IDsignals)

The system interconnect is responsible for coordinating the progress of allshared (coherent) transactions:

– e.g. The interconnect may present snoop addresses to all masters in parallelsimultaneously, OR it may present snoop addresses one at a time serially – Access to system memory can be issued upon snoop-miss, or speculatively

before all snoop responses have arrived

– One example of such coherent interconnect is the ‘CCI -400 Interconnect’developed by ARM

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Different kinds of Components


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Interconnect: – CCI (Cache Coherent

Interconnect)

ACE Masters – Masters with Caches

ACE-Lite Masters – Components without caches

snooping other caches

Slaves – Components not initiating snoop

transactionsExample Cortex-A15 Coherent System

with CCI-400 Interconnect

Transaction Groups


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ACE introduces a large number of new transactions to AMBA4.

Non-Shared Transactions – These are the existing AXI read and write transactions – Used for non-coherent, non-snooped transactions

Non-Cached Transactions – ReadOnce – WriteUnique – WriteLineUnique

Cache Maintenance Transactions

– CleanShared – CleanInvalid – MakeInvalid

Shareable Read Transactions – ReadShared – ReadNotSharedDirty

Shareable Write Transactions – MakeUnique – ReadUnique – CleanUnique

Write-back Transactions – WriteBack – WriteClean – Evict

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Transaction Processing


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Initiating Master component issues a transactionDepending on whether coherency support is required, either: – The transaction is passed directly to a slave component – The transaction is passed to the coherency support logic within the

interconnect

Interconnect initiates the snoop transactions that are requiredEach cached master that receives a snoop transaction provides a snoopresponse.The interconnect determines whether a main memory access is requiredThe interconnect collates snoop responses and any required data

The initiating master completes the transaction

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Example: Load operation from Shareable Location


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Master Component issues a read transaction on Read-Address channelInterconnect determines whether any other cache holds a copy of thelocation, by Snooping: – i.e. It passes the shareable address to other caching masters that can hold a

copy, on the Snoop Address Channel – If any snooped master holds the requested cache line, then it:

• Responds on the snoop response channel• Provides the snoop-data to the interconnect on the snoop data channel

– If no snooped master component holds the requested cache line:• The interconnect initiates a transaction to main memory,• The read data is supplied back to the initiating master on the AXI Read Data

channel, as for standard transactions – The master component indicates that the transaction has completed, using the

RACK signal

Example: Store operation to a Shareable Location


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Initiating master component requests a unique copy of the cache-line byissuing a ‘MakeUnique’ transaction on the AXI Read Address Channel – Interconnect passes the transaction to other caches on the Snoop Address

Channel – Snooped masters respond on ‘Snoop Response Channel’ to indicate that the

cache line has been removed from their local caches – A response is provided to the initiating master, using AXI Read Data channel

(no data transfer occurs) – MakeUnique removes copies of the cache-lines from other Caching Masters

Initiating master performs the store using standard AXI write channelsInitiating master issues and RACK signal, to indicate that the transactionhas completed

Example: Transaction Execution Scenario


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Barrier Instructions


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ARM Architecture supports 2 types of Barrier Instructions: – DMB (Data Memory Barrier):

•

The DMB transaction can flow on the pipelined interconnect but no re-ordering is allowed about the DMB.• Ensures that all memory transactions prior to the barrier are visible by other masters• This prevents re-ordering about the DMB• Everything before the DMB must be complete before anything after the DMB• This was ensured by the ARM MPCore processor cluster• In ACE, the DMB Barriers may define a subset of masters that must be able to observe the barrier:

- This is indicated on the AxDOMAIN signals. These can indicate: Inner, Outer, System or Non-Shareable.

– DSB (Data Synchronization Barrier):• DSB is used to stall the processor until previous transactions have completed• Can be used for example to ensure data written to DMA command buffer in memory has reached its

destination before kicking off the DMA via a peripheral register• Is the most time-consuming barrier since it stops the processor until transactions are complete

A master issues a Barrier on both: Read Address Channel and Write Address channelsimultaneously using ARBAR and AWBAR signaling.

A barrier transaction has an address phase and response phase, but no data transfer occurs.Barriers enforce ordering because a master must not issue any read or write transactionuntil the master has received a response for the barrier on both: read and write channels

Types of Master Interfaces


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Full-ACE Master: – Contains all ACE Channels – Can issue snoop requests and can be snooped by interconnect – e.g. ARM Cortex A15 Processor cluster

ACE-Lite Master: – Does not include the AC, CR and CD channels – But has the additional coherency signals on existing AXI channels – Can issue Snoop requests but it itself cannot be snooped – E.g. a GPU or a Coherent I/O Device

ACE-Lite


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ACE-Lite is a subset of ACEEnables uncached masters to snoop ACE Coherent masters – e.g. An AXI Master interface like GigabitEthernet that shares data

with CPU can directly read/write cached data shared within the CPU.

ACE-Lite masters have additional signals on AXI Channels, but donot have the additional three ACE Snoop channels.


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ACE protocol does not guarantee Coherency! – ACE defines the hardware infrastructure required for Coherency

References


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AMBA® AXI™ and ACE™ Protocol Specification (Issue E, Date 22February 2013) – http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0022e/index.html

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0022e/index.htmlhttp://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0022e/index.htmlhttp://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0022e/index.htmlhttp://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0022e/index.htmlhttp://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0022e/index.html


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Thank You

Yashdeep Mahajani

[email protected]

Documents

AXI Overview