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Axel Jantsch1
NOCARCNetwork on Chip Architecture
KTH, VTT
Nokia, Ericsson, Spirea
TEKES, Vinnova
Axel Jantsch 2 20th Sept. 2002
Outline NoC Architecture overview Activities Switch Design
Buffer-lessHot-potato routingStress sensitive routing
Axel Jantsch 3 20th Sept. 2002
NoC Architecture Overview
Switch
Resource
•Message passing communication infrastructure
•Physical-Architectural Level design integration
Axel Jantsch 4 20th Sept. 2002
Resource-Network Interface
Resource
RNI
Axel Jantsch 5 20th Sept. 2002
Concept of Region
Resources larger than a slot
FPGA
Memory
Parallel processor
Wrapper will make the region transparent to outside traffic
Communication within a region could happen differently than rest of the network
Wrapper
Axel Jantsch 6 20th Sept. 2002
Quick Summary of Activities NoC Architecture Implementation
Physical feasibility study Buffer Less Switch Design
NoC Evaluation Ns-2 based NoC Simulator Dedicated simulator for NoC
Nostrum protocol stack 5-layered protocol stack
Two Phase Design Methodology Special Purpose NoC Region NoC Specific Fault Model and Error Protection NoC Specific Quasi-synchronous Clocking
Axel Jantsch 7 20th Sept. 2002
Buffer Less Switch
Switch
Packet
Packet
Packet
PacketPacket
Packet
Packet
Packet
Axel Jantsch 8 20th Sept. 2002
• Load information sent between switches, stress value1. no Stress value
2. with Stress value
3. averaged Stress value (four cycles)
• Better routing decisions for intermediate load
• Larger design
Load distribution using Stress values
Axel Jantsch 9 20th Sept. 2002
Final implementation
Axel Jantsch 10 20th Sept. 2002
Results of synthesis
constraint total combined logic critical path gate depth
optimised for area 13 964 79
optimised for speed 21 029 48
(using Synopsys)
Axel Jantsch 11 20th Sept. 2002
Maximum probability for various mesh sizes
Axel Jantsch 12 20th Sept. 2002
Network delay
Axel Jantsch 13 20th Sept. 2002
Number of packets in centre FIFO
p=0.47 p=0.48 p=0.49 p=0.50
Axel Jantsch 14 20th Sept. 2002
Average load in FIFOs with no Stress value
max=3.2
Axel Jantsch 15 20th Sept. 2002
Average load in FIFOs using Stress value
max=0.9
Axel Jantsch 16 20th Sept. 2002
Average load in FIFOs using averaged Stress value
max=0.15
Axel Jantsch 17 20th Sept. 2002
Comparing results
2115.0
2.3 times longer waiting time
max=3.2 max=0.9 max=0.15
Axel Jantsch 18 20th Sept. 2002
Conclusion
A buffer-less switch is feasible Very low cost and high performance Stress values is a simple control mechanism It increases maximum load by 20% It decreases the maximum latency by factor of 20
