Avalanche Breakdown Delay in ESD Protection Diodes

2470 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 10, OCTOBER 2010

Avalanche Breakdown Delay in ESDProtection Diodes

David Johnsson, Dionyz Pogany, Joost Willemen, Erich Gornik, and Matthias Stecher

Abstract—Electrostatic discharge (ESD) protection diodes witha breakdown (BD) voltage above 50 V might exhibit a BD delay inthe order of microseconds. The phenomenon is related to the lowgeneration of seed carriers that can start an avalanche BD event byimpact ionization. However, emission of carriers from deep traps,or the onset of tunneling generation, can shorten the delay to onlyfractions of a nanosecond. Emission from deep traps has beenfound strong enough to make this kind of device effective for pro-tection under standard ESD conditions. However, the applicationof a bias voltage prior to a stress pulse empties the trap states andthus leads to increasing BD delay. This paper investigates the BDdelay in an ESD protection diode under various bias and pulseconditions. A model for the BD delay is proposed, taking intoaccount the different seed carrier generation mechanisms. Theactivation energy of the dominating deep trap can be calculatedto 0.18 eV by measuring the time to BD at different temperatures.

Index Terms—Avalanche breakdown (BD) delay, electrostaticdischarge (ESD), trap emission.

I. INTRODUCTION

MANY electrostatic discharge (ESD) protection de-vices involve reverse-biased p-n junctions, whose

current–voltage (I–V ) characteristics increase abruptly at thebreakdown (BD) voltage due to the onset of the avalanchemultiplication process [1]. The most basic device is a pure p-ndiode conducting the ESD current in the BD regime, but it canalso be some transistor, or thyristor, where a junction BD is in-volved in the device triggering. For reliable operation in a short-pulse regime (pulse duration in the nanosecond–microsecondrange), it is important that the junction BD is initiated as soonas the BD voltage is exceeded. However, the delayed onsetof avalanche BD, with a resulting voltage overshoot, has beenreported in some works [2]–[4].

Avalanche BD delay is a well-known phenomenon, whosetheory has been thoroughly studied, mainly in relation toavalanche photodiodes [5]. It is related to the low number ofseed carriers in the depletion region (DR) that can undergo im-pact ionization and start the avalanche BD process. In avalanchephotodiodes, the number of seed carriers is so low that theprobability of spontaneous avalanche turn-on is practically

Manuscript received January 19, 2010; revised June 29, 2010; acceptedJuly 1, 2010. Date of publication August 23, 2010; date of current versionSeptember 22, 2010. This work was supported in part by the Austrian andGerman National Authorities. The review of this paper was arranged by EditorC. McAndrew.

D. Johnsson, J. Willemen, and M. Stecher are with Infineon TechnologiesAG, 85579 Munich, Germany (e-mail: [email protected]).

D. Pogany and E. Gornik are with the Institute for Solid State Electronics,Vienna University of Technology, 1040 Vienna, Austria.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2010.2058790

zero. Any incoming photon that generates a carrier can thusstart a detectable avalanche BD event. The seed carriers canalternatively be introduced by tunneling from the valence band[6], [7] or from carrier emission from trap states [6].

In [4], it was observed that the delayed BD can be causedby a bias voltage at the device prior to the arrival of a stresspulse. It has been suggested that the bias voltage empties deeptrap states in the avalanche region from carriers, which wouldotherwise help to initiate the BD event by carrier emission, butno detailed study has been given.

Protection devices that depend on trap emission for reliableavalanche initiation introduce a problem for circuits subjectedto dc bias prior to the arrival of ESD stress, e.g., for circuitswith applied operation voltage. Voltage bias might also be builtup during the ESD event itself from the displacement currentthat appears when a charged object approaches a circuit pin orthe traces of a printed circuit board [4], [8].

In this paper, the avalanche BD delay of an ESD protec-tion device is studied in detail in advanced Bipolar-CMOS-DMOS (BCD) technology devices. This technology includesbulk diodes for ESD protection in reverse mode in the 50-Vregime [9]. The low leakage current of these devices makesthem prone to BD delay effects. In particular, the effect ofbias voltage is systematically analyzed. A model is proposedfor the BD delay, taking into account the different seed carriergeneration mechanisms: midgap center generation (Shockley,Reed and Hall, SRH), electron tunneling, and trap emission.The latter mechanism is found to be the dominating initia-tion process under standard ESD conditions. The experimentalresults are supported by technology computer-aided design(TCAD) simulations.

The paper starts with an overview of the BD processeswith the purpose of giving the basic knowledge needed tounderstand the experimental results. Section III presents thestudied device and the methods used for characterization of theBD delay. Section IV presents experimental results and showshow the BD delay depends on dc and pulsed biasing and onambient temperature. Different carrier generation mechanismsinfluencing the avalanche BD initiation are discussed. The totalnumber of traps and their activation energy are determined.

II. MECHANISMS OF BD DELAY

When a p-n junction is driven above the BD voltage, impactionization can take place when free carriers in the DR gainenough kinetic energy to knock valence electrons out of theirbound states to create free electron/hole pairs. In a depleteddevice, the number of free carriers (seed carriers) in the DR is

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Fig. 1. Carrier generation by (a) SRH generation over a generation center and(b) electron tunneling at a high electric field.

low and governed by the carrier generation within the junction.Both the carrier generation and the BD initiation are stochasticprocesses, which leads to a mean time to BD according to [5]:

〈tBD〉 =q

PBDIgen(1)

where PBD is the probability for a single carrier to causeavalanche BD, Igen is the rate of carriers generated in the DR,and q is the magnitude of the electron charge. We considerthree different contributions to the generation current: 1) SRHgeneration (ISRH); 2) tunneling (Itun); and 3) emission fromtraps (Itrap), i.e.,

Igen = ISRH + Itun + Itrap. (2)

A. SRH Generation

In silicon material, electron emission directly from the va-lence band to the conduction band is rather unlikely because ofthe high-energy band gap (1.12 eV) and the associated changeof momentum. However, various defects with an energy levelclose to the middle of the band gap can act as a middle stepand reduce the carrier ionization energy to half of the bandgap. Thus, free electrons and holes can be generated, whichis commonly referred to as the SRH generation–recombinationprocess [see Fig. 1(a)]. In advanced smart power technologysilicon material, the number of defects is rather low, and thecontribution from SRH generation is thus very small at roomtemperature. The typical dark generation current of an ESDdevice lies in the range below picoamperes, which correspondsto less than one generated carrier per microsecond. The SRHgeneration alone is thus too small for reliable avalanche turn-on in the ESD regime.

B. Electron Tunneling

In a p-n junction subjected to a strong reverse bias, carrierscan be generated by band-to-band tunneling [see Fig. 1(b)].Tunneling in silicon takes place at a field strength of approx-imately 1 MV/cm, which is much higher than the onset ofimpact ionization (in typical BCD structures). However, inhighly doped p-n junctions, the DR width is shorter than themean free path of electrons, which lowers the probability ofimpact ionization. In such junctions, electron tunneling will

Fig. 2. Idealized band diagram of a p-n junction, showing an electron trapat Etrap, the equilibrium Fermi level EF , and the quasi-Fermi levels forholes (EFP) and electrons (EFN). Three different conditions are considered.(a) Zero-level bias. (b) Reverse bias with emitting traps. (c) Reverse bias atsteady state with empty traps.

dominate the BD process. In p-n junctions with a BD voltageof approximately 5.6 V, tunneling and avalanche multiplica-tion contribute equally to the BD current, and up to a BDvoltage of about 30 V tunneling still plays a significant role[10]. In devices where tunneling and avalanche BD take placesimultaneously, the tunneling introduces enough seed carriersto support a fast avalanche turn-on. However, in high-voltagedevices with VBD > 30 V (such as studied in this paper), thecontribution from tunneling is negligible near VBD, and thus,a BD delay might appear. However, in the case of delayed BDwhere the voltage continues to rise, the tunneling will start togenerate seed carriers at a certain onset voltage, which will setthe upper limit for the BD delay and voltage overshoot.

C. Trap Emission

In addition to the midgap centers, other impurities and de-fects can have their energy levels closer to one of the bandedges. These defects do not contribute significantly to the SRHgeneration current since the defect ionization energy to themore distant band edge is too large. Instead, they have theability to exchange carriers with the nearest band edge bycapture and emission processes, and are therefore referred to ascarrier traps. Here, we consider electron traps and the electronexchange with the conduction band.

Fig. 2(a) shows the energy band diagram for a p-n junctionat 0-V bias with an electron trap having an energy level in theupper half of the band gap. The trap is occupied in the part


where the trap is located below the electron quasi-Fermi level,which applies to the N-side of the junction.

If a reverse bias is suddenly applied to the p-n junction, a DRis formed in which the electron quasi-Fermi level approachesthe valence band, according to Fig. 2(b). The filled electrontraps in the DR are now located above the electron quasi-Fermilevel, and they will start to emit their carriers to the conductionband with an emission rate [11], [12]

en = σνnNCe−Eact

kT = k1T2e

−EactkT (3)

where T is the temperature, k is the Boltzmann constant, σ isthe capture cross section of the trap, νn is the average speedof the electrons, NC is the effective density of states in theconduction band, and Eact is the activation energy of the trap(see Fig. 2). The latter form includes a T 2 prefactor. Equation(3) is used to extract the trap activation energy and capture crosssection from the slope and intersection of an Arrhenius plot.

The carrier emission causes an exponentially decaying tran-sient current Itrap, which can be expressed as

Itrap = qNtene−ent (4)

where Nt is the initial number of occupied traps, and en is theemission rate of the specific trap. At the end of the emissionprocess, all the traps above the quasi-Fermi level in the DR areempty [see Fig. 2(c)].

Carriers emitted from traps can act as seed carriers for theavalanche BD process, as described in [6] and [13]. However,the ability for an emitted carrier to cause impact ionizationdepends on the position of the emitting trap in the DR. Underreverse bias, the emitted carriers from majority traps drift awayfrom the junction. Thus, carriers emitted near the junction willtravel the longest path through the high-field region and havethe highest probability to undergo impact ionization. The avail-ability of occupied trap states depends on the bias conditionbefore the device is driven into avalanche BD. If the junctionbias is at 0 V prior to a stress pulse [situation depicted inFig. 2(a)], a large number of trap states are occupied, and theavalanche BD can be triggered quickly. However, if the junctionis at some bias voltage prior to the pulse, the traps in the cor-responding DR have already emitted their carriers [Fig. 2(c)].Since the traps in the middle of the DR are most important, theapplication of a small bias voltage can dramatically reduce thetrigger probability.

III. DEVICE AND EXPERIMENTS

The studied device in this work is an avalanche BD diodemanufactured in a BCD process. The cross section of the deviceis shown in Fig. 3. Avalanche BD takes place at the junctionbetween the highly n-doped buried layer (cathode) and a deepp-diffusion (anode) at 50 V. The deep location of the p-njunction (4 μm) is favorable for heat dissipation and provideshigh ESD clamping robustness. In reverse bias, the thermalgeneration current (leakage current) in the device is slightlybelow 1 pA, which corresponds to about one generated carrierevery 200 ns on average. At a BD level of 50 V, the contribution

Fig. 3. Cross section of investigated device.

Fig. 4. Setup to produce a double-step pulse. The square-shaped pulse at theinput is split into two delay lines of different lengths and then combined toproduce the double-step pulse at the output.

from electron tunneling can be neglected, and thus, a BD delayof several hundreds of nanoseconds can be expected.

The BD behavior of the device is characterized by using atransmission line pulser (TLP) system capable of deliveringrectangular pulses with a rise time of 0.1 ns through a 50-Ωtransmission line. The measurement setup utilizes RF probes toachieve a system bandwidth of 5 GHz, which makes it possibleto resolve BD delays in the subnanosecond regime. To emulatethe effect of a static or a pulsed bias voltage, two different TLPsetup arrangements were used: To investigate the BD delaywithout trap emission, the TLP pulses are superimposed ona dc bias slightly below the BD voltage by using a bias tee.This empties most of the trap states within the avalanche zone[see Fig. 2(c)]. A detailed description of the setup can be foundin [4].

To apply prebias pulses with varying duration and amplitude,we use the setup shown in Fig. 4. This setup generates double-step pulses, where the first step represents the prebias pulseand the second step sets the device above VBD (see the insetof Fig. 4). Briefly, the pulse from the TLP system is split intotwo delay lines of different lengths and then combined to theoutput. The pulse through the shorter line arrives first, followedby the pulse through the longer line, which arrives Δx ∗ 5 ns/mlater. (Δx is the length difference in meters.) Series attenuatorsin the delay lines set the amplitude of the two different stepsand eliminate circulating pulses and reflections.

IV. RESULTS AND DISCUSSION

A. Determination of BD Probability

To determine the BD probability, it is necessary to workunder conditions with homogeneous carrier generation in theDR of the p-n junction and where carriers are equally generatedover time. The latter condition implies that the transient contri-bution due to trap emission is negligible. It is also advantageous


Fig. 5. BD delay at 10-pA generation current, and prebias of 40 V, measuredwith 200 pulses.

Fig. 6. BD probability as function of applied excess voltage over the BD level.Above-60-V excess voltage electron tunneling starts to contribute to the carriergeneration and causes the probability to exceed unity.

that the average BD delay lies well within the time windowof the measurement system. Typically at room temperature andin the dark, the averaged BD delay without trap emission (i.e.,with prebiasing close to VBD) is more than 1 μs, which exceedsthe maximum pulse width of the TLP system that was used.To achieve a homogeneous carrier generation over the junctionarea, the device was illuminated from the backside, using anordinary light bulb. With the light applied from the top, themetal contacts would prevent the light from reaching the middleregion of the device.

The variation of the light intensity allowed us to measure thedevice BD response in the range of photo-generated currents ofIgen = 5−200 pA. An example of the pulse voltage responseunder Igen = 10 pA recorded from 200 pulses is shown inFig. 5, giving the average BD delay of 48 ns. The averageBD delay follows an exponential distribution, which is due tothe Poisson nature of the carrier generation process, and 〈tBD〉scales linearly to 1/Igen over the measured range.

The probability that a single carrier initiates a BD event isobtained from (1). Voltage pulses above VBD were applied, andthe resulting BD probability as a function of the applied excessvoltage ΔV (i.e., voltage above the static VBD) is shown inFig. 6. The linear increase at moderate excess voltage agreeswell with the theory of McIntyre [5]. It can be related tothe faster acceleration of carriers in the higher electrical field,which increases the impact ionization probability. However, atan applied voltage above 110 V (i.e., for ΔV > 60 V), theprobability extracted from (1) rapidly increases above unity,

Fig. 7. BD delay at 10-pA generation current, with 0- and 5-V prebias,measured with 200 pulses. (a) 0-V prebias. (b) 5-V prebias.

Fig. 8. Average BD delay as function of the dc bias when a 70-V pulse isapplied to the device. The right axis shows the width of the DR at respectivebias value.

which is an obvious artefact due to the neglecting of the band-to-band tunneling in the carrier generation process. TCADsimulations of the device, with impact ionization switched off,confirms that tunneling starts to be noticeable beyond 100 V.

B. BD Delay With Carrier Emission From Traps

When an applied pulse starts from 0 V, the avalanche ini-tiation is almost immediate, with a delay well below 1 ns, asshown in Fig. 7(a). However, with increasing bias voltage, thedelay becomes noticeable, which is shown in Fig. 7(b) for a biasof 5 V.

The 〈tBD〉 shortening under low prebias conditions is directlyrelated to the carrier emission from the filled trap states in theavalanching region. Fig. 8 shows the average BD delay as a


Fig. 9. Two-step pulse applied to the device. The 26-ns-wide prebias steppartly empties the traps, which leads to delayed BD.

function of the applied dc bias with an applied pulse that bringsthe voltage up to 70 V. The right axis of the same plot showsthe width of the DR at a corresponding bias voltage, extractedfrom TCAD simulations of the device. The BD delay starts tobe noticeable when the bias exceeds 10 V and continues togrow until it saturates at 25-V bias. With applied prebias, thetraps in the corresponding DR become empty [see Fig. 2(c)].Hence, the higher the bias voltage, the smaller the amount ofcarriers that can be emitted from the remaining traps when theBD criterion is fulfilled. According to TCAD simulation, atthe applied pulse level of 70 V, the width of the region whereavalanche BD takes place (E > 0.2 MeV) is approximately1.7 μm wide. It follows that, when the width of the trap-depleted region approaches the avalanching width, no emittedcarriers can no longer contribute to the onset of avalanche BD.This leads to a purely SRH triggered BD, resulting in a BDdelay saturation that can be seen for biases above 25 V in Fig. 8.

C. Analysis With Double-Step Pulser

Fig. 9 shows a typical set of voltage transients obtained usingthe double-step pulser described in Section III. The first steptakes the device to a voltage slightly below the BD level for acertain time that we refer to as prebias time (tpb). The secondlevel takes the device above the BD level. Since the first levelbuilds up the DR, the traps within it start to emit their trappedcarriers. Neglecting the SRH and tunneling current componentsin (2) and taking (4) into account, the generation current at theend of the prebias pulse can be expressed as

Igen = qNtene−entpb . (5)

Then, by taking (1) into account and considering that Igen

does not decay too much during the BD delay time, the averageBD delay can be approximated by

〈tBD〉 =1

PBDNT ene−entpb. (6)

Equation (6) offers the possibility to determine en from theslope of the ln(1/〈tBD〉) versus tpb dependence. Furthermore,by using (3), trap parameters can be determined from thetemperature dependence of en(T ).

Fig. 10. Inverse of the BD delay 〈tBD〉 plotted logarithmic against the prebiastime (tpb). 1/〈tBD〉 is proportional to the electron emission from traps inthe DR.

Fig. 11. Arrhenius plot of ln(en/T 2) as a function of 1/T . The activation ofthe dominating trap is extracted from the curve slope multiplied with kB .

The measurement of 〈tBD〉 versus tpb was performed attemperatures ranging from −60 ◦C to +60 ◦C, with tpb variedfrom 5 to 40 ns. The result is plotted in Fig. 10 as ln(1/〈tBD〉)over tpb. The emission rate can be extracted from the slope ofthe curves, which was calculated by means of a minimum meansquare error linear fit.

The total number of traps (NT ) that contribute to theavalanche initiation can be determined from the curve intersec-tion with the vertical axis (i.e., at tpb = 0) according to

Nt =1

en〈tBD〉PBD. (7)

We estimate Nt ≈ 100 if PBD is assumed to be 0.3, asobtained from Fig. 6, at ΔV = 10 V.

The extracted emission rates versus temperature from Fig. 10are inserted in an Arrhenius plot (i.e., ln(en/T 2) versus1/T , see Fig. 11). The trap activation energy obtained fromthe slope of the dependence is Eact = 0.18 ± 0.01 eV. Suchan energy was obtained from the measurement on four de-vices. We suppose that the trap could be possibly an oxygen-related defect localized in the n-epi layer. Several authorshave reported on such a defect induced from implantation andirradiation [14], [15].

We would like to note that the very low measured trapnumber of NT = 100 shows that the double-pulse BD delaymeasurement technique is a very sensitive tool for trap parame-ter determination, compared to conventional capacitance tech-niques, such as deep-level transient spectroscopy (DLTS) [11].DLTS monitors the capacitance change in the junction when


the trapped carriers are emitted or directly the emitted chargetransients (charge-DLTS) [16]. The best sensitivity reported inDLTS is 104 electrons [17]. A DLTS analysis was performed onthe previously described device, but no indication of bulk trapswithin the detection limit was found, indicating a high purity ofthe epitaxial material and technology process.

V. CONCLUSION

We have shown that ESD protection devices with a BDvoltage above approximately 30 V depend on carrier emissionfrom deep trap states to facilitate a quick BD initiation. With apulse applied from 0 V, the BD was found to take place withina nanosecond, but with a dc bias voltage applied prior to thepulse, a BD delay up to the microsecond range was observed.This can be explained by the emptying of trap states withinthe DR in the biased condition. In the case without trap emis-sion, the time-to-BD was found to be inversely proportionalto the leakage current in the device, which could be variedby illumination. At an applied voltage above 100 V, however,the BD delay drastically decreased, which can be explainedby the contribution of seed carriers from the onset of electrontunneling.

The trap properties were determined by applying a bias pulseof various widths and monitoring the appearing BD delay. Withthis method, a trap with an activation energy of Eact = 0.18 eVwas found. This trap level has been reported in several worksas a typical oxygen-silicon complex that appears from siliconprocessing. The total number of emitting traps in the avalancheregion was found to be only about 100.

Emptying of trap states can be a serious problem for high-voltage p-n junctions used for ESD protection since ESD pulsesare not necessarily applied from 0-V bias. Prebiased conditionsappear when ESD pulses are applied in powered systems orwhen the ESD event itself charges the device nodes by displace-ment current when a charged object approaches [4]. On theother hand, the biasing issue is existent not only for p-n junctionBD but also for many dV/dt triggered protection devices thatare dependent on the voltage step at the beginning of an ESDevent [18].

In the case of a delayed BD initiation under ESD conditions,the voltage over the device will continue to rise until the BDis triggered by SRH-generated seed carriers or until electrontunneling introduces enough carriers to trigger the BD. Thus,a voltage overshoot takes place, whose duration and amplitudedepends on the rise time of the pulse and also has a statisticaldistribution. ESD pulses according to the HBM standard [19]are defined to have a rise time between 2 and 10 ns, butbecause of its current source property (large source resistance),the voltage can reach the tunneling level within fractions ofthat time in circuits with low capacitance. Such short voltageovershoots are not necessarily hazardous for all circuits, butpossible risks have to be carefully considered during circuitdesign and testing.

ACKNOWLEDGMENT

This paper was performed within the EU MEDEA+ ProjectSPOT-2 (2T205).

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[17] V. Nadazdy, private communication, 2009.[18] R. Ashton and E. Worley, “Pre pulse voltage in the human body model,”

in Proc. EOS/ESD Symp., 2006, pp. 326–334.[19] Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model

(HBM), JEDEC Standard JESD22-A114E, Jan. 2007.

David Johnsson received the M.Sc. degree in elec-trical engineering from the Royal Institute of Tech-nology, Stockholm, Sweden, in 2006.

In 2006, he joined Infineon Technologies AG,Munich, Germany, where worked on his Ph.D. the-sis in collaboration with the Institute for SolidState Electronics, Vienna University of Technology,Vienna, Austria. In 2010, he joined the ESD ConceptDevelopment Group, Infineon Technologies, wherehe is currently working on system-level electrostaticdischarge (ESD) topics. His field of research was

system-level ESD protection in high voltage automotive technologies. He alsospecialized on transient device analysis and constructed state of the art pulsecharacterization systems.


Dionyz Pogany received the Dipl.-Ing. degree insolid-state engineering from Slovak Technical Uni-versity, Bratislava, Slovakia, in 1987 and the Ph.D.degree from the Institut National des Sciences Ap-pliquées de Lyon, Villeurbanne, France, in 1994.

From 1994 to 1995, he was a Postdoc withFrance Telecom, CNET-Grenoble, Grenoble, France.Since 1995, he has been with the Institute of SolidState Electronics, Vienna University of Technology,Vienna, Austria, where he currently leads a researchteam and has been an Associate Professor since

2003. He published on defect states in semiconductors, low-frequency noise,and device reliability physics. His current research interests include electro-static discharge (ESD) phenomena, self-heating effects, thermal modeling,current filamentation, breakdown phenomena, power electronics, GaN highelectron mobility transistors and light-emitting diodes, failure analysis, devicereliability, and development of new optical methods for device characterization.He is the author or coauthor of more than 230 scientific papers.

Joost Willemen received the Master’s and Ph.D.degrees in electrical engineering from DIMES In-stitute, Delft University of Technology, Delft, TheNetherlands, in 1993 and 1998, respectively.

In 1998, he joined the Automotive Electron-ics Division, Robert Bosch GmbH, Reutlingen,Germany, where he developed methodologies forhuman body model and conventional delay modelcircuit-level simulation, high-current electrostaticdischarge (ESD) device models, and a simulationenvironment for fully coupled electrothermal circuit

simulations. In 2005, he joined Smart Power Technology R&D, InfineonTechnologies AG, Munich, Germany. His main tasks are the development ofESD concepts and devices for automotive applications and ESD consultancyfor automotive IC design. His research interests are the physics of ESD devicesand advanced ESD characterization methods.

Erich Gornik was born in Krumau, Czech Repub-lic, in 1944. He received the Diploma degree inphysics, the Ph.D. degree, and the Venia Docendifor “physical electronics” from Vienna Universityof Technology, Vienna, Austria, in 1968, 1972, and1976, respectively.

From 1975 to 1977, he was a Postdoctoral Fellowwith Bell Laboratories, Holmdel, NJ. In 1978, he re-turned to Vienna University of Technology, where hebecame a University Professor with the Institute forPhysical Electronics. In 1979, he was appointed Full

Professor for experimental physics at the University of Innsbruck, Innsbruck,Austria. From 1988 to 1993, he was a Full Professor (C4) of semiconductorphysics and the Director of the Walter Schottky Institute, Technical UniversityMunich, Munich, Germany. Since 1993, he has been a Full Professor ofsemiconductor electronics with the Institute for Solid State Electronics, ViennaUniversity of Technology. He has spent several research professorships atnumerous international research institutions.

Dr. Gornik was nominated Fellow of the American Physical Society in 1995.From 2003 to 2008, he was the President of the society “Forschung Austria”and Managing Director of the Austrian Research Centers. He was the recipientof the Wittgenstein Price of the Austrian Government in 1997.

Matthias Stecher received the Dipl.-Ing. andPh.D. degrees in electrical and electronic engi-neering from Rheinisch-Westfälische TechnischeHochschule Aachen, Aachen, Germany, in 1989 and1995, respectively.

He was a Visiting Student with Virginia Polytech-nic Institute and State University, Blacksburg, forone year. Between 1989 and 1994, he was involvedin the development of device and circuit simulationtools. In 1994, he joined Infineon Technologies AG,Munich, Germany, where he has been the Project

Manager for several Smart Power Technologies. Since 2003, he has beeninvolved in the thermomechanical optimization of chip-package systems. Cur-rently, he holds the position of a Senior Technical Advisor in the fields of powertechnology and package development. He is the holder of more than 20 patents.

Documents

Avalanche Breakdown Delay in ESD Protection Diodes