Automatic VHDL Model Generation of Parameterized FIR Filtersglossner.org/john/papers/samos_2002_presentation.pdf · FIR filter architecture: 4th stage, final addition. Filter Generation

Automatic VHDL Model Generation of

Parameterized FIR Filters

E. George Walters III1, John Glossner2,and Michael J. Schulte1

1Computer Architecture and Arithmetic LaboratoryComputer Science and Engineering Department

Lehigh UniversityBethlehem, PA 18015 USA

2Sandbridge Technologies1 North Lexington Ave, 10th Floor

White Plains, NY 10601 USA

Outline

• Background• FIR filter architecture• Filter generation software• Results and conclusions

Two’s Complement MultipliersA

x B1

1

multiplier

partial product

product

bit matrix

multiplicand

n

2n

6 x 6 parallel tree multiplier (two’s complement)

Truncated MultipliersA

x B

not formed

1

1

product

multiplier

multiplicand

rkn

6 x 6 truncated multiplier


x B

1

1

1 1 0 0 0 1

expectedvalue

n k r

Correcting for average reduction error


x B

1

1

1 correction constant

valueexpected

n k r

Rounding the correction constant

Truncated Multiplier Errors

• Two sources of error– Reduction error– Roundoff error– Roundoff error often dominates

• Average reduction error is not zero

FIR Filters

∑−

=

−⋅=1

0][][][

T

kknxibny

– x[ ] is the input– y[ ] is the output– T is the number of taps– b[ ] are the tap coefficients

Operand Bus 1 Operand Bus 'M'

Taps

Input Data

b[0] b[T-2] b[T-1]

x[n] x[n-1] x[n-T+1]

Register Register Register Register n bits

FIR filter architecture: 1st stage, operand selection


Multiplier 1

Register

Multiplier 'M'

Register

Taps

Input Data

b[0] b[T-2] b[T-1]

x[n] x[n-1] x[n-T+1]

Register Register Register Register

n + k bits

n bits

FIR filter architecture: 2nd stage, multiplication


Multiplier 1

Register

Multiplier 'M'

RegisterAccumulator

Multi-Operand Adder

Register

Taps

Input Data

b[0] b[T-2] b[T-1]

x[n] x[n-1] x[n-T+1]

Register Register Register Register

n + k bits

n + k bits

n bits

FIR filter architecture: 3rd stage, summation


Multiplier 1

Register

Multiplier 'M'

RegisterAccumulator

Multi-Operand Adder

Register

Final Adder

Output Register

Correction Constant

Taps

Input Data

Output Data

b[0] b[T-2] b[T-1]

x[n] x[n-1] x[n-T+1]

Register Register Register Register n bits

n + k bits

n + k bits

n bits

FIR filter architecture: 4th stage, final addition

Filter Generation Software

• VHDL generation• Test bench generation• Synthesis script generation• Bit level simulation

ReducedAreaReductionTree

RippleCarryAdder

CarryPropagateAdder

WallaceReductionTree

CarryLookaheadAdder

ParallelMultiplier

BitMatrix ReductionTree

DaddaReductionTree

FIRFilter

Partial class diagram of the Filter Generation Software

Class <<Interface>>Abstract Class

Bit

BitMatrix

HDLFile

StdLogicVector

Util

arithmeticVHDLGenerator

<<Parameterized>>

<<Simulator>>

Object

java.lang

extends implements

The arithmetic package


CLALookaheadLogic

D_FF

FullAdder

HalfAdder

ReducedFullAdder

arithmetic.smallcomponents

VHDLGenerator <<Parameterized>>Object

java.lang

extends implements

SpecialHalfAdder

arithmetic

The arithmetic.smallcomponents package


Summer

CarryPropagateAdder

CarryLookaheadAdder

RippleCarryAdder

arithmetic.adders


java.lang

extends implements

SpecialCarrySaveAdder

arithmetic <<Simulator>>

The arithmetic.adders package


ReducedAreaReductionTree

WallaceReductionTree

arithmetic.matrixreductionReductionTreeObject

java.lang

extends implements

DaddaReductionTree

The arithmetic.matrixreduction package


ParallelMultiplier

arithmetic.multipliers


java.lang

extends implements


The arithmetic.multipliers package


Bus

Register

arithmetic.misccomponents


java.lang

extends implements

arithmetic

The arithmetic.misccomponents package


IdealFIRFilter

arithmetic.firfilters


java.lang

extends implements


FIRFilter

FIRControl

The arithmetic.firfilters package


TestFIRFilter

arithmetic.testingObject

java.lang

extends implements

TestParallelMultiplier

The arithmetic.testing package


FIRControlPanel

BusPanel

arithmetic.guiComponentPanelJPanel

javax.swing

extends implements

CarryLookaheadPanel

FIRFilterPanel

ParallelMultiplierPanel

RegisterPanel

RippleCarryAdderPanel

SpecialCarrySaveAdderPanel

SummerPanel

<<RadioButtonGroupUser>>

Graph

RadioButtonGroup

The arithmetic.gui package

Area Results

00.10.20.30.40.50.60.70.80.9

1

8-Bit Operands 12-Bit Operands 16-Bit Operands

12 Tap Filters with 4 Multipliers (normalized within each group)

standard multipliersk = 4k = 3k = 2k = 1k = 0

Error Results

0

1

2

3

4

5

6

ulps

8-Bit Operands 12-Bit Operands 16-Bit Operands

Standard deviation of error, 12 Tap Filters

k = 6

k = 5

k = 4

k = 3

k = 2

k = 1

k = 0

Conclusions

• Studied use of truncated multipliers in FIR filters• Area is significantly reduced• Error is tolerable for many applications• Average error is significantly reduced

Average Reduction Error22

_ 22)1( −− +•−−= ravgr rE

• Ex: 12 unformed columns, 1 multiplier– 1011000000000001 (correction constant)– 11-------------- (rounded)

• Ex: 12 unformed columns, 4 taps– 101100000000000100 (4 * correction constant)– 1011--------------

Tree Multipliers

p0p1p2p3p4p5p6p7p8p9p10p11

a0b5a1b5a2b5a3b5a4b5a5b5






b0b1b2b3b4b5GB

a0a1a2a3a4a5A

6 x 6 partial product bit matrix

Parallel Tree Multipliers

Ax B

multiplicand

multiplier

partial product

product

bit matrix

6 x 6 parallel tree multiplier (unsigned)

Ax B

1

1

partial productbit matrix

1st reduction stage

2nd reduction stage

final reduction stage

product

multiplicand

multiplier

Reduced area reduction for 6 x6 multiplier


x B

1

1

1

Bx1

A

Truncated multiplier reduction tree vs. standard multiplier


x B

1

1

1

keep discard

round

Rounding truncated multiplier to 6 bits

Error Results

0

20

40

60

80

100

120

SNR

12 taps 24 taps 36 taps 48 taps

Reduction error SNR, 16-bit operands

r = 10

r = 11

r = 12

r = 13

r = 14

r = 15

r = 16

Results and Conclusions

0

0.2

0.4

0.6

0.8

1

12 16 20 24

Number of Taps

Area-Delay Product, 4 Multipliers, 16-Bit Operands

r = 0r = 12r = 16

Unformed Columns

Documents

Automatic VHDL Model Generation of Parameterized FIR Filtersglossner.org/john/papers/samos_2002_presentation.pdf · FIR filter architecture: 4th stage, final addition. Filter Generation