Automatic Layout Synthesis for FIR Filters Using a Silicon Compiler

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Automatic L ayout Synthesis for FIR FiltersUsing a Sil icon CompilerMasaki ISHIJSAWA, Masato EDAHIRO,Takeshi YOSHIMURA,Takashi MIYAZAKI,Shin-ichi AIKOHt, Takao NISHITANI, KaoruMJ TSUHASHIi, MitsuhiroFURUICHI':C&C Systems Research Laboratories, tR&D Planning and Technical Service Division,

$SystemLSI Development Division,NEC Corporation4-1-1, Miyazaki, Miyamae-ku. Kawasaki 213, JAPAN

AbstractA silicon compiler for FIR filters is presented. Unlike ex-isting silicon compilersfordesigning Digita Signa Processor(DSP)chips, which need descriptions for signa processing al-gorithms as inputs, the synthesis systemtakes as inputs onlyfilter specificationsand processing word lengths, and gener-ates theFI R filter mask pattems ina few mnutes. The systemconsistsof twoprograms: an FIR filter design programtode-termne FIR filter coefficients at the mnima filter order tomeet design objectives and a module generator to generatemask pattems, according to optima parameters obtaned bythe filter design program For describing layout structurescorrectly and easily, the module generator provides graphicalayout description tools and includes mechanisms to permtdesigning thestructures before leaf-cels are completed. Lay-

outs for severa filters have been successfully generated in ashorttime. A single chipVLSI chromnance/lumnance sep-arator forNTSC compositeTV signas employing four FIRfilters generated by the systemis shown.

1 IntroductionWith the increase in the complexity and density in V U 1 chips,the design costs for the development of a VLSI chip have beenrapidly increasing. System designers, who are generally inexperi-enced in IC design and processing technology, now need to design

VLSI chips, because whole systems can be realized on a single chip.Tosolve theVLSI design crisis and allow system designers to designVLSI chips, silicon compilers have become attractive.Many silicon compilers using different approaches have beenproposed in the past decade[l][2]. These systems can be classifiedinto the followingtwogroups:Silicon compilers for general architectures.Silicon compilers for target architectures.

Silicon compilers for general architectures, which usually havehigh-level description languages and consist of a high-level syn-thesizer, a logic synthesizer and an automatic layout system, cangenerate various layouts from high-level descriptions. However, theperformance, such as size and operation speed of synthesized chips,isoften much worse than that achieved by manually designed chips.On the other hand, silicon compilers for target architectures areexpected to generate efficient layouts, although the chip architecture.is restricted. So far, several silicon compilers for designing DigitalSignal Processor(DSP) chips have been proposed[3]-[7]. S'memany

of the systems require descriptions for signal processing algorithms,chipdesigners need to write the descriptions in special high-levellanguages.

Thispaper presents a silicon compiler for FIR filters, whicharecommonly included in fast video signal processors as a special hard-ware. In this system, the inputs are the system-level specifications.Since the abstraction for the chip design reaches a higher level,the algorithm descriptions become unnecessary, and therefore, thechips are easier to design and can be designed in a shorter periodof time. The system starts from system-level specifications, such asfilter specifications, coefficient word lengths, etc., and generates theFIR filter mask pattems in a few mnutes. The following sectionsexplain the system configuration andtwo major programs in the sys-tem: an FIR filter design program and a module generator. Finally,layout results and a mcro-photograph of the developedVLSI chipare presented.

2 System ConfigurationThe proposed system consists of two major programs: an FIRfilter design program and a module generator. The system configura-tion and data flow are shown in Fig.1. The input data for designingan FIR filter are only filter specifications and word lengths for thefilter, as follows:

Filter types.Filter mecifications.Word lengths.IFIR filter design program7.

rchitecture.F ilter coefficients.F ilter order.

[Mask patternFig. 1 System configuration

CH2868-8/90/0000-2588$1,@1990IEEE


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Filter types: low-pass, high-pass, band-pass, band-stop andmulti-bandFilter specifications: cut-off frequency, pass-band ripple, stop-band attenuation, etc.Word lengths: input, output, intemal and coefficient

The FIR filter design program starts with these data, accom-plishes an optimal design and generates the following parametersfor layout design by using the module generator.Filter architectures and specificationsFilter order

o Filter coefficientsThe module generator generates mask patterns for theFIR filters,according to the parameters described above. The module generatorhas several layout structures for FIR filters in the database. The

FI R filter design program selects a layout structure for optimal filterdesign, and the generator makes mask pattems, by using the layoutstructure.

3 FIR filter design programThe FIR filter design program automatically designs FIR filtercoefficients at a mnimal filter order by using the McClellan et al.algorithm based on the Remez Exchange Algorithm[8][9]. The de-sign is canied out according to input data, suchascut-off frequency,passband ripple, stop-band attenuation, coefficient word length, etc.This program makes it possibletodesign optimal FIR filters withoutmuch expertise.Several initial values for the Remez Exchange Algorithm aredetermned automatically according to the input data, because it isdifficult for inexperienced filter designers to set suitableinitialvalues.First, FIR filter coefficients are calculated by using the algorithm. Ifthe coefficients do not satisfy the desired filter specifications, thefilter order is increased and coefficientsarecalculated again. If thecoefficients satisfy the specifications, the coefficients are rounded

off to given word length(e.g. 8 bits) and checked again to determnewhether the desired specifications are satisfied by those values. Ifthe rounded off values satisfy the specifications, those coefficientsand filter order are derivedasparameters for layout generation, usinga module generator.When coefficients are rounded off, the Canonical Signed-digitRepresentation (CSR) is used to decrease non-zero digits. CSR canrepresent any N-bit number with less than or equal toN/2+1non-zerodigits by allowing 0, 1 and -1weights to each digit. For example,127 and -73 n decimal form can be represented in 8digit CSRby 1000000~nd O ~ O O l O O ~espectively, although they are ex-pressed as 01111111 and 10110111 in 8bit binary code. Here,rmeans -1 weighting in CSR.Decreasing non-zero digits by the CSR results in reducing thenumber of shift and add operations for a multiplication. In the filterdesign for the chromnance/lumnance separator chip, limting themaximum numbers of non-zero digits to3for 8-bit fixed coefficients,each multiplier used in the filter can be simply realized by three shiftand add operations using three adders, inverters and/or selectors.This simplified and regular structure is effective in layout designusing a module generator.Figure2shows coefficients representation on a filter layout. Co-efficients in CSR are ultimately represented with wired logics onlayout.

I

( jGz&)

( Example )-36

II+11011100

100~00lp0Fig. 2 Representation of coefficients

4 Layout generation by a module generatorThe proposed module generator can accomplish placement ofleaf-cells and routing between the cells, according to layout descrip-tions for the target functional moddes[lO]. Inaddition to these basicfunctions, the generatorhas the followingtwofeatures for describing

layout structure.J . Layout description with graphical interface and C language2. Layout description with temporary cellsIndividual features for the layout description aTe discussed indetail in the following sections.

4.1 L ayout descriptionwith a graphical interface andC languageLayout structures can be described by the following two methods:1. C language2. Graphical interfaceMore than 50 functions in C language, called layout functions,are prepared to describe the layout st~~ctures.ayout functi ons in-clude functions not only for absolute/relative cell placement, but alsofor making a netlist for automatic routers. Using these functions andcontrol statements in C, such as for, ifthen, case, etc., anylayout structures can be described.Since cells have various sizes and termnal positions in practicallayout designs, it is quite difficult to describe legal topological rela-tionships among cells on texts. In addition, layout descriptions axeoften error-prone. Todescribe correct layout structures easily, graph-ical tools to draw the layout structure are provided. Using commandson the graphic display, various relationships betweencellswtharbi-traq sizes and termnal positions can be described. Each commandassures legal relationships between two cells. Layout structures canbe checked visually and layouts can be modified easily on the graphicdisplay.Figure3 shows the system configuration for the proposed mod-ule generator. As described above, layout descriptions can be madeby using a graphical interface. These graphic layout descriptionsare transformed into intermediate forms automatically. The layoutdescription environment is set up from the intermediate forms, byusing a command sequence generation program. The intermediateforms, which have been made previously and stored inthe database,

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canbeused to make a new layout structure on the graphic display.The intermediate forms are interpreted to layout descriptions n Clanguage, by using layout functions. Thedescriptions can be mod-ified in the C language, if necessary. Moreover, t is effective todescribe logical information, such as ROM pattems, PLA pattems,etc., directly intheC language, which is difficult to berepresentedongraphics. Parameten can be set at any stageon the module design,as shown in Fig.3.Figure4shows an example of layout descriptions on graphicdisplays. Parameters and temporary values for them can be set onpanels, as showninthe figure. Layout structuresaremade by usingtheseparameters.

Layout generator

, *(Graphical ........................interface

........................

&&ntermediate formssequence gen. 1 generator

Fig. 4Layout structure descriptions using a graphical nterface

4.2 L ayout description with temporary cellsMany existing cell-based module generators assume that leaf-cells are prepared or generated before making the layout descriptions.Inactual chip designs, however, leaf-cellsareoftencompleted after

the layout descriptionsaremade. I n this case, it is necessary todescribe layout structures using temporary leaf-cells: the size andterminal positions of temporary cells may be changed. Moreover,many of the leaf-cells n the modulesare sometimesreplaced in thesame ayout structure, when the parameters are changed. It is difficultto describe such layout structures with a usual layout descriptionlanguage.

In the proposed generator, layout structures can be describedusing temporary cells, and after the actual cells are designed, maskpattems are generated, by using actual cells as follows (shown inFig.5):Design temporary cellsongraphics.Describe layout structures with temporary cells. Note thatthe layout structures should be described, by using relative-placement commands (or functions) for leaf-cells, since thesize of the temporary cells is not equal to the correspondingactual cells.Make case files, which represent the correspondencebetweentemporary cells and actual cells.After completing the actual cell design, choose a case fileandgenerate themask patterns.

Several mask patterns with actual cells can be generated, accord-ing to the relationship between temporary cells and actual cells onthe case file. - ata flowOperation flow

Describe layout structurewith temporary cellsr..l.;l-.-yca you t description , ,Map temporary\ I to actual cells cells I

CASE-1

Fig. 5 Layout generation with temporary cells

5 ResultsThreekinds of FI Rfilters have been designed using the system,asshown inTable1.Structures for these filters fall into two categories:one is for the symmetric coefficientFIR filter and the other is forFIR decimation filters. A band-pass filter for color signals, calledCBPF, has been designedwith the symmetric coefficientFIR filterstructure, and two low-pass filters for color signals and a low-passfilter for luminance signals, called CLPFs and YLPF respectively,

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have been designed with the FIR decimation structure. Decimationrates for the CLPFs and the YLPF are 1/4 and 1/2, respectively. Theentire filter design process takes from200to400seconds on an NECEWS4800 workstation (3.2 Mips), depending on the filter order forthe filter.The basic layout structures, which consist of leaf-cells, such asinverters, adders, selectors, flip-flops, etc., were designed, by usinga graphical interface with temporary cells described in the previ-ous section. Filter coefficients are represented with wired logic onlayouts. Layout structures for basic structures and the wired logicwere written in C language, and stored in a database in a parameterexpansible format.By using the system, fast and error-free VLSI development wasrealized. Figure 6 indicates the layout produced for a CLPF. Figure7 is a mcro-photograph of chromnance/lumnance separation VLSI

CLPF LPF for color signalsYLPF LPF for lumnance signalsCBPF BPF for color signals

Table 1 Produced FIR filters1 Name 11 Function I Fil. ord. I *DR 1 Num.1

15 114 219 1/2 115 1 1*Decimation Rate

Fig. 6 Produced layout (CLPF)

Fig. 7 Chromnance/lumnance separator chip mcro-photogragh

chip for NTSC compositeTV signals at 13.5 MHz CCIR standardsampling rate. Four FIR filters, which are major functional mod-ules in the chip, were designed, using the system. The VLSI chipwas fabricated n 10.4 x 11.7 die size, using 1.2pm CMOStechnology, and achieves about 860 MOPS (Million Operations PerSecond) operation speed.

6 ConclusionA silicon compiler for FIR filters and a chrominance/ uminanceseparation VLSI chip, employing four FIR filters generated by thesynthesis system, have been presented. Starting&om filter specifi-cations, such as cut-off frequency, pass-band ripple, stop-band atten-uation and coefficient word length, the synthesis system generatesoptimal filter mask pattems correctly in a short time. The modulegenerator, which accomplishes ayout design in the system, providesgraphical ayout description tools and includes mechanisms to per-mt describing ayout structures before leaf-cells are completed. Thesynthesis system can be used by system designers who are inex-perienced in filter design and LSI chip design, because the systemrequires only filter specifications and processing word lengths togenerate the target filter.

AcknowledrrmentsThe authors would like to thank T. Ishiguro,A. Morino, S. Goto,K. Watanabe, B. Hirosaki,Y. Nagai, H. Nakamura and M. Hrata fortheir continuous encouragement and valuable suggestions.

ReferencesD. Gajiski, Silicon compilation, Addison Wesley, 1987.G. De Micheli, et al., Design Systems for VLSI Circuits:Logic Synthesis and Silicon Compilation,Martinus Nijhoff,1987.P. Denyer, et a ., A Silicon Compiler forVLSI Signal Pro-cessors, Proc. ESSCIRC 82, pp. 215-218, 1982.M. Glesner, et a., A Flexible Silicon Compiler forDigi-tal Signal Processing Circuits, Proc ICCD84, pp. 845-850,1984.H. De Man, et al., Cathedral-D. A Silicon Compiler forDigital Signal Processing, IEEE Design& Test, pp. 13-25,Dec. 1986.J. Rabaey, et al., An Integrated Automated Layout Genera-tion System for DSP Circuits, IEEE Trans. CADDCAS,vol.CAD-4, no. 3, pp. 285-296, 1985.J. Schuck, et a., The ALGIC Silicon Compiler System:Implementation, Design Experience and Results, Proc. 24thT.Miyazaki,et al., A Single Chip Chromnance/ LumnanceSeparator Based on a Si licon Compiler, Proc. ICASSP89,1989.J. McClellan, et a., A Computer Program for DesigningOptumum FIR Linear Phase Digital Filters, IEEE Trans.Audio Electroacoustics, AU-21-6, 1973.M. Ishikawa, et al., A New Module Generator with Struc-tural Routers and Graphical Interface, Proc. ICCAD87, pp.436439, 1987.

DAC, pp. 370-375, 1987.

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Automatic Layout Synthesis for FIR Filters Using a Silicon Compiler