www.t-vec.com

Automated Test Generation and Execution for Simulink

SIMULINK TESTER OVERVIEWT-VEC

Traditional Software Testing is CostlySoftware is an inherent part of many products, andits ever-growing complexity is increasing the cost ofproduct development. Although many tools sup-port software system design and implementation,few support verification, validation, and testingwhich accounts for 40% to 70% of developmenteffort. Software verification and testing in manyorganizations is a manual process. It is inefficientand relies on testers' experience and judgment tofind problems hidden throughout the system.

A Comprehensive ApproachT-VEC's Test Generation System for Simulink(Simulink Tester) provides an integrated solution forcontinuous model analysis, automatic test generation,test execution and results analysis. It analyzes everypath throughout the model hierarchy and generatestest vectors that exercise the path boundaries.Unreachable paths which result in dead code are iden-tified and hyperlinked to the Simulink model elementsinvolved. This test selection process produces unit,integration and systems test vectors most effective inrevealing both decision and computational errors inlogical, integer and floating-point domains.

Significant BenefitsT-VEC customers report savings between 40% and60% of their development budgets while reducing testschedule by up to 90%. T-VEC solutions help productdevelopment teams integrate modeling with modelanalysis, and automated testing to eliminate labor-intensive, manual processes that cannot find bugs incomplex systems.

Test design is the most labor-intensiveand time-consuming testing activityconsuming 60% of test effort.

Simulink Tester Features:Systematic, comprehensive test generation fromSimulink modelsUnit, integration and system level testsTest sequences for testing dynamic systemsModel defect identificationTest drivers for any platformSimulation data for model validationMeasurement and status reports for trackingproject statusUnrivaled test coverage:

Path CoverageDecision CoverageCondition Coverage (MC/DC)Complete Hierarchy CoverageInput Range StressingBoundary Value Stressing

The Benefits:Considerable competitive advantages fromreduced schedule and costsIncreased quality and reliabilityEnhanced test coverageEarly defect identificationReduced risk to budgets and schedulesMeasurable project status, defects, and test coverage Testable modelsReduced evolution and maintenance costs

Mature and TrustedT-VEC has developed and refined the tools underly-ing the Simulink Tester for more than a decade tomeet the needs of complex, mission-critical aircraftsoftware systems. These tools have been used in soft-ware certifications with authorities such as the FAAand FDA. Although the roots of the technology weredeveloped to meet the needs of ultra high assurancesystems, T-VEC tools improve software quality inany industry's products whether embedded systems,information systems, or otherwise.

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Model Analysis and Test AutomationProject engineers use Simulink to model the soft-ware system and typically validate the modelthrough simulation. Source code is then generatedautomatically from the model or developed manu-ally. To test implementations of the model or gen-erate simulation data, the engineer uses theSimulink Tester Graphical User Interface fromwithin MATLAB to:

Configure options for test generationAdd signal range informationOptionally configure test sequence generationTranslate Simulink model to T-VEC

Within the T-VEC Test Vector Generation System,the engineer then:

Analyzes model for defectsGenerates test vectorsGenerates test driversExecutes tests against code or within SimulinkGenerates test results report

The Simulink Tester creates T-VEC test specifica-tions from Simulink models, then analyzes the testspecifications to generate an optimal set of testvectors. During this process T-VEC identifiesmodel errors, such as contradictions or inconsis-tencies, which can result in unachievable condi-tions or other undesirable properties. Testsequence vectors support verifying dynamicaspects of the system. Test driver generation trans-forms the test vectors from a generic format intotest harnesses compatible with the code generatedby the Real-time Workshop GRT and ERT codegenerators. These test harnesses are compiled inthe same environment as the source code to gener-ate a test program. This test program is executed inconjunction with the source code in the targetenvironment. When the test driver executes, theresults of each test are stored for comparison withthe expected results. Finally, T-VEC tools compareactual test outputs to expected outputs to verifythat the code implementation satisfies the model.

SIMULINK TESTER OVERVIEWT-VEC

www.t-vec.com

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We cover all boundaries of your software™

T-VEC Technologies, Inc.2214 Rock Hill RoadHerndon, Virginia 20170-4227www.t-vec.com703.742.7100

Model CaptureModel SimulationCode Generation

Subsystem SelectionTranslation OptionsSignal Range Data

Model AnalysisTest Generation

Coverage AnalysisTest Driver Generation

Minimum System RequirementsMATLAB R13, Simulink, RTWIBM PC or 100% compatible1 GHz processor and 256MB RAMMicrosoft Windows NT 4.0 SP3, 2000, XP