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Atomic Level Precision Materials Engineering
Peter Loewenhardt, Terry S Lee, Jun-Chieh Wang , Leonid Dorf, Shahid Rauf, Amulya Athyde
Applied Materials
Mobility’s Implications for Semiconductor Equipment
2
THEN NOW
Litho-enabled 2D transistor Materials-enabled 3D transistor
Litho-enabled 2D NAND Materials-enabled 3D NAND
Conventional processes Selective material processes
Bulk dominates Interface engineering increasingly critical
Standalone tool Integrated processes on same tool
3
Performance improvement is not about scaling… At 28 nm, 90% of the performance gains come from materials and device architecture innovation
SOURCE: ARM, IBM, IC INSIGHTS
Era of Precision Materials Engineering
4
NEW MATERIALS will be the driver of technology migrations in advanced nodes
2X INCREASE IN NEW MATERIALS
5
Mobility and Connectivity Drive Performance Gains
Increasing Functionality Driving the Biggest Semiconductor Inflections in Decades
Speech Recognition Gesture Sensor Mobile Payment Ultra Power
Saving Mode
Video Chat Finger Print ID Facial Recognition
Wireless Charging
45nm 32 / 28nm 20nm 14nm High-k Metal
Gate n-MOS Epi FinFET
0.3 | 6 GB 0.8 | 13 GB 1.5 | 21 GB 2.2 | 23 GB *
FEATURES
AND
FUNCTIONS
INFLECTIONS
2010 – 2011 2012 – 2013 2014 2015F
Sources: Gartner * Average Mobile DRAM and NAND Content Per Unit of Premium Smartphone
3D Inflections Driving ALD Market Growth
3D FinFET Tighter thickness/conformality control Decreasing thermal budgets
3D NAND Higher aspect ratios Vertical, electrical grade films
3D Inflections Driving new Materials High-Performance ALD required
ATOMIC LAYER DEPOSITION (ALD)
ALD Has Become an Industry Norm However many Practical Challenges:
•Thermal budget (getting lower and lower . . .)
•Increased quality of films
•Monolayer engineering for high performance
•Incompatible chemistries
•Stringent and ever tightening low defect requirements
•Productivity: maximize output
–Minimize non-process time (reduce heat-up/cool down, etc.)
–Increase cycle time (reduce purges, etc.)
–Increase MWBC to >10,000 wafers
8
ALD Practical Challenges and Improvements
•Time separated ALD challenges:
–Added time for purge & pump-down
–Potential interaction between precursors
•Spatially separated ALD challenges:
–Chemistry precursor separation
9
Conventional ALD Olympia ALD
Wafer travels continuously Spatially separated chemistries Chemistry-free zones isolate
individual chemistries
Precursor Precursor
Wafer is stationary Alternating chemistries Purge separates chemistries
Primary technology used today
A B A B
A B
Applied’s Focus is on Spatially Separated ALD OlympiaTM ALD
0
1
2
3
4
5
Al2O340Å
TiO2200Å
SiO2250Å
TiN50Å
550°C SiN250Å
450°C SiN300Å
Nor
mal
ized
Thro
ughp
ut
Time Separated
Olympia
Single Wafer Furnace Olympia
Purge Time
Medium Common
precursor volume
Extremely Long Common precursor
volume
Short Precursor specific volume
MWBC Low
Deposition everywhere
Medium Deposition everywhere
Batch
High Contained deposition
Applied’s Focus is on Spatially Separated ALD OlympiaTM ALD
Applied’s Focus is on Spatially Separated ALD OlympiaTM ALD
Concept
Wafer travels continuously Spatially separated chemistries Chemistry-free zones isolate
individual chemistries
Precursor
A B
A B High-quality, low-temperature films
for ≤10nm
Modularity for materials engineering of future ALD films
Unique chemical confinement to minimize defects
High-productivity platform
Proven differentiation - DTOR at multiple customer sites
Proof
External Use
Treatment X
Modular Design for Atomic-Level Engineering
Precursor Precursor
20nm
Silicon Oxide
20nm
Silicon Nitride
20nm
Titanium Oxide
100nm
Aluminum Oxide
20nm
Titanium Nitride
Versatility Broadens Spectrum of Achievable ALD Materials
without Compromising Productivity
13
A B Thermal
B P A
Plasma Enhanced
ALD Mode Process Sequence
Atomic-Layer
Treatment X B A
Conventional ALD
Olympia ALD
Source: Applied Materials, Inc.
External Use
Olympia Solution Industry Challenge
Spatially Separated Sequence Preserves Films
Film
Qua
lity
Conventional ALD
Olympia ALD
14
B P A
X B A
Unique ALD Sequence Preserves Film Quality at Low Temperatures
Impurities Jeopardize Quality
High-Quality Film
14nm 10nm
20nm
7nm
External Use
Precursor Precursor Treatment X Precursor Treatment X
Modular Adaptability for Next-Generation Materials
15
Post-Treated X B A
Pre-Treated X B A
Multi-Chemical
C B A
Multi-Chemical
/Treatments
C B A X
Olympia ALD Modes
Opens the Way to Widest Spectrum of
Achievable Next-Generation Films
Selective Deposition
Advanced Patterning Films
Low-Temperature Films
Lower-k Films
Nano-Laminates Higher-k Films
Spatially Separated (Olympia) ALD
ATOMIC LAYER REMOVAL
Parameters Governing Isotropic Removal Etch Governing Equation:
: rate parameters for spontaneous chemical etching : neutral, and ion flux
: physical and ion enhanced etching yield : the fraction of surface sites occupied by the reactant species
a E k , 0 + Γ Γ ,
IE p Y Y ,
Θ
: neutral, and ion flux IE p Y Y ,
18
Parameters Governing Isotropic Removal Etch Governing Equation:
Pure Chemical Neutrals, Radicals
Parameters Governing Isotropic Removal Etch Governing Equation:
Physical Etch
Plasma Density (type of reactor)
Voltage (Bias)
If Bias = 0, Then Etch Rate is determined by the sheath voltage
Kinetic energy of electrons in plasma
To avoid underlayer damage, lower Te as much as possible
Atomic Layer Etching (ALE)
ALE allows for control of critical dimension to Å level, especially on ultra-sensitive materials.
In ALE, etching proceeds monolayer by monolayer in a cyclic, self limiting process. ► Passivation: Top monolayer is passivated by chemical precursors. ► Passivation makes top layer more easily etched compared to sub-layers. ► Purge: Remove the remaining chemical reactants. ► Etching: Passivated surface is exposed to ion bombardment with energy
below the sputtering threshold. ► The etch process stops once the topmost layer of the passivated crystal
was removed (self limiting).
Sputtering Yield of Si – Cl+ Bombardment
The density distribution within the simulation cell after 400 successive 5 and 85 eV Cl+ impacts on an initially defect-free silicon lattice.
Damage on Si surface increase with impact energy. Ultra-thin chlorinated layer produced by low energy ions and/or radicals is critical to ALE.
Sputtering Yield of Si
Successively bombardment: Crystalline Si surface bombarded successively by 400 ions (O).
Parallel bombardment: Crystalline Si surface bombarded by 1 ion, 400 samples (O).
Qualitatively good agreement with experimental and simulation results.
Si Etch Using Cl and Cl+ Ions – Cl+ Bombardment
We use the chlorinated surface generated using 5 eV Cl+ ions (400 ion impacts) and bombard it with 105 eV Cl+ ions (1000 ion impacts).
A deep crack/roughness is developed at the surface, and Cl is distributed inhomogeneously.
Si is continuously etched with Y ≈ 0.3
Thicker damage caused by high energy Cl+.
For more on this model please see paper: Molecular Dynamics Simulations of Low Damage Atomic Layer Etching. J-C. Wang, S. Rauf, J. Kenney, L. Dorf, and K. Collins, Applied Materials, Inc ALE 2015 Workshop, Portland, Oregon USA
Si Etch Using Cl and Ar+ Ions – Ar+ Bombardment
We use the chlorinated surface generated using 5 eV Cl+ ions (400 ion impacts) and bombard it with 50 eV Ar+ ions (1000 ion impacts).
Ar+ energy below sputtering threshold.
Cl removal rate is significantly reduced after 500 Ar+ impacts due to lower Cl density on surface. Etch stops.
Damage layer is thin.
Electron Beam-Generated Plasma Etch Tool Motivation: need for ultra-low ion energies
Atomic layer precision requires accurate control of ion energy during plasma processing
Damage caused by conventional plasma technologies (capacitive or inductively coupled plasmas) is becoming marginal for critical applications
Electron Beam-Generated Plasma Etch Tool
Electron beams’ energy targeted for ionization: reduces the overall ‘Maxwellian’ Te Also allows for tailoring of species dissociation
Ar/N2, e-Jet source power = 3 kW
Very low Te (and therefore low Plasma Potential) plasmas can be generated and sustained
Electron Beam-Generated Plasma Etch Tool
Si ALE in chlorine at different ion energies
Ei = 46.2 eV τsat ~ 25 s
Ei = 28.7 eV τsat ~ 60 s
Markers = data with repeats Curves = tanh fit
P = 5 mT Saturation is limited by Ar-only etch rate of ~ 1 A/min
As Bias Phase Duration is increased the etch depth per cycle saturates
Signifies passivation layer is being removed each cycle, resulting in layer-by-layer etching. For more on this chamber please see paper: Low Damage Etch Chamber for Atomic Precision Etching L. Dorf, S. Rauf, A. Agarwal, G. Monroy, K. Ramaswamy, Applied Materials ALE 2015 Workshop, Portland, Oregon USA
Atomic Level Precision Materials Engineering
•Each technology node is aggressively exploring new materials many of which require atomic layer deposition and removal control
•Technologies exist and are being developed that are making ALD/ALE possible in a production environment