AT94 Training 2001Slide 1

AT94KConfiguration Modes

Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131

Hotline

(408) 436-4119

fpga@atmel.com OR configurator@atmel.com

AT94K TrainingAT94K Training

AT94 Training 2001Slide 2

Configuration Modes

2 Configuration Modes controlled by M0 and M2

• Mode 0: Master serial ( by Configurator )

• Mode 1: Slave Serial Cascade ( External MCU )

AT94 Training 2001Slide 3

• Dedicated Pins (all modes)– M2, M0, RESET, CON, CCLK.

• Dual Use Pins– INIT (all modes)

– CSOUT, CHECK, CS1, CS0, A(23:0), D(15:0), HDC, LDC

AT94K Configuration I/O

CSOUT CHECK CS1 CS0 A(23:20) A(19:0) D(15:8) D(7:1) D0 HDC LDC

RESET A A A A A A A A A A A

Mode 0 O O A A A

Mode 1 O O A A A A

Mode 4 A A A A O A A

A (Active) O (Optional)

AT94 Training 2001Slide 4

Mode 0

M0

M2

OTS

CHECK

CCLK

D<0>

RESET

INIT

CON

CSOUT

AT94K

Mode 0Master Serial

CLK

DATA

CE

RESET

CEO

AT17C256

RESET

INIT

OPTIONAL IO

OPTIONAL IO

• 1, 2, 4 or 8 MHz internally-generated CCLK set through Bitstream options

• Configurator RESET pin may be tied to either FPGA RESET or INIT pin

Mode 1 M2 M0 0 0

AT94 Training 2001Slide 5

M0

M2

OTS

CHECK

CCLK

CS0

D<0>

RESET

INIT

CON

CSOUT

AT94K

Optional IO

Optional IO

IO<0>

IO<1>

IO<2>

IO<3>

IO<4>

IO<5>

IO<6>

IO<7>

IO<8>

IO<9>

IO<10>

IO<11>

IO<12>

IO<13>

IO<14>

IO<15>

IO<16>

IO<17>

IO<18>

IO<20>

IO<21>

IO<22>

IO<23>

IO<24>

IO<19>

IO<25>

IO<26>

IO<27>

IO<28>

IO<29>

IO<30>

IO<31>

Microprocessor

Reset

Clk

VSS

RESET

CLOCK

Mode 1

• External clocking up to 40 MHz• Microprocessor- or EEPROM-driven

Mode 1 M2 M0 0 1

AT94 Training 2001Slide 6

Mode 1 Parallel

IO<0>

IO<1>

IO<2>

IO<3>

IO<4>

IO<5>

IO<6>

IO<7>

IO<8>

IO<9>

IO<10>

IO<11>

IO<12>

IO<13>

IO<14>

IO<15>

IO<16>

IO<17>

IO<18>

IO<20>

IO<21>

IO<22>

IO<23>

IO<24>

IO<19>

IO<25>

IO<26>

IO<27>

IO<28>

IO<29>

IO<30>

IO<31>

Microprocessor

Reset

Clk

WE

M0

M2

OTS

CHECK

CCLK

CS0

D<0>

RESET

INIT

CON

CSOUT

AT94K

Optional IO

Optional IO

M0

M2

OTS

CHECK

CCLK

CS0

D<0>

RESET

INIT

CON

CSOUT

AT94K

Optional IO

Optional IO

CLOCK

RESET

• Allows independent programming of multiple FPGAs in parallel with the same data

Mode 1 M2 M0 0 1

AT94 Training 2001Slide 7

Mode 1 Cascade

IO<0>

IO<1>

IO<2>

IO<3>

IO<4>

IO<5>

IO<6>

IO<7>

IO<8>

IO<9>

IO<10>

IO<11>

IO<12>

IO<13>

IO<14>

IO<15>

IO<16>

IO<17>

IO<18>

IO<20>

IO<21>

IO<22>

IO<23>

IO<24>

IO<19>

IO<25>

IO<26>

IO<27>

IO<28>

IO<29>

IO<30>

IO<31>

Microprocessor

Reset

Clk

WE

M0

M2

OTS

CHECK

CCLK

CS0

D<0>

RESET

INIT

CON

CSOUT

AT94K

Optional IO

Optional IO

M0

M2

OTS

CHECK

CCLK

CS0

D<0>

RESET

INIT

CON

CSOUT

AT94K

Optional IO

Optional IO

CLOCK

RESET

GND

• Uses CS0 to propagate chip select between cascaded FPGAs; Xilinx devices propagate data

M2 M0

• Mode1 0 1

AT94 Training 2001Slide 8

M0

M2

OTS

CHECK

CCLK

D<0>

RESET

INIT

CON

CSOUT

AT94K

Mode 0Master Serial

M0

M2

OTS

CHECK

CCLK

CS0

D<0>

RESET

INIT

CON

CSOUT

AT94K

Mode1

Optional IO

Optional IO

M0

M2

OTS

CHECK

CCLK

CS0

D<0>

RESET

INIT

CON

CSOUT

AT94K

Mode 1

Optional IO

Optional IO

CLK

DATA

CE

RESET

CEO

AT17C256

CLK

DATA

CE

RESET

CEO

AT17C256

CLK

DATA

CE

RESET

CEO

AT17C256

RESET

INIT

Optional IO

Optional IO

Mode 0 with Mode 1 Cascade

AT94 Training 2001Slide 9

AT94K Example Bitstream8 bit Description

00000000 Null10110111 Preamble10000000 CR(31:24)00000100 CR(23:16)00100000 CR(15:8)10000001 CR(7:0)00000000 # Windows MSB00000010 # Windows LSB00000000 X Start(Extended) 00000000 Y Start(Extended)11010100 T/Z Start(Extended)00000000 X End(Extended)00000000 Y End(Extended)11010111 T/Z End (Extended)01000000 CR(63:56)00000010 CR(55:48)00010000 CR(47:40)01000010 CR(39:32)00000000 X Start 00001001 Y Start 01100100 T/Z Start 00000000 X End 00001001 Y End

01100101 T/Z End 10101010 Data 2 bytes 01010101 Postamble >11100111 < Postamble

Serial data is read in MSB first. Byte/word entries above are shown MSB<->LSB.

Not applicable to Mode 4.

AT94 Training 2001Slide 10

Cache Logic Mode

• Mode designed for CacheLogic applications– Device treated as an SRAM by the system

– Microprocessor treats FPGA as memory mapped I/O.

– Simple 24 bit Address and 8 bit Data structure.

31 or 39 0

32 Bit word defines address and data Information for one byte per clock cycle

X AddressY AddressZ AddressTag Data

8 Bits8 Bits4 Bits 4 Bits 8 Bits

MSB LSB

AT94 Training 2001Slide 11

AT94K Memory Map and CacheLogic

• Memory map is architected to support CacheLogic Applications.– Memory Map Pages are all dissociated.

» Writing data to one structure has NO impact on any other structure. Key requirement for CacheLogic.

– Simple 32 bit interface and 33MHz clocking allow very rapid caching of logic functions.

– Symmetrical FPGA architecture results in simple and predictable CacheLogic designs.

– Each memory byte has a unique memory map location and can be individually addressed.

– Data can be loaded x8 for faster reconfiguration.

– In full bitstream, X, Y, Z, Tag information is handled by the on-chip control logic.

• Design verification of AT94K FPSLIC devices

• Built-in support for Configuration processes

– Mode 0

– Mode 1

AT94 Training 2001Slide 12

ATDH40M Development Board

• Design verification of AT94K FPSLIC

• Built-in support for Configuration processes

– Mode 0

» Program Configurator

» Boot from Configurator

– Mode 1

» Download direct to FPGA with CS0

AT94 Training 2001Slide 13

FPSLIC Starter KitATSTK94

• Text book to take customers step by step through the design process

• System Designer tool for 4 months trial period– Synthesis/VHDL Simulator/Co-verification– AVR studio debugger– Place and Route IDS7– IAR and Imagecraft C compiler( 1 month trial period)

• Comprehensive development board– Design examples– AT94K40– AT17LV010 Configurator– 2 Serial Ports– Programmable switches & LEDs– ISP cables for programming configurator

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