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Project

Project

Bachelor Engineering Technology

EN7061

Analog Electronics Circuits

Aqeel Mohamed

201702149

David Krause

Date submitted: 06/01/2019

Assessment Cover Sheet

ii

ABSTRACT

The aim of this report is to design, simulate, build and test a simple 6.8v – 200mA DC power

supply from an AC supply. The design went through four different stages: full wave

rectification, smoothing, ripple reduction and voltage regulation. Firstly, the necessary

parameters were calculated to complete the design. Then, these parameters were

simulated in Altium Designer. Finally, the circuit was constructed on a breadboard and

soldered into a vero board.

iii

Table of Contents

ABSTRACT ............................................................................................................................. ii

TABLE OF FIGURES .............................................................................................................. iv

TABLE OF TABLES ................................................................................................................ iv

1.0 OBJECTIVES .................................................................................................................... 1

2.0 INTRODUCTION .............................................................................................................. 1

3.0 STAGES THEORITICAL CALCULATIONS ........................................................................... 3

3.1 Full Wave Rectification Stage ..................................................................................... 3

3.2 Smoothing Stage ........................................................................................................ 4

3.3 Ripple Reduction Stage .............................................................................................. 5

3.4 Zener Diode Shunt Regulator Stage ........................................................................... 6

4.0 ALTIUM DESIGNER SIMULATION ................................................................................... 7

4.1 Full Wave Rectification Stage ..................................................................................... 7

4.2 Smoothing Stage ........................................................................................................ 8

4.3 Ripple Reduction Stage .............................................................................................. 9

4.4 Zener Diode Shunt Regulator Stage ......................................................................... 10

5.0 BOARDS CONSTRUCTION ............................................................................................. 11

5.1 Breadboard ............................................................................................................... 11

5.1.1 Full wave rectification stage .............................................................................. 11

5.1.2 Smoothing stage ................................................................................................ 12

5.1.3 Ripple reduction stage ....................................................................................... 13

5.1.4 Zener diode shunt regulator stage .................................................................... 14

5.2 Vero board ................................................................................................................ 15

6.0 RESULTS ....................................................................................................................... 16

7.0 DISCUSSION.................................................................................................................. 17

8.0 CONCLUSION ................................................................................................................ 19

REFERENCES ....................................................................................................................... 20

APPENDIX ........................................................................................................................... 21

iv

TABLE OF FIGURES

Figure 1. Half wave rectifier circuit ............................................................................................ 1

Figure 2. Full wave bridge rectifier circuit ................................................................................. 2

Figure 3. Full wave rectifier with smoothing capacitor ............................................................. 2

Figure 4. Full wave rectification stage schematic ...................................................................... 7

Figure 5. Full wave rectification stage simulated graph ............................................................ 7

Figure 6. Smoothing stage schematic ........................................................................................ 8

Figure 7. Smoothing stage simulated graph .............................................................................. 8

Figure 8. Ripple reduction stage schematic ............................................................................... 9

Figure 9. Ripple reduction stage simulated graph ..................................................................... 9

Figure 10. Zener diode shunt regulator stage schematic ........................................................ 10

Figure 11. Zener diode shunt regulator stage simulated graph .............................................. 10

Figure 12. Full wave rectification stage breadboard ............................................................... 11

Figure 13. Full wave rectification stage breadboard graph ..................................................... 11

Figure 14. Smoothing stage breadboard ................................................................................. 12

Figure 15. Smoothing stage breadboard graph ....................................................................... 12

Figure 16. Ripple reduction stage breadboard ........................................................................ 13

Figure 17. Ripple reduction stage breadboard graph .............................................................. 13

Figure 18. Zener diode shunt regulator stage breadboard ..................................................... 14

Figure 19. Zener diode shunt regulator stage breadboard graph ........................................... 14

Figure 20. Vero board circuit ................................................................................................... 15

Figure 21. Breadboard circuit .................................................................................................. 21

Figure 22. Vero board backside ............................................................................................... 21

TABLE OF TABLES

Table 1. Stages results ............................................................................................................. 16

Table 2. Deviation percentages ............................................................................................... 17

Figure 1. Half wave rectifier circuit

1.0 OBJECTIVES

✓ To design a simple 6.8v – 200mA DC power supply from an AC supply including four

stages: rectification, smoothing, reduction and Zener regulation.

✓ To simulate the designed circuit using Altium Designer.

✓ To build the circuit and fully test it on a breadboard.

✓ To construct the circuit and fully test it on a vero board.

✓ To compare the theoretical, simulated and experimental obtained results.

2.0 INTRODUCTION

As direct current DC power supply is expensive to produce and alternating current AC power

supply is available at low cost, a method of converting AC to DC is required to produce a DC

supply at the minimum cost with the best constant DC output [1]. This operation is called

rectification. However, this operation can’t be done in one stage directly. An AC power must

move through numerous stages to completely change to DC [2].

There are two types of rectifier circuits, half wave and full wave rectification. A half wave

rectifier could be simply achieved by using a single diode. This way, a single diode only

allows either a positive half cycle or a negative half cycle of the input AC signal to flow

through the load while the remaining half cycle of the input AC signal is blocked. Thus, it

utilizes only the one-half cycle of the input signal. As a result, the output will be unsteady

(e.g. off during half cycle) which means huge amount of power is lost [3]. Figure 1 illustrates

a half wave rectifier circuit with its output.

2

Figure 2. Full wave bridge rectifier circuit

Figure 3. Full wave rectifier with smoothing capacitor

On the other side, a full wave rectifier circuit uses four individual rectifying diodes

connected in a closed loop “bridge” configuration to produce the desired output. Similarly

to a half wave circuit, a full wave rectifier circuit produces an output voltage or current

which is purely DC or has some specified DC component. Nonetheless, full wave rectifiers

have some fundamental advantages over their half wave rectifier counterparts. The average

DC output voltage is higher than for half wave as two diodes conduct current in each half

cycle (e.g. forward biased) which keeps the voltage on over the whole cycle. Additionally,

the output of the full wave rectifier has much less ripple than that of the half wave rectifier

circuit producing a smoother output waveform [4]. Figure 2 showcases a full wave bridge

rectifier circuit along with its output.

To produce a constant direct current using a full wave bridge rectifier, several stages should

be done to achieve that. Adding a smoothing capacitor after the bridge is the first stage to

reduce the ripple voltage. Next, placing a filter stage including capacitors, inductors or

resistors to reduce the ripple more and more. The final step is to add a voltage regulator

either a Zener diode or a regulator to produce a constant DC output.

3

3.0 STAGES THEORITICAL CALCULATIONS

3.1 Full Wave Rectification Stage

Used transformer: 230/0-6, 0-6v, 50 VA, 50Hz, 200 mA

The transformer ratio could be found using the RMS voltages values:

𝑉𝑠−𝑅𝑀𝑆

𝑉𝑝−𝑅𝑀𝑆=

12

230= 0.05217

These RMS values should be converted to peak values to be used in calculations where:

𝑉𝑝𝑒𝑎𝑘 = 𝑉𝑟𝑚𝑠 × √2

𝑉𝑝−𝑝𝑒𝑎𝑘 = 230 × √2 = 325 𝑣

𝑉𝑠−𝑝𝑒𝑎𝑘 = 16 × √2 = 17 𝑣

Due to the fact that on each cycle two diodes will be forward biased (turned on), there will

be a drop in the output voltage. A single diode forward biasing value is considered as almost

0.7 v. Hence, the peak value of the full wave rectified output Vout-peak will be:

𝑉𝑜𝑢𝑡−𝑝𝑒𝑎𝑘 = 𝑉𝑝𝑒𝑎𝑘−𝑠 − (2 × 𝑉𝑑)

𝑉𝑜𝑢𝑡−𝑝𝑒𝑎𝑘 = 17 − (2 × 0.7)

𝑉𝑜𝑢𝑡−𝑝𝑒𝑎𝑘 = 15.6 𝑣

For calculating the load resistor, the average voltage should be used alongside the known

current value:

𝑉𝑎𝑣𝑔 = 𝑉𝑜𝑢𝑡−𝑝𝑒𝑎𝑘 ×2

𝜋

𝑉𝑎𝑣𝑔 = 15.6 ×2

𝜋

𝑉𝑎𝑣𝑔 = 9.93 𝑣

Hence Rload will be:

𝑅𝑙𝑜𝑎𝑑 =𝑉𝑎𝑣𝑔

𝐼𝑙𝑜𝑎𝑑=

9.93

200 × 10−3= 49.65 Ω ≈ 50 Ω

𝑃𝑙𝑜𝑎𝑑 = 𝑉𝑎𝑣𝑔 × 𝐼𝑙𝑜𝑎𝑑 = 9.93 × 200 × 10−3 = 2 𝑊

4

3.2 Smoothing Stage

In this stage, a capacitor should be added to give a 6v Vripple. Since a capacitor will be added in this

stage, the average output voltage Vavg will increase:

𝑉𝑎𝑣𝑔 = 𝑉𝑜𝑢𝑡−𝑝𝑒𝑎𝑘 − (𝑉𝑟𝑖𝑝𝑝𝑙𝑒

2)

𝑉𝑎𝑣𝑔 = 15.6 − (6

2)

𝑉𝑎𝑣𝑔 = 12.6 𝑣

Hence Rload will be:

𝑅𝑙𝑜𝑎𝑑 =𝑉𝑎𝑣𝑔

𝐼𝑙𝑜𝑎𝑑=

12.6

200 × 10−3= 63 Ω

𝑃𝑙𝑜𝑎𝑑 = 𝑉𝑎𝑣𝑔 × 𝐼𝑙𝑜𝑎𝑑 = 12.6 × 200 × 10−3 = 2.5 𝑊

Using a rule of thumb which works if Iload ≤ 1 A [5 p.77], the needed smoothing capacitor C1

can be calculated:

𝐶1 =𝐼𝑙𝑜𝑎𝑑

𝑉𝑟𝑖𝑝𝑝𝑙𝑒× 6 × 10−3

𝐶1 =200 × 10−3

6× 6 × 10−3

𝐶1 = 200 𝜇𝐹

5

3.3 Ripple Reduction Stage

In this stage, the previous 6v Vripple is to be reduced by 70% which means that the new Vripple is:

𝑉′𝑟𝑖𝑝𝑝𝑙𝑒 = 𝑉𝑟𝑖𝑝𝑝𝑙𝑒 × (1 − 0.7) = 6 × 0.3 = 1.8 𝑣

Hence, the ripple reduction capacitor C2 is:

𝐶2 =𝐼𝑙𝑜𝑎𝑑

2𝑓 × 𝑉′𝑟𝑖𝑝𝑝𝑙𝑒

𝐶2 =200 × 10−3

2 × 50 × 1.8

𝐶2 = 1111.11 𝜇𝐹 ≈ 1111 𝜇𝐹

Hence, finding Xc to calculate the required Rr:

𝑋𝑐 =1

2𝜋𝑓𝐶2=

1

2𝜋 × 100 × 1111 × 10−6= 1.43 Ω

𝑉′𝑟𝑖𝑝𝑝𝑙𝑒 = 𝑉𝑟𝑖𝑝𝑝𝑙𝑒 ×

𝑋𝑐

√𝑅𝑟2 + 𝑋𝑐

2

After dividing, multiplying and rearranging the parameters, the following equation will be

used to calculate Rr:

𝑅𝑟 = √(𝑉𝑟𝑖𝑝𝑝𝑙𝑒 × 𝑋𝑐

𝑉′𝑟𝑖𝑝𝑝𝑙𝑒

)

2

− 𝑋𝑐2

𝑅𝑟 = √(6 × 1.43

1.8)

2

− 1.432

𝑅𝑟 = 4.55 Ω

Hence, Vr will be:

𝑉𝑟 = 𝐼𝑙𝑜𝑎𝑑 × 𝑅𝑟 = 200 × 10−3 × 4.55 = 0.91 𝑣

The output voltage will change in this stage as there are two capacitors now:

𝑉𝑜𝑢𝑡 = 𝑉𝑖𝑛 − 𝑉𝑟 = 15.6 − 0.91 = 14.69 𝑣

Hence, Rload will be:

𝑅𝑙𝑜𝑎𝑑 =𝑉𝑜𝑢𝑡

𝐼𝑙𝑜𝑎𝑑=

14.69

200 × 10−3= 73.45 Ω ≈ 74 Ω

𝑃𝑙𝑜𝑎𝑑 = 𝑉𝑎𝑣𝑔 × 𝐼𝑙𝑜𝑎𝑑 = 14.69 × 200 × 10−3 = 2.9 𝑊

6

3.4 Zener Diode Shunt Regulator Stage

In this stage, the output voltage Vout is required to be shunted to 6.8 v with 200 mA. Knowing that

Iz = 10 mA and using these values, the Zener resistor Rz can be calculated:

𝑅𝑧 =𝑉𝑧

𝐼𝑡=

11.69 − 6.8

(200 + 10) × 10−3= 23.3 Ω ≈ 23 Ω

𝑃𝑧 = 𝑉𝑧 × 𝐼𝑡 = 4.89 × 210 × 10−3 = 1.02 𝑊

Now, calculating Rload:

𝑅𝑙𝑜𝑎𝑑 =𝑉𝑜𝑢𝑡

𝐼𝑙𝑜𝑎𝑑=

6.8

200 × 10−3= 34 Ω

𝑃𝑙𝑜𝑎𝑑 = 𝑉𝑜𝑢𝑡 × 𝐼𝑙𝑜𝑎𝑑 = 6.8 × 200 × 10−3 = 1.36 𝑊

7

4.0 ALTIUM DESIGNER SIMULATION

After calculating the required values for capacitors and loads, Altium designer was used to

test and simulate the determined values.

4.1 Full Wave Rectification Stage

Figure 4. Full wave rectification stage schematic

Figure 5. Full wave rectification stage simulated graph

8

4.2 Smoothing Stage

Figure 6. Smoothing stage schematic

Figure 7. Smoothing stage simulated graph

9

4.3 Ripple Reduction Stage

Figure 8. Ripple reduction stage schematic

Figure 9. Ripple reduction stage simulated graph

10

4.4 Zener Diode Shunt Regulator Stage

Figure 10. Zener diode shunt regulator stage schematic

Figure 11. Zener diode shunt regulator stage simulated graph

11

Figure 12. Full wave rectification stage breadboard

Figure 13. Full wave rectification stage breadboard graph

5.0 BOARDS CONSTRUCTION

5.1 Breadboard

After finishing calculations and simulation, the stages were constructed on a breadboard

and tested.

5.1.1 Full wave rectification stage

12

Figure 14. Smoothing stage breadboard

Figure 15. Smoothing stage breadboard graph

5.1.2 Smoothing stage

13

Figure 16. Ripple reduction stage breadboard

Figure 17. Ripple reduction stage breadboard graph

5.1.3 Ripple reduction stage

14

Figure 18. Zener diode shunt regulator stage breadboard

Figure 19. Zener diode shunt regulator stage breadboard graph

5.1.4 Zener diode shunt regulator stage

15

5.2 Vero board

Next, almost the same components used in breadboard construction were soldered on a

vero board and tested. However, due to the close values obtained from both breadboard

and vero board, breadboard was considered as the main experimental results.

Figure 20. Vero board circuit

16

6.0 RESULTS

Table 1. Stages results

Stage 1: Full Wave Rectification

Calculated Simulated Experimental

Vpeak (v) 15.6 15.2 15.6

Stage 2: Smoothing

Calculated Simulated Experimental

Vpeak (v) 15.6 15.2 15.6

Vavg (v) 12.6 12.02 12.4

Vripple (v) 6 6.3 6.8

Stage 3: Ripple Reduction

Calculated Simulated Experimental

Vpeak (v) 15.6 15.1 15.6

Vavg (v) 14.69 14.24 14.9

Vripple (v) 1.8 1.6 1.4

Stage 4: Zener Diode Shunt Regulator

Calculated Simulated Experimental

Vpeak (v) 6.8 6.84 6.8

Vavg (v) 6.8 6.83 6.53

Vripple (mv) 0 22 600

17

7.0 DISCUSSION

From the above results table, deviation percentages can be determined between calculated,

simulated and experimental results assuming the calculated results are the reference or

theoretical values. This will help in identifying the areas of errors hence explaining the

reasons for these errors.

Table 2. Deviation percentages

Stage 1: Full Wave Rectification

Calculated – Simulated %p Calculated – Experimental %p

Vpeak (v) %𝑝 =15.6 − 15.2

15.6= 2.56 % %𝑝 =

15.6 − 15.6

15.6= 0 %

Stage 2: Smoothing

Calculated – Simulated %p Calculated – Experimental %p

Vpeak (v) %𝑝 =15.6 − 15.2

15.6= 2.56 % %𝑝 =

15.6 − 15.6

15.6= 0 %

Vavg (v) %𝑝 =12.6 − 12.02

12.6= 4.6 % %𝑝 =

12.6 − 12.4

12.6= 1.59 %

Vripple (v) %𝑝 =6 − 6.3

6= 5 % %𝑝 =

6 − 6.8

6= 13.33 %

Stage 3: Ripple Reduction

Calculated – Simulated %p Calculated – Experimental %p

Vpeak (v) %𝑝 =15.6 − 15.1

15.6= 3.21% %𝑝 =

15.6 − 15.6

15.6= 0%

Vavg (v) %𝑝 =14.69 − 14.24

14.69= 3.06 % %𝑝 =

14.69 − 14.9

14.69= 1.43 %

Vripple (v) %𝑝 =1.8 − 1.6

1.8= 11.11 % %𝑝 =

1.8 − 1.4

1.8= 22.22 %

Stage 4: Zener Diode Shunt Regulator

Calculated – Simulated %p Calculated – Experimental %p

Vpeak (v) %𝑝 =6.8 − 6.84

6.8= 0.59 % %𝑝 =

6.8 − 6.8

6.8= 0 %

Vavg (v) %𝑝 =6.8 − 6.83

6.8= 0.44 % %𝑝 =

6.8 − 6.53

6.8= 3.97 %

Vripple (mv) %𝑝 = 0.22 % %𝑝 = 6 %

18

Analyzing the deviation percentages between the calculated and simulated values, it can be

said that these percentages are almost in range and acceptable (0.44% - 11.11%). The 11%

deviation was for Vripple at third stage while other values have an error less than 5%. As the

same calculated values were used in the simulation, the deviation percentages were

expected to be in range. This shows that the simulation is consistent with the theory.

Turning on to the deviation percentages between the calculated and experimental values, it

is evident that there are some high percentages of error in this part (1.43% - 22.22%) where

higher deviation percentages where found for Vripple in stages 3 and 4. This could be due to

various reasons. The used components are not as well as the calculated values due to the

lack of some values. Additionally, these components have tolerances. These tolerances

affect the measured values as they obtain an unfixed value. Furthermore, human error in

recording measurements is considered an error factor too. For instance, several taken

measurements where floating between ±1 volt.

19

8.0 CONCLUSION

A 230v/12v step down low voltage power transformer was used to successfully design 6.8

volts – 200 mA DC power supply through four stages. Firstly, four diodes were used to

design the full wave bridge rectifier stage. Next, a 200 µF capacitor was placed to gain a

ripple of approximately 6 volts. Then, a 1111 µF was used to reduce the ripple by

approximately 70% (1.8 volts). Finally, a 6.8v Zener diode was placed to regulate the output

voltage to the required voltage 6.8v.

This design was simulated using Altium Designer then constructed on a breadboard and a

vero board. There were some error percentages (0.22 % - 22.22 %) found between obtained

values due to the component’s tolerances and human error. Nevertheless, the aims of this

project have been fulfilled and accomplished.

20

REFERENCES

[1] Razak, I. (2016, September). A Design of Single Phase Bridge Full-wave Rectifier. Retrieved from https://www.researchgate.net/publication/308788220_A_Design _of_Single_Phase_Bridge_Full-wave_Rectifier

[2] Admin. (2018, December 13). Rectifier - Half wave rectifier and Full wave rectifier. Retrieved from https://mechatrofice.com/circuits/rectifier-half-wave-full-wave

[3] Shaik, A. (n.d.). Full wave rectifier. Retrieved from https://www.physics-and-radio- electronics.com/electronic-devices-and-circuits/rectifier/fullwaverectifier.html

[4] Full Wave Rectifier and Bridge Rectifier Theory. (2018, February 24). Retrieved from https://www.electronics-tutorials.ws/diode/diode_6.html

[5] National Semiconductor Voltage Regulator Handbook 1980: National Semiconductor Corporation (n.d.). Retrieved from https://archive.org/details/NationalSemiconductor VoltageRegulatorHandbook1980/page/n77

[6] Jojo. (2018, July 31). Full Wave Rectifier-Bridge Rectifier-Circuit Diagram with Design & Theory. Retrieved from http://www.circuitstoday.com/full-wave-bridge-rectifier

21

Figure 21. Breadboard circuit

APPENDIX

Figure 22. Vero board backside