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APPLICATION NOTE

Assembling EPCGaN Transistors

Table of Contents

1. Overview of GaN Technology . . . . . . . . . . . . . . . . . . . page 1

2. PCB Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . page 3

3. Quick Start Assembly Guide . . . . . . . . . . . . . . . . . . . . page 6

4. Die Storage Requirements . . . . . . . . . . . . . . . . . . . . . page 8

5. Heatsinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 8

6. Post Assembly Inspection . . . . . . . . . . . . . . . . . . . . . . page 8

7. Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 9

8. Summary and Conclusions . . . . . . . . . . . . . . . . . . . . . page 9

Appendix A: Low Cost Assembly Kit . . . . . . . . . . . . . . . . page 10

Appendix B: Step-by-Step Quick Start Assembly Process . . page 10

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2010 | | PAGE 1

Assembling EPC GaN Transistors

EFFICIENT POWER CONVERSION

1. Overview of Gallium Nitride (GaN) TechnologyIn June 2009 Efficient Power Conversion Corporation (EPC) introduced the first enhancement mode gallium nitride on silicon power transistors designed specifically as power MOSFET replacements. These products were developed to be produced in high volume at low cost using stan-dard silicon manufacturing technology and facilities. The initial product family consists of 10 part numbers ranging from 40V to 200V and from 4 milliohms to 100 milliohms. Table 1 lists the devices and their basic char-acteristics. For more information about EPC’s GaN transistors, go to www.epc-co.com.

STRUCTURE – A device’s cost effectiveness starts with leveraging existing production infrastructure. EPC’s process begins with silicon wafers. A thin layer of Aluminum Nitride (AlN) is grown on the Silicon to isolate the de-vice structure from the substrate. The isolation between the substrate and the active device, for product with voltage ratings 200 V and below, is over 300 V. On top of this AlN, a thick layer of highly resistive GaN is grown. This layer provides a foundation on which to build the active transistor. An electron generating material comprised of Aluminum, Gallium, and Nitro-gen (AlGaN) is applied on top of the GaN. This layer creates an abundance of free electrons just below it. Further processing forms a depletion region under the gate. To enhance the transistor, a positive voltage is applied to the gate in a similar manner to turning on an n-channel, enhancement mode power MOSFET. A cross section of this structure, repeated many times to form a complete power device, is depicted in figure 1. The end re-sult is a fundamentally simple, cost effective solution for power switching1.

EPC’s GaN transistors are lateral devices with all three terminals: gate, drain, and source, on the top side of the chip. The active device is isolated from the substrate and fully encapsulated by passivation layers. Generally, EPC devices have three layers of metal used to connect the active device to the outside world (fig 2). The top metal layer is then used as a founda-tion for solder bumps as shown in Figure 3. This configuration allows EPC’s GaN transistors to eliminate unnecessary elements of traditional power MOSFET packaging that contribute to higher inductance, thermal and electrical resistance, higher costs, and compromised reliability.

Alana Nakata, Edgar Abdoulin, Jianjun Cao PhD, and Yanping Ma PhD, EPC Corporation

Si

S G D

GaN

AIGaN

Protection Dielectric

Aluminum NitrideIsolation La

Two DimensionalElectron Gas (2DEG)

yer

Fig 1: EPC’s GaN Power Transistor Structure

Fig 3: Flip ChipFigure 2: Device Construction

S I L I C O N S U B S T R AT E

GS D

Semi Insulating GaN (uGaN)

Interlayer Insulation

Interlayer Insulation

Top Layer Insulation

Metal Layer 3

Metal Layer 2

Metal Layer 1

AIN Isolation Layer

AIGaN Strain Layer

Active GaN Device Region

Solder Bumps

PRINTED CIRCUIT BOARDCOPPER TRACES

SILICONAluminum Nitride

APPLICATION NOTE



EPC TRANSISTOR CONFIGURATIONS – As of March 2010, EPC transistors come in four different layout configurations (fig 4,5,6,7, bottom view). All devices use eutectic lead solder, 63Sn/37Pb (Conversion to lead-free is scheduled for late 2010). Bump height is 75 µm +/- 20 µm.

All products are delivered in tape and reel for efficient and low cost assembly (Fig 8).

DIM MILLIMETERS MIN Nominal MAX

A 4.075 4.105 4.135 B 1.602 1.632 1.662 c 1.379 1.382 1.385 d 0.577 0.580 0.583 e 0.235 0.250 0.265 f 0.248 0.250 0.252 g 0.400 0.400 0.400


A 1.672 1.702 1.732 B 1.057 1.087 1.117 c 0.834 0.837 0.840 d 0.327 0.330 0.333 e 0.235 0.250 0.265 f 0.248 0.250 0.252 g 0.400 0.400 0.400


A 3.524 3.554 3.584 B 1.602 1.632 1.662 c 1.379 1.382 1.385 d 0.577 0.580 0.583 e 0.260 0.275 0.290 f 0.297 0.300 0.303 g 0.600 0.600 0.600

Die orientation

dot

Gate Pad bump is

under this corner

Die is placed into pocket bump side down (face side down)

7” reel

Loaded Tape Feed Direction

a

d e f g

c

b

EPC1012 Dimension (mm) target min max

a 8.00 7.90 8.30 b 1.75 1.65 1.85

c (see note) 3.50 3.45 3.55 d 4.00 3.90 4.10 e 4.00 3.90 4.10

f (see note) 2.00 1.95 2.05 g 1.5 1.5 1.6

Note: Pocket position is relative to the sprocket holemeasured as true position of the pocket, not the pocket hole

4mm pitch, 8mm wide tape on 7” reel

Fig 8: Tape and Reel configuration

Fig 4: EPC1001, EPC1005, EPC1015 Die and Solder Bump Layout,bottom view

Fig 5: EPC1007, EPC1009, EPC1014 Die and Solder Bump Layout,bottom view

Fig 6: EPC1010, EPC1011 Die and Solder Bump Layout, bottom view

Fig 7:EPC1012, EPC1013 Die and Solder Bump Layout,bottom view


A 1.681 1.711 1.741 B 0.889 0.919 0.949 c 0.666 0.669 0.672 d 0.252 0.255 0.258 e 0.230 0.245 0.260 f 0.297 0.300 0.303 g 0.600 0.600 0.600

APPLICATION NOTE



2. Printed Circuit Board (PCB) Design Guide

LAND PATTERN DESIGN – Figure 9 shows the recommended land pattern design for EPC’s products listed in Table 1. As an example, for EPC1001 transistors, pad no. 1 is gate, pads no. 3, 5, 7, 9, 11 are drain, and pad no. 2, 4, 6, 8, and 10 are source (Pad number 2 is recommended to pin out as source sense). For products with 250 µm wide solder bars, the land pad width is 200 µm. For products with 300 µm wide solder bars, the land pad width is 250 µm.

Pad no. 1 is Gate;Pads no. 3, 5, 7, 9, 11 are Drain;Pads no. 4, 6, 8, 10 are Source;Pad no. 2 is source and is recommended to pin out as a source sense.

Pad no. 1 is Gate;Pad no. 3 is Drain;Pads no. 2 and 4 are Source.

Pad no. 1 is Gate;Pads no. 3 and 5 are Drain;Pads no. 2 and 4 are Source.

Pad no. 1 is Gate;Pads no. 3, 5, 7 are Drain;Pads no. 4, 6 are Source;Pad no. 2 is source and is recommended to pin out as a source sense.

400

507

1087

1702

1 3 4

2

5

400 X2

200 200 X3

787

280

600

414

919

1711

1 3 4

2

205 X2

250 X2

600

619

205

X2

Fig 9a: Recommended Land Pads for EPC1001, EPC1005, and EPC1015 (units in µm)

Fig 9b: Recommended Land Pads for EPC1010 and EPC1011 (units in µm)

Fig 9c: Recommended Land Pads for EPC1007, EPC1009, and EPC1014 (units in µm)

Fig 9d: Recommended Land Pads for EPC1012 and EPC1013 (units in µm)

600

802

1632

3554

1 3 4

2

5

250

1332

530

6 7

600 X4

250 X5

APPLICATION NOTE



SOLDER MASK – Non-solder-mask-defined (NSMD) land is preferred. NSMD provides a more accurate pattern registration than SMD (solder-mask-de-fined) which is required due to the fine pitch configuration. Furthermore, NSMD land allows solder to flow around the edges of the land, eliminating areas of stress concentrations, and potentially improving reliability.

Figures 10 is the recommended solder mask opening dimensions for EPC products listed in Table 1. Units are in µm.

SURFACE FINISH – The commonly used pad-surface finishes are as follows:

• NiAu (electroless nickel immersion gold);• OSP (organic solderability preservative);• HASL (hot-air surface leveling);• Immersion Ag (silver).

EPC has no preference on the suitable surface finish for this package. Reli-ability tests were performed on NiAu finish.

BOARD VIA – EPC recommends 2 OZ top layer Cu and through PCB vias just outside of the die area. A thick top layer copper and multi layer PCB (e.g., 4 layers or 6 layers), connected by vias just outside of the die area is im-portant to minimize the resistance added by the PCB. Figure 11 shows the relative positions and dimensions of top layer Cu, board vias, and solder mask for EPC products listed in Table 1.

350

1432

630

X2

350 X5

300

887

300 X2

380

X2

305 350 X2

719

305

X2

0.250

1732

2282

1 3 4 5 6 7 8 9 10 1 1

2

Pad no. 1 is Gate;Pads no. 3, 5, 7, 9, 11 are Drain;Pads no. 4, 6, 8, 10 are Source;Pad no. 2 is source and is recommended to pin out as a source sense.

0.250

1732

2282

1 3 4 5 6 7 8 9 10 1 1

2

0.250

1732

2282

1 3 4 5 6 7 8 9 10 1 1

2

Pad no. 1 is Gate;Pads no. 3, 5, 7, 9, 11 are Drain;Pads no. 2, 4, 6, 8, 10 are Source;Pad no. 2 is source and is recommended to pin out as a source sense.

Fig 10a: Recommended solder mask for EPC1001, EPC1005, EPC1015

Fig 10b: Recommended Solder Mask for EPC1010 and EPC1011

Fig 10c: Recommended Solder Mask for EPC1007, EPC1009, and EPC1014

Fig 10d: Recommended Solder Mask for EPC1012 and EPC1013

Fig 11a: Top layer copper trace(2Oz), solder mask, and vias for EPC1001, EPC1005, EPC1015

Fig 11b: Top layer copper trace(2Oz), solder mask, and vias for EPC1001, EPC1005, EPC1015

Fig 11c: Top layer copper trace(2Oz),solder mask, and vias for EPC1001, EPC1005, EPC1015

Pad no. 1 is Gate;Pads no. 3, 5, 7, 9, 11 are Drain;Pads no. 2, 4, 6, 8, 10 are Source.

APPLICATION NOTE



FIDUCIALS – Depending on the accuracy of the pick and place equipment, it may be necessary to have local fiducials. Local fiducials are typically placed diagonally outside of the die.

Alignment legends can be used as visual indicators for good placement of the die on PCB. Such alignment legends can be copper features on the top layer, or solder mask features, or silkscreen features.

STENCIL DESIGN – The recommended stencil aperture designs are shown in Figure 12. The rectangular shaped apertures are larger than the land pads. The corners of the apertures are rounded at radius of 60 µm. The recom-mended stencil foil thickness is 100 µm.

1 3 4

2

5

2032

2582

6 7

0.250

1 3 4

2

5

1187

1737

0.250

1 3 4

2

1319

1869

0.250

280

1362

560

X2

280 X5

240

827

240 X2

320

X2

235 280 X2

649

235

X2

Fig 11d: Top layer copper trace(2Oz),solder mask, and vias for EPC1010 and EPC1011

Fig 12a: Recommended Stencil Aperture Design for EPC1001, EPC1005, EPC1015 (units in µm)

Fig 12b: Recommended Stencil Aperture Design for EPC1010 and EPC1011

Fig 12c: Recommended Stencil for EPC1007, EPC1009, and EPC1014

Fig 12d: Recommended Stencil for EPC1012and EPC1013

Fig 11e: Top layer copper trace(2Oz),solder mask, and vias for EPC1007, EPC1009, and EPC1014

Fig 11f: Top layer copper trace(2Oz),solder mask, and vias for EPC1012 and EPC1013

Pad no. 1 is Gate;Pads no. 3, 5, 7 are Drain;Pads no. 2, 4, 6 are Source;

Pad no. 1 is Gate;Pads no. 3 and 5 are Drain;Pads no. 2 and 4 are Source.

Pad no. 1 is Gate;Pad no. 3 is Drain;Pads no. 2 and 4 are Source.

APPLICATION NOTE



SOLDER PASTE AND SOLDER PASTE PRINTING – Eutectic SnPb solder (63Sn-37Pb) is used with particle size of either Type 4 or Type 3. The solder paste typically contains about 50% of solder and 50% of flux by volume. EPC recommends that solder pastes with a no-clean flux be used.

Solder paste printing is accomplished by stenciling solder paste onto the PCB land pads. Alignment of the aperture to the pad is recommended to be 50 µm or less, however, the solder paste realigns with the land pad dur-ing reflow. As a result, the alignment of the solder paste to the land pad is not very critical.

DIE PLACEMENT – EPC recommends that misalignment of bumps on the die to the land pads on the PCB be 50 µm or less. However, the surface tension of the molten solder will self-align the die to the land pads. Misalignment up to 100 µm during placement of the die on the PCB is tolerable.

It is advisable not to correct a placement offset. This can smear the paste underneath, and can lead to bridging and solder balling.

Figure 13 illustrates a die placement prior to reflow.

3. Quick-Start Assembly Guidelines

GaN users can generally apply standard surface mount techniques to suc-cessfully attach EPC’s GaN transistors onto standard PCBs. Below are two techniques that have demonstrated reliable and high yielding results; a tacky flux process, and a solder stencil process.

TACKY FLUX PROCESS – EPC’s GaN transistors can be mounted directly onto PC boards without added solder by using a tacky flux to hold the part in place while reflowing the solder on the die (fig 14). An example

of an acceptable process uses Kester TSF6502 no-rinse flux2. The reflow profile used by EPC to assemble product used in the Application Readi-ness Review3 is shown in figure 15 compared with the manufacturer’s rec-ommended profile. Figure 16 is an X-Ray image of a mounted device on FR408 PCB material using the temperature profile of figure 15.

SOLDER STENCIL PROCESS – Many high volume assembly processes involve using a solder stencil mask to apply additional solder to the PCB prior to mounting devices (fig 13). This is recommended in order to insure ade-quate die standoff distance following reflow when die are mounted onto a PCB with a solder mask. A recommended reflow temperature profile is shown in figure 17 and an X-Ray of the resulting die mounted on the PCB is shown in figure 18.

Solder bump

7010

075

± 20

675 ±

15

Die

PCB

Solder maskCopper traceStencil printed solder paste

Die

PCB

Solder bump

Solder mask Tacky �uxCopper trace

Re�ow Pro�le

Assembly House Pro�le

Flux Vendor Pro�le

Tem

pera

ture

(˚C)

Time (Seconds)

250

200

150

100

50

00 60 120 180 240 300 360 420 480

Re�ow Pro�le

Tem

pera

ture

(˚C)

Time (Seconds)

300

250

200

150

100

50

00 50 100 150 200 250 300

Fig 13: Schematic cross-sectional view of a die placed on a PCB with a stencil-printed solder paste

Fig 15: Reflow profile from Kester Datasheet for TSF 6502 overlaid with assembly house profile

Fig 16: Tacky Flux assembly process[Pictures courtesy of Promex-Industries]

Fig 17 and 18: Solder Stencil Process[Pictures courtesy of Promex-Industries]

Fig 14: Schematic cross-sectional view of a die placed on a PCB with tacky flux

APPLICATION NOTE



SIMPLE, LOW-VOLUME ASSEMBLY EQUIPMENT – EPC GaN transistors are ex-tremely small when compared with silicon power MOSFETs of similar cur-rent handling capability. This can pose a challenge to designers wanting to quickly produce experimental or prototype circuits. EPC’s applications group has been successful in using a simple two-station setup for mount-ing individual die on PCBs as shown in figure 19 (a) and (b).

The system consists of an XYZ-θ table with a vacuum pump for aligning and installing the die on the board and a separate hot air station to solder the die (For a full list of equipment, see Appendix A). The use of ”tacky flux” enables the board to be moved from one station to another with-out loss of alignment. Best results are obtained when the board is at room temperature prior to applying the flux; this preserves the “tackiness” of the flux and prevents the die from shifting while being transferred from one station to another.

The process begins by applying a small amount of flux on the die footprint area, and then continues with aligning and installing the die on the XYZ-θ table. The soldering profile shown in figure 20 (a) has proven to be an ad-equate starting point to obtain a good solder joint as can be seen from the X-Ray and optical images in figure 20 (b). Ambient temperature and other factors in a specific lab setting might cause minor adjustments to the time and temperature setting to be required. Figure 20(c) shows the X-Ray and optical result of a part that used the same temperature profile as the part in 20(b), but was reflowed for almost double the time. The result is too

much reflow, and the solder is now seen to be flowing out from under the die. Depending on how much solder flows out, this could cause a bridge between terminals and therefore an electrical short.

Preheating the boards is a must. Whereas the amount of preheat will de-pend on the type of board used, maintaining a PCB surface temperature of about 100°C prior to beginning the soldering sequence has proven to be an adequate condition to ensure a proper solder joint regardless of copper content or thickness. Appendix B is a basic step-by step process success-fully used by EPC’s applications group. As always, experimenting with vari-ous settings is a good practice to find an optimum solution.

DIE REMOVAL – De-soldering the EPC die from the boards is an easier pro-cess. Again, the preheat step is important to bring the solder to a melt-ing point to remove the die. The die can be removed using a pair of fine tweezers when the solder is re-flowed in zone one or two. There is no need to apply additional flux prior to removal. A cleaning/solder wicking step following the removal will assist in achieving a flat surface for subsequent die mounts.

Fig 19a and 19b: Low volume die mounting apparatus

Fig 20b: X-Ray of a part assembled using the profile in figure 20a

[X-Ray Photos courtesy of EAG]

Fig 20c (below left and right): X-Rayand Optical of part assembled usinga too long time – temp profile

20a: Soldering/de-soldering time-temperature profile

4 APPLICATION NOTE



UNDERFILL CONSIDERATIONS – EPC has tested parts with both underfill and no-undefill with no measured difference in performance or reliability. In figure 21 we show reliability tests under high voltage and high humidity conditions. All groups show good results after 1000 hours of stress.

Additional stress testing was done with reduced separation between gate-source and drain terminals without underfill. Experimental parts with 100 um gaps between all terminals were put on stress at 200V (Produc-tion 200V product from EPC has a 300um gap between terminals). Results shown in figure 22 demonstrate that, even under stresses as high as 2V/um, devices without underfill do not degrade after 1000 hrs.

Underfill may still be warranted if the users’ manufacturing process may expose the GaN transistors to contamination after mounting. EPC has suc-cessfully applied two underfill materials during product development and during demo-board manufacture.

1. Loctite FP4549Si 9

2. Zymet CN-1703 10

4. Die Storage Requirements

EPC’s GaN transistors are packed in nitrogen purged, vacuum sealed anti-static bags including desiccant packs 4. Devices in sealed, unopened bags have a shelf life in excess of two years. Once a bag is opened, its contents should be treated as Moisture Sensitivity Level (MSL) 3 to guarantee good solderability.

5. Heatsinking

EPC’s GaN transistors are able to conduct significantly higher current than similarly-sized power MOSFETs. In general, the lower on-resistance and lower temperature coefficient of that on-resistance 5 make additional heat-sinking unnecessary. If, however, even greater power density is desired, heatsinks can be attached directly to the back of the GaN device as per figure 23. To avoid mechanically damaging the devices, it is recommended that a thermal pad be used between the device and the heatsink such as 3M thermally conductive interface pads 6, Dow Corning thermal interface pads and films 7, or Bergquist Gap Pads 8

6. Inspection

EPC’s GaN transistors are mechanically robust and have demonstrated high yield in volume assembly. Damage, however, can still occur if several standard precautions are not taken to insure adequate solder reflow, re-duce excessive die tilt, and avoid residual solder flux.

ADEQUATE SOLDER REFLOW – As with all chip scale packaging, the best way to determine if devices are properly reflowed is by taking X-ray images. Figures 16 and 18 show X-ray images of parts assembled with tacky flux (no added solder) and with a solder stencil process. EPC found that the solder stencil process typically yields less voiding, but both processes can be used to produce a reliable product based on EPC’s reliability testing.

HTRB, Under�ll vs. No-under�ll

Stress Hour1 10 100 1000

200180160140120100

80604020

0

I DSS @

100 V

(µA)

THB, Under�ll vs. No-under�ll


200180160140120100

80604020

0

I DSS @

100 V

(µA)

HTRB, 200 V Drain Bias, 100 µm Solder Spacing


60

50

40

30

20

10

0

I DSS @

200 V

(µA)

Heat Sink

Thermal Pad EPC GaN Die PCB

Fig 21: HTRB and THB comparing underfilled parts with no-underfill parts

Fig 22: HTRB tests with 100uM terminal spacing and no underfill

Figure 23: GaN devices mounted on a PCB with heatsink directly attached

4 APPLICATION NOTE



DIE TILT AND DENDRITES – During EPC’s product testing and assembly pro-cess development, several parts were observed to be tilted after reflow us-ing a solder stencil process (figure 24). Three causes of die tilt were found; (1) uneven thickness of solder paste, (2) excessive vibration during reflow, and (3) non-optimized temperature profile.

If the assembly process uses a solder with a flux that requires rinsing, die tilt can obstruct the flow of the rinse and cause flux to be trapped under the die. This residual flux can cause rapid formation of dendrites (figure 25) which will cause early device failure. For this reason, EPC recommends using a no rinse solder flux with low ionic content.

7. Future Work

EPC will be converting to a lead free solder system in the second half of 2010. In addition to full qualification of the new system, an update of pre-ferred assembly conditions will be published.

EPC’s reliability testing continues. Phase One testing is complete 3 and Phase Two testing is scheduled to be published in May 2010. In Phase Three, scheduled for September 2010, EPC will have reliability data for lead free product.

8. Summary and Conclusions

EPC’s enhancement mode GaN transistors give the power conversion de-signer a whole new spectrum of capabilities unachievable with silicon-based power MOSFETs. The intrinsic low conduction losses and high fre-quency capability are complimented by the ability of GaN-on-silicon to be assembled without additional packaging. The assembly technology required is not significantly more demanding than the technology already in place for LGA, chipscale, and high-density SO packages.

Tilted Die

PCB PLANETrapped flux residue coming up the side of die

Fig 24: Die Tilt

Figure 25: Solder dendrites after exposure to non-reflowed solder flux

Table 1

Part Number Package (mm) Mode Ch VDS VGS

Max. RDS(ON) (mW) @ 5V QG @ 5V QGS Typ. QGD Typ. VTH Typ. QRR ID

Single

EPC1014 LGA 1.7 x 1.1 EN 40 6 16.0 3.0 1.0 0.6 1.4 0 10

EPC1015 LGA 4.1 x 1.6 EN 40 6 4.0 11.6 3.8 2.2 1.4 0 33

EPC1009 LGA 1.7 x 1.1 EN 60 6 30.0 2.4 0.8 0.6 1.4 0 6

EPC1005 LGA 4.1 x 1.6 EN 60 6 7.0 10.0 3.0 2.5 1.4 0 25

EPC1007 LGA 1.7 x 1.1 EN 100 6 30.0 2.7 0.8 1.0 1.4 0 6

EPC1001 LGA 4.1 x 1.6 EN 100 6 7.0 10.5 3.0 3.3 1.4 0 25

EPC1013 LGA 1.7 x 0.9 EN 150 6 100.0 1.7 0.4 0.7 1.4 0 3

EPC1011 LGA 3.6 x 1.6 EN 150 6 25.0 6.7 1.5 2.8 1.4 0 12

EPC1012 LGA 1.7 x 0.9 EN 200 6 100.0 1.9 0.4 0.9 1.4 0 3

EPC1010 LGA 3.6 x 1.6 EN 200 6 25.0 7.5 1.5 3.5 1.4 0 12

4 APPLICATION NOTE

EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2010 | | PAGE10


Appendix A: Low Cost Die Mount Apparatus for EPC GaN Transistors

Pick and Place Station With Vacuum Pump:

XYZ Table with Vacuum pump: Madell Technologies http://www.madelltech.com/xyztable.html

CCD Camera : Swann Security Model HD-420LCD Display: Swann Security Compact 8” LCD Monitor P/N SW248-LM8http://www.swannsecurity.com/

LED Flex Lights: Coast Products Model 7583http://www.ledlenserusa.com

Soldering/De-soldering Station:

Soldering station: HAKKO USA Model FR-803BRe-work fixture: HAKKO USA Model C1392BBoard Pre-preheater : HAKKO USA Model FR-820http://www.hakkousa.com/default.asp

Panavise rapid assembly circuit board holder Model 333http://www.panavise.com

Appendix B: Die Mount Process for Low Volume Assembly of EPC GaN Transistors

To solder:

• Apply a drop of Kester “Tacky Flux” (TSF-6502/6522) to die area with an appropriate syringe. Always apply flux with board at room temperature!• Secure board on pick and place table. • With vacuum on, align die over the footprint between alignment marks, then lower die to contact the board and turn off vacuum to release die.• Carefully move board to soldering station.• Use time/temperature profile in fig 20(a) to solder die.

To de-solder:

• Install board in soldering station, start soldering profile, remove die at stage three with a pair of fine tweezers.• Note: Board preheat settings depend on type of board used – With Pre-heater ~1” below area of board to be soldered: • For 2~4 layer boards (1or 2 oz copper) Use pre-heat setting of 150~200oC.• For 4~8 layer boards (2 oz copper) Use pre-heat setting of 200~250oC.

4 APPLICATION NOTE



REFERENCES

[1] Steve Colino and Robert Beach, “ Fundamentals of Gallium Nitride Power Transistors”, http://epc-co.com/epc/documents/product-training/Appnote_GaNfundamentals.pdf

[2] http://www.kester.com/SideMenu/Products/SphereAttachFlux/TackyFluxes/tabid/235/Default.aspx

[3] Yanping Ma, “EPC GaN Transistor Application Readiness: Phase One Testing”, http://epc-co.com/epc/documents/product-training/EPC_relreport_030510_finalfinal.pdf

[4] Dessi Pak dessicant packs, Sud-Chemie, www.sud-chemie.com

[5] Alex Lidow, “Is it the End of the Road for Silicon?”, http://epc-co.com/epc/documents/product-training/Appnote_Si_endofroad.pdf

[6] 3M pads : http://solutions.3m.com/wps/portal/3M/en_WW/electronics/home/productsandservices/products/TapesAdhesives/ThermalInterface/

[7] Dow Corning Pads: http://www.dowcorning.com/content/etronics/etronicspadsfilm/

[8] Bergquist Pads: http://www.bergquistcompany.com/thermal_materials/gap_pad/pdfs/gap-pad-vo-soft/PDS_GP_VOS_12.08_E.pdf

[9] http://www.mv-group.biz/images/loctite.pdf?nconline=208d580d695356b06651cd3ccceaabfc

[10] [email protected]

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