Asicppts 141015103057 Conversion Gate01

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ASIC DESIGNMODULE - III

ASIC CONSTUCTION : PLACE

PR

HARSHA


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Contents

Introduction

Defnition o placement

Goal and o!"ecti#e

Placement la$out

T$pe o placement

Placement tep

Placement trend%olution&

Reerence


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Introduction

Placement is an essential step in physical design flow since it assigns

for various circuit components within the chips core area. A placer takes a given synthesized circuit netlist together with a tec

and produces a valid placement layout.

Decide the locations of cells in a block.

Selects the specific location for each logic block in the FPA!

minimize the total length of interconnect re"uired.

Placement is much more suited to automation than floorplanning.

Placement is a key step in physical design.

Placement placed in AS#$ design flow step no. % in physical design.


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Placement position in ASIC des!o"


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De#nition o$ placement

E'act placement

o t(e module%module can !e)ate* tandardcell* macro+&.

T(e )eneral )oali to minimi,e t(e

total area andinterconnect cot.


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Placement

T%ere are &arious t'pes o$ placements(

S$tem-le#el placement Place all t%e PC)s toetArea occupied is minimum and *eat dissipation is "

Board-le#el placement All t%e c%ips %a&e to +ePC)( Area is #,ed( All modules o$ rectanular

o+ecti&e is to. minimi/e t%e num+er o$ routin la'e

s'stem per$ormance re0uirements(

/(ip-le#el placement Normall' placement carrie"it% pin assinment


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Placement oals 1 o+ecti&es

Goals

To arrange all the logic cells within the flexible blocks on a

Objectives

Minimize all the critical net delays

Minimize power dissipation

Minimize crosstalk between signals

Minimize the interconnect congestion

Guarantee the router can complete the router step

Minimize the total estimated interconnect length

pecific timing re!uirement for critical nets


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PLACEMENTLA2OUT A3EA

R01 /0NSIST 02 NU3BER 02 SITES1HI/H /AN BE 0//UPIED BY THE/IR/UIT /03P0NENT.

4AY0UT AREA SPE/I2IES THE 2I5HEIGHT 02 R01S.

STANDARD /E44S HA6E A 2I5EDHEIGHT E7UA4 T0 R01S HEIGHT BUTHA6E 6ARIAB4E 1IDTHS.

B40/8S /AN HA6E PREASSIGNED40/ATI0NS.

THIS IS /A44ED 3I5ED 30DEP4A/E3ENT.


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GLO)AL PLACEMENT

T(e )oal o )lo!al placement i to pread* ideall$ 9it( no o#erlap* placet(e )i#en net lit t(at attain o!"ecti#e uc( a 9irelen)t( minimitimin) pecifcation.

Standard cell are placed into )roup t(e num!er o connection !et9een minimi,ed.

T(i i ol#ed t(rou)( circuit partitioni


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Alorit%ms

;. Simulated-annealin) placer

cut placer >

3in cut placer operate in a top-do9n (ierarc(ical a

recuri#el$ partitionin) a )i#en netlit into

1(ere ?@; multi9a$ partitionin)

?; !iection partitionin)

?< :uadriection partitionin)Di#ided into u! ection or !etter reult

i& 3in cut partitioner- ?-9a$ min cut partitionin)

ii& /ut e:uence- cut direction

iii& /apturin) )lo!al connecti#it$- ueul or impro#e place


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DETAILED PLACEMENT ANDLEGALI4E3S

A placement i ille)al i cell or !loc? are o#erlap.

A detailed placer ta?e a le)al placement and impro#e omo!"ecti#e li?e 9irelen)t( con)etion.


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DETAILED PLACEMENT ANDLEGALI4E3S

Goal o detailed placer and le)ali,erRemo#e all o#erlap* and nap cell to ite

minimum impact on 9irelen)t(* timin) and

Impro#e 9irelen)t( !$ reorderin) )roup o

Impro#e routa!ilit$ !$ careull$ ditri!utin)

/laifcation o detailed placement into (euritmet(od.

;& Heuritic met(od t$picall$ ac(ie#e )ood reruntime.


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PLACEMENT STEPS


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Placement trends5solutions6

3i'ed i,e placement

Simultaneoul$ place cell and !loc?. 1(itepace ditri!ution

1(itepace or ree pace i t(e percplacement ite not occupied !$ cell and !l

1(itepace enlar)e t(e core la$out areanecear$ or placement* in order to pro

routin) area. Placement al)orit(m can allocate 9(it

impro#e perormance in a num!er o 9a$con)etion reduction* o#erlap minimi,atimin) impro#ement.

Placement !enc(mar?in)

Etimate t(e proper !enc(mar? 9(ic( de


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Good placement &s( )ad placem

Good placement No con)etion S(orter 9ire 4e metal le#el Smaller dela$ 4o9er po9er diipation

Bad placeme /on)etio 4on)er 9

len)t( 3ore met 4on)er de Hi)(er po

diipatio


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3E7E3ENCES

3ic(ael Smit(* Application Specifc I/ircuitC Pearon Education Aia * c(apte

Andre9 ?a(n) and Reda* di)ital

placementC *c(apter * EDA or I/ implemcircuit dei)n and proce tec(nolo)$.

P($ical dei)n Fo9


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