ASIC Design

Introduction - 1

The history of Integrated Circuit (IC)• The base for such a significant progress

– Well understanding of semiconductor physics– Capability of purifying the material – Fine control of IC manufacture process

• One of the most important inventions in our modern life– IC has changed our life

• Personal computer• Cellular phone• Internet • Wireless communication• Automobile electronics• Medical applications

ASIC Design

Introduction - 2

In 1947, John Bardeen, Walter Brattain, and William Shockley invented the first transistor.

ASIC Design

Introduction - 3

In 1958, Jack Kilby and Robert Noyce invented the first integrated circuit.

ASIC Design

Introduction - 4

ASIC Design

Introduction - 5

Moore’s law

• The performance and density are doubled every 18 months.

• Moore’s law has held for the past 40 year. Let’s look at – Moore’s law in microprocessors – Moore’s law in chip capacity – Die size growth– Wafer size (12 inch)

ASIC Design

Introduction - 6

Moore’s Law in Microprocessors

40048008

80808085 8086

286386

486Pentium® proc

P6

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010

Year

Tran

sist

ors

(M

T)

2X growth in 1.96 years!

Courtesy, Intel

ASIC Design

Introduction - 7

64

256

1,000

4,000

16,000

64,000

256,000

1,000,000

4,000,000

16,000,000

64,000,000

10

100

1000

10000

100000

1000000

10000000

100000000

1980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010

Year

Kbi

t cap

acity

/chi

p

Evolution in DRAM Chip Capacity

1.6-2.4 m

1.0-1.2 m

0.7-0.8 m

0.5-0.6 m

0.35-0.4 m

0.18-0.25 m

0.13 m

0.1 m

0.07 m

human memoryhuman DNA

encyclopedia2 hrs CD audio30 sec HDTV

book

page

4X growth every 3 years!

ASIC Design

Introduction - 8

Die Size Growth

40048008

80808085

8086286

386486 Pentium ® proc

P6

1

10

100

1970 1980 1990 2000 2010

Year

Die

siz

e (m

m)

~7% growth per year

~2X growth in 10 years

Courtesy, Intel

ASIC Design

Introduction - 9

Production year 2002 2003 2004 2005 2006 2007

MPU Gate length (nm)

75 65 53 45 40 35

Clock (GHz) 2.3 3.1 4.0 5.2 5.6 6.7

Metal layers 8 8 8 9 9 9

Supply voltage (V) 1.0 1.0 1.0 0.9 0.9 0.7

International Technology Roadmap for Semiconductors (ITRS)

ASIC Design

Introduction - 10

Technology has moved into the deep submicron (DSM) feature size

– The state of the art technology is 22nm feature size

– Face many new IC design issues due to the increasing performance requirement and DSM feature size

• Design for manufacture (DFM)• New device model• Performance driven design• Distributed circuit parameters• Power dissipation • More powerful CAD tools

ASIC Design

Introduction - 11

Exploding Mask Costs

• Raster scan patterning exposure time for a 110mm x 110 mm mask is 6.5 hrs and 20 hrs with fine granularities (60nm vs. 120nm pixel size)

• Largest cost contribution to mask making is mask exposure time (capital cost ~$20M)

• RET is being absorbed by CAD vendors into layout verification / tape-out suites.

• RET may move up into routing, placementSource: Thomas Weisel Partners

$800K-1.2M $1-2M$500K-1M$200-400KCost

.9µm

2004

.065µm.13µm.18µmNode

200720021999Year

256GB 1024GB64GB16GBData

ASIC Design

Introduction - 12

Power Dissipation

P6Pentium ® proc

486

3862868086

80858080

80084004

0.1

1

10

100

1971 1974 1978 1985 1992 2000Year

Po

wer

(W

atts

)

Courtesy, Intel

Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive

ASIC Design

Introduction - 13

Power Density

40048008

80808085

8086

286386

486Pentium® proc

P6

1

10

100

1000

10000

1970 1980 1990 2000 2010

Year

Po

wer

Den

sity

(W

/cm

2)

Hot Plate

NuclearReactor

RocketNozzle

Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp

Courtesy, Intel

ASIC Design

Introduction - 14

Custom and semi-custom ICs– Custom designed microprocessors, such as Intel

Pentium– Semi-custom designed ICs, such as gate array and

FPGA• Specific circuit structures are introduced to shorten

design cycle • Tread-off between the design quality and design time• ASIC chip usually uses custom design to increase the

performance and to reduce the chip cost• Prototype development usually use the semi-custom

design to reduce the design cycle

ASIC Design

Introduction - 15

Intel Pentium (IV) Microprocessor (custom design)

ASIC Design

Introduction - 16

Design flow

– Traditional design flow• The design tasks usually can be divided into separated

stages• Single direction, usually a top-down strategy

– The interplay between different design tasks becomes important• Physical phenomena and circuit facts should be

considered at high design levels– Floorplanning is a challenge

This chart only presents the basic tasks in the design process.

However, the flow of design tasks is not a single direction.

The influence of the late design stage can affect the early ones.

Design perspectives

ASIC Design

Introduction - 19

CAD tools– Most of today’s IC design are done by using CAD tools.

The major CAD tools are:• Cadence

– good physical design– synthesis

• Synopsis– good high level synthesis– physical layout

• Mentor Graphics– analog IC– verification

• Magma– physical design, good in time closure