ASIC APPROACH OF UART TO BUS INTERFACE IP VERIFICATION · 3Design Engineer,PSK VLSI Design Center,Guntur. 4Director, PSK VLSI Design Center, Guntur mail:[email protected]

JARDCS, ISSN 1943-023X

JARDCS Special Issue on Allied Electrical And Control Systems 1097

Journal of Advanced Research in Dynamical and Control Systems

Special Issue – 02 / 2017

ASIC APPROACH OF UART TO BUS INTERFACE IP VERIFICATION

P.Deepak Chaitanya1, M.S.S.Rukmini

2, Y.Satya Narayana

3, Kishore Prabhala

4

1PG/VLSI student, VFSTR University,Vadlamudi,India.

2Professor, ECE Department, VFSTR University, Vadlamudi, India.

3Design Engineer,PSK VLSI Design Center,Guntur.

4Director, PSK VLSI Design Center, Guntur

mail:[email protected]

ABSTRACT

UART is a structure, which is responsible for implementing Serial Communication

Protocol. UART acts as the intercessor for Serial and parallel interfaces. Proposed design can be

applied for serial communication over a computer accessories and input-output devices. This

paper presents the design of UART to Bus interface and architecture. The UART design has

programmable features for Parser, Baud Generator, Receiver and Transmitter. UART to bus IP

verification is built here to find out whether the verification achieves the expected result or not.

The entire RTL design is coded in Verilog. Simulation results are verified by using 130nm

technology in Mentor graphics Questa sim tool.

Keywords:UART ,Baud Rate ,Parser, Verilog Implementation questa sim 10.4c.

1. INTRODUCTION

Many popular serial communication standards exists, one of them is UART. In present

scenario UART plays a crucial role in sequential communication. It transmit and receive data

through serial port. There are different types of UARTs. They are RS 232,RS 422 and RS 485.



UART'S are used in micro controllers. The function of UART is acts as interface between serial

and parallel communication.

UART stands for Universal Asynchronous Receiver and Transmitter. It has mainly three

blocks, they are baud generator, transmitter and receiver. This internal block of UART helpful to

transmit the data in serial communication. Half duplex Asynchronous protocol is used in UART.

It allows transmitting of signal in both direction but not simultaneously. Since it is half-duplex

communication lanes are completely independent. Depending upon the baud generator,

frequency of both transmitter and receiver are used. It implements error detection in the form of

parity detection. Initially when data is low, transmitter unable to send data to the receiver.

Whenever the start bit is high it will transmit the signal.

According to American Standard Code for Information Interchange(ASCII) eight data bits

can form 256 different combinations. Each character found on the keyboard has a special unique

ASCII code. An UART is preferable when a communication link is required because of its

inexpensive. It is simply asynchronous because no clock signal is required. By using baud

generator single clock signal can be used for transmitter and receiver.

2. DESIGN FLOW

Design Specification is a high level representation of a system. The factors to be

considered in this design are Functionality, Performance, and timing analysis. Behavioral

Description is usually a timing diagram or relationship between units. It is done by using verilog

in Mentor Graphics HDL. Functional verification and testing is done in Questa Sim software and

synthesis is observed by using Leonardo Spectrum.



Figure 1. Design Flow

3. PROPOSED DESIGN

The modules in the proposed UART design are

1. Transmitter

2. Receiver

3. Baud generator & 4. Parser

Each module plays an important role in the serial communication. Where Parser module

implements different commands for UART to Bus design. Each module is explained below.

4. UART to BUS Design

The UART to Bus IP is a simple design. It has mainly two top level modules. In

uart_top module it has mainly three blocks. They are transmitter, receiver and baud generator.

Other module is uart2bus_top.In uart2bus_top module Parser block can be used to access an

internal bus via a UART interface. During debugging this core can be used initially. It is

designed with data bus of 8 bits and address bus of 16 bits.

UART core includes mainly command parser interface, transmitter and receiver. It uses

only five signals between “uart_top.v” modules and “uart_parser.v”module.For different cases

uart_top module is not possible, other interface is required. Where uart_parser.v module can be



used with in a different interface implementation. It uses different parser commands for different

cases. When data is send from transmitter to receiver, it will wait for the int request.

Figure 2. UART to bus design block diagram

The four components of UART are explained in detail.

4.1. UART TRANSMITTER

UART Transmitter objective is to convert 8 bits into single bit. Initially to transmit the

information which is stored in the hold register is shifts into shift register. Once shift signal is

high, the transmitter output is serves as the receiver input. Similarly remaining bits follow the

same path and serves as receiver input. Transmitter will provide a parity bit, when complete

information is sent then it will accepted by the receiver. From fig.3 transmitting data is D0-D7

and „P‟ is the parity bit. Transmitter will generate a bit stream based on its clock signal, and then

receiver's goal is to use its internal clock signal to sample the incoming data in the middle of

each bit period. The transmitter output carries serial data to another device on serial bus. It

converts data from parallel to serial format. It calculates and insert parity bit is required. Later it

will send to the receiver.RTL view of Transmitter can be observed in fig 4.

Figure 3. Transmitting data



SIMULATION RESULTS

Figure 4. TRANSMITTER RTL SCHEMATIC

4.2. UART RECEIVER MODULE

Receiver module function is to store the transmitter output data. When initial load signal

is high transmitter will sent data to receiver by providing int_request and receiver will accept as

input. Working of UART depends on baud clock signal and runs at variable data rate. After

receiving the information from the transmitter, receiver module will send an int_grant to

transmitter as acknowledgement. It‟s like a „handshake‟ between the transmitter and receiver

module. Spurious pulse is ignored by receiver. After the character length of 5 to 8 bits typically

elapsed, shift registers are available to receiver system. After receiving the data from transmitter,



busy grant is done and it is observed from fig 5.The clock frequency of both initial timing and

final timing is same in receiver module.

Figure 5. RECEIVER SIMULATION RESULT

RECEIVER RTL SCHEMATIC



4.3. BAUD GENERATOR

Baud generator is a clock generator which contains free running counters. It contains

internal x16 clocks, baud 16 signals. It provides timing information for both transmitter and

receiver. Baud clock frequency is 16 times of baud rate. Where Baud Rate stands for no of pulses

per sec. Baud rate states that how speed the data is sent in a sequential line. It is generally

represented in no of bits per sec. By improving the Baud rate, time taken to transfer the data

decreases and we can observe time taken for a single bit.

Based on application baud rate will be varied. It can be any value within a reason. The main

purpose of using baud generator is both the modules operate at same baud rate. Most common

baud rates used in serial communication are 9600, 384000, 57600 and 115200 bps. From fig 6.

baud generator simulation can be observed.

Figure 6. BAUD GENERATOR SIMULATION RESULT



RTL SCHEMATIC OF BAUD GENERATOR

4.4. PARSER MODULE

Parser module explains about the protocol used to access internal bus from UART

interface. Parser supports mainly two modes of protocols. It can be better explained by using the

state flow diagram. The right side of flow graph explains about the text mode protocol and left

side explained about binary mode. Parser will abort the illegal sequences in the state flow

diagram. Initially it is in idle state.



Depending upon the white space character, data and address are defined. When the data is send,

carrier return or line feed is passed to the End Of Line(EOL). Text mode protocol requires

special characters to change the data from ASCII.

The protocols are explained below:

1. Text Mode

2. Binary Mode

4.4.1. TEXT MODE PROTOCOL

The right side of the state flow diagram explains about the text mode. It includes only two

commands. They are address read and address write. In text mode all values are in Hex format.

The Parser function is to check the initial data on the right side. It will check and detects the

white space, line feed and carrier returns. It detects both space (0*20) and tab (0*09) as white

space. The commands which are not following the protocol sequence are aborted.

On the reception the data which is on the white space as address read and it will write to

the address write. After both commands completed it will send to the end of line. The entire

mode is in the form of ASCII. It takes more time when compared to binary mode.



Features:

1. All values in HEX format.

2. Address Read command.

3. Read 'R' or 'r'.

4. White space is used for single or multiple.

5. Address to read in 4-digit HEX.

6. Address to write in 4-digit HEX.

7. Data to write in 2-digit HEX.

8. CR or LF character.

4.4.2. BINARY MODE PROTOCOL

The binary mode protocol takes less time when compared to the text mode. Since it

doesn‟t need to convert from ASCII, it is more efficient. Binary mode uses a single command

either read or writes. Different test cases are used to test the data in binary mode from fig 7.

Parser simulation result can be observed. There is no delay in the receiver section during

synthesis.



Figure 7. PARSER SIMULATION RESULT

PARSER RTL SCHEMATIC

UART TO BUS SIMULATION RESULT



UART TO BUS RTL SCHEMATIC

TABLE 1. COMPARISION BETWEEN EXISTING DESIGN AND PROPOSED DESIGN

Serial

no

Parameters Existed design Proposed design

1. Frequency 107.082M.hz 109M.hz

2. Gate count 3558 4249

3. Baud rate 20Kbps 115.2Kbps

4. Most critical slack 0.5 0

Critical slack is the longest delay



4. CONCLUSION

By observing the existing and proposed design we conclude that there is a difference in

baud rate, frequency, gate count and most critical slack. By improving the baud rate time taken

to transfer the data decreases, so it‟s applicable in faster communication. The simulation results

are quite constant and reliable. Parser in the UART design becomes more firm and produces high

bits per sec.

5. FUTURE SCOPE

In existing system there is one baud rate one data width. Variable baud rate and variable

data width can be implemented in future implementation UART models by using “Multichannel

UART”. FPGA Implementation on multi channel UART is cost effective. Due to the

reprogrammable feature of FPGA, code can be modified and rewritable depending upon the

application. There is a wide scope in future electronics for UART devices including single

UART s, quad UARTs, octal UARTs and USART devices.

6. REFERENCES

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Asynchronous Receiver and Transmitter(UART)Design and & Implementation By

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2. Amanpreet Kaur, Amandeep Kaur, "An approach for Designing a Universal

synchronous Receiver Transmitter(UART)",International Journal of Engineering

Research and Applications. Vol.2, Issue 3, May-Jun 2012.

3. Tanmay Sandeep Singh Rawat, & Prof.Vishal Ramola, "UART Design using FIFO

ram and LCR circuit with BIST capability at different baud rate", International

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4. Neha R.Ladda and Prof.A.P.Thakare, "Implementation of serial communication

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Innovation Trends in Computing and Communication ISSN 2321-8169 Volume: 1

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Documents

ASIC APPROACH OF UART TO BUS INTERFACE IP VERIFICATION · 3Design Engineer,PSK VLSI Design Center,Guntur. 4Director, PSK VLSI Design Center, Guntur mail:[email protected]