•  Objectives

–  VLSI technology trend

–  Design challenges

–  Custom and semi-custom VLSI

–  System-on-a-Chip and IPs

–  Design domain and perspective

–  Design tasks

–  Design flow

•  One of the most important indicators in measuring the level of VLSI advancement is the so-called feature size. –  It indicates how fine a process can be achieved in

producing a geometric component in a chip, for instance, the separation between two interconnects or the width of a wire segment.

•  A more proper measurement, half-pitch, is adopted on the roadmap of IC development. –  Although this measurement is more specific for the layer or

the type of the device, providing a more accurate measure of the technology, there is no fundamental difference from the traditional notion of the feature size.

•  Definition of pitches (ITRS, 2009)

•  Improvement trends for ICs enabled by feature size scaling (ITRS, 2009)

•  Most of these trends have resulted from the industry’s ability to exponentially decrease the minimum feature size (or half-pitch) used to fabricate integrated circuits.

•  Another frequently cited trend is the level of integration, which is usually expressed as Moore’s Law (the number of components per chip doubles roughly every 18 months).

•  The penetration of IC into our lives has brought many new varieties of applications, which cannot be encompassed by Moore’s Law.

•  Moore’s Law measures the number of devices in a chip, but it can hardly describe the variety of chips and systems built upon them.

•  In the past decade, the development of System-on-a-chip and System-in-Package (SiP) technologies has greatly increased the capability of integration, and further broadened the IC application.

•  As far as the number of the devices integrated into a chip is concerned, the major enabler is CMOS technology, despite being considered a “die-hard” technology.

•  In the nanometer regime, such as with the 22nm process, the accuracy of lithography has reached a fraction of the light wavelength.

•  Further improvement has been limited by the laws of physics. As such, there is a great concern about the situation “beyond CMOS”.

•  At the moment, the answer to this question is still unclear.

•  The ITRS roadmap has been considered the most complete and accurate open source information for the research and development (R&D) of integrated circuits and the IC industry’s future trends.

–  ITRS updates its roadmap regularly and the roadmap can be found on its website.

•  People in this area should visit this site regularly to obtain information on state-of-the-art IC technology.

•  VLSI design is no longer a pure hardware issue, and also involves software development.

•  The previous figure shows the cost comparison between hardware and software development spent in each categories.

•  Hardware and software co-design has been necessary in most advanced digital system development, especially in the development of SoC where high level IPs, different type functional blocks, system protocols and operation systems need to be realized in a single chip.

•  SoC provides a platform for extending Moore’s law in the dimension of diversity.

•  An SoC consists of not only a collection of hardware blocks, such as a microcontroller, microprocessor or DSP cores, peripherals and interfaces, but also the software which control these hardware blocks.

•  Most SoCs are developed from pre-qualified hardware blocks for the hardware elements along with the software drivers that control their operations.

•  The hardware blocks are put together using CAD tools; the software modules are integrated using a software development environment.

•  Microcontroller-based system-on-a-chip

•  SoC design flow is much more complicated than a traditional IC design process. –  Hardware and

software co-design is heavily involved.

–  In many cases the IPs come from different IC vendors and the model and interface protocols are often inconsistent with each other.

–  Signals usually have to pass through several clock domains, which in turn requires very cautious design.

•  A custom designer in principle can end up designing most circuit blocks from scratch for a particular application.

–  Considering the work involved in logic, circuit, layout, and verification, this would easily result in a very long design cycle and high design cost.

•  To reduce the design cycle and cost, semi-custom design methodology was introduced.

–  With this method, some or all components are pre-designed or even pre-fabricated such that design effort for an application can be shifted to a higher level.

•  Custom and semi-custom designs

•  Gate Array –  Gate array is a widely used approach for the design and

manufacture of ASICs.

–  A gate array circuit is a prefabricated chip with no particular function, in which transistors, standard NAND or NOR logic gates, and other active devices are placed at regular predefined array positions and manufactured on a wafer, usually called a master slice.

–  Creation of a circuit for a specified function is accomplished by adding a few layers of metal interconnects on top of the master slice late in the manufacturing process, joining the elements in the array cells to allow the function of the chip to be customized as desired

–  Gate array master slices, usually in several families containing different number of logic gates, are prefabricated in large quantities regardless of customer orders.

–  The design and fabrication according to the individual customer specifications may be finished in a shorter time compared with a full custom design, because there is no need to design the low level masks for the transistors.

–  The gate array approach reduces the mask costs because fewer custom masks need to be produced.

–  In addition, manufacturing test tooling lead time and costs are reduced since the same test fixtures may be used for all gate array products manufactured on the same die size.

•  A view of gate array and its cells

•  Standard Cell

–  When the adjacent gate array cells are pushed one against the other horizontally and the vertical channels between them diminish, the result is a standard cell technology.

–  Standard cell works very much the same way as the gate array, and currently it is not distinguished from gate array without specific need.

•  A view of standard cell technology

•  Cell library –  ASIC foundries will provide a technology library of cells, which

contains multiple implementations of the same logic function that differ in area and speed.

–  The cells in the library are characterized and modeled in detail in terms of speed, power consumption, fan-in and fan-out limit, geometric shape and size, etc.

–  The variety found in the cell library enhances the efficiency of automated synthesis, place and route (SPR) tools. It also gives the designer more freedom to perform implementation tradeoffs, such as area vs. speed vs. power consumption.

–  The technology library, along with a design netlist format, is the basis for exchanging design information between different phases of the SPR process.

•  Synthesis

–  The logic synthesis tool maps the ASIC's register-transfer level (RTL) description into a technology dependent netlist.

–  The netlist is the standard cell representation of the ASIC design at the logical view level. It consists of instances of the standard cell library gates and port-connectivity between gates.

–  Proper synthesis techniques ensure logical equivalency between the synthesized netlist and the original RTL description.

–  During the mapping process certain optimization objectives are considered, such as the signal delay constraint or usage of the minimal number of gates.

•  Placement –  The placement tool starts the physical implementation of the

ASIC. •  The placement tool assigns locations for each gate in the netlist.

•  The resulting placed gates netlist contains the physical location of each of the standard cells in the netlist, but retains an abstract description of how the gates’ terminals are wired to each other.

–  Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows on the integrated circuit.

•  Such arrangement greatly eases the complexity of the layout, since the size difference of the cells are accommodated by the cell width and routing can be done in a simple rectangular channel.

•  Technology mapping and placement of standard cells

•  Routing

–  Using the placed gates netlist and the layout view of the library, the router adds both signal connect lines and power supply lines.

–  The fully routed physical netlist contains the listing of gates from synthesis, the placement of each gate from placement, and the drawn interconnects from routing.

•  The following figure is a standard cell layout example, in which there are two metal layers indicated by pink and blue respectively.

•  Field Programmable Gate Array –  A field programmable gate array (FPGA) is a semiconductor

device that can be configured by the customer or designer after manufacturing - hence the name “field-programmable”.

•  Compared to a gate array or standard cell, the interconnect wire segments are pre-designed and manufactured in addition to the logic gates. Between the wire segments are programmable switches.

–  FPGAs are programmed according to an application logic circuit netlist or a source code in a hardware description language (HDL) which specifies how the chip will work.

•  They can be used to implement any logical function of an ASIC.

–  The ability to update the functionality after shipping offers advantages for many applications.

•  An illustration of FPGA structure

•  An example island-style FPGA routing architecture

•  VLSI design perspective

–  VLSI design perspective is often represented by the well-known Y-chart.

•  The Y-chart looks at the design from three different angles: structure, behavior and physical domains, respectively.

•  The descriptions in the same circle represent the same abstraction level of a design issue but from different domains.

–  For instance, a Finite State Machine (FSM) in the behavior domain corresponds to a functional block in the structural domain, and to a module in the physical domain.

•  Design domains and perspective

•  In the behavior domain, we do not look at the hardware issues, such as functional block or size. The goal is to start from a specification and refine it step by step until all operations are defined and scheduled correctly.

•  In the structural domain, we are interested in developing the architecture of a system and implementing each functional block with suitable lower level logics and circuits.

•  In the physical domain, we place geometric modules in such a way that the resultant chip area is minimized. In this domain, we are also concerned with whether design rules and performance issues such as signal delay/integrity are satisfied.

•  Along any axis of the Y-chart, a design process is neither a simple top-down nor bottom-up process.

•  It usually starts from the top of the axis and moves down, and stops somewhere around the middle. It then starts from the bottom of the axis and moves up until it meets the previous stop point.

•  Top-down and bottom-up design process

•  Most designers go through the top-down design process

•  In real ASIC design practice, lower level cells, logics and frequently used functional units are reused for different applications. –  They are well designed and characterized, and stored in a cell

library. –  We do not have to redesign them every time, except for a few

special logic circuits related to the particular application.

•  Most design processes start from the behavior description and move top-down to the RTL level, selecting existing functional blocks from the cell library.

•  Designers often go through a top-down design process. •  The bottom-up lower level design is not obvious because these

tasks are taken care of by the cell library.

•  Sequence of design tasks

•  An ASIC designer usually works at the top-levels of the Y-chart.

•  When connecting the tasks in these top-levels we find a natural sequence of design tasks.

•  A basic ASIC design flow

•  The above basic design flow is somehow over simplified in the sense that it only connects the design tasks in one direction. –  Interactions between different stages, especially the influences of

later stages on earlier ones, are not shown.

•  In reality, a design cannot be done in such a singular path. –  If the timing analysis finds that the delay of the critical path is

longer than that required by a clock period, we have to go back to the physical design to modify the layout.

–  If the problem cannot be resolved inside the physical design stage we then have to go back further to the circuit design to add buffers.

–  If we cannot resolve the problem through the modification of physical or circuit design, we would have to go back another stage to change the architecture design.

•  Most interference between different design stages is actually due to system performance requirements and variable remitting solutions at different stages.

–  As a consequence, we need to have loops in the design flow.

•  In general we want to go backward as little as possible.

–  A subsequent problem is that we might be end up cycling through these stages endlessly.

–  This issue is called timing closure

•  Loops in the design flow

•  An industrial VLSI design flow example

•  Verification and testing

•  System specifications

–  A real ASIC design practice starts from understanding the application and writing a clear and complete specification in terms of VLSI terminology, such as input/output signals, clock rate, protocol definition, operation mode and etc.

–  This is one of the most challenging issues for ASIC designers, especially for students who usually do not have such training in real working environment.

–  We pay special attention to this issue and uses a real ASIC design project to guide readers through this process step-by-step

•  Writing a specification for an ASIC project includes

–  Understanding the application

–  Communicating with custom for whom ASIC chip is designed

–  Converting application terminology into circuit design terminology

–  Defining system settings

–  Listing the performance criteria, and

–  Selecting the process

•  Architecture design –  Architecture probably plays the most important role in

determining the quality of a designed chip. •  Experience in IC design and insight into the application

contribute to the architecture choice.

•  Currently, architecture design still depends on the wisdom of the designer instead of on CAD tools, since there are too many factors involved.

– Unfortunately the influence of different factors usually conflicts with each other.

–  This is another focus point: addressing the complex issue such that the reader can learn how to integrate basic functional blocks and clock the operations properly.

•  Logics and circuits

–  Logic and circuit design are used to implement the functional blocks specified in the architecture.

–  For a given function there is more than one logic and circuit implementation option.

–  A designer can chose a proper implementation using the small chip area, short delay, and low power consumption criteria.

–  This task in most cases can be automated by using today’s CAD tools.

–  However, designing good logic components based on a particular manufacture process and requirement is still a “hand-made” matter.

•  Physical layout –  Physical design is a process that includes the placement of

circuit elements, with certain sizes and shapes, into a 2-dimentional surface and connecting them, in several routing layers, according to the netlist obtained from the logic/circuit design.

–  Usually, CAD tools handle this task. •  Considering the fact that the physical layout has a significant

impact on circuit performance, such as might be measured by signal delay and crosstalk, the designer’s interference is still needed.

•  Notably, at the floorplan level many decisions are made based on intuition rather than rigid mathematics.

•  Engineering change order (ECO) requirements are also usually responded to manually.

–  The layout impact on performance becomes more obvious as the process moves into a nanometer scale feature size, such as in the 22nm to 60nm range, where crosstalk, substrate noise, power density are critical to circuit performance and reliability.

•  Timing, power and performance analysis –  Timing, power and performance analysis are necessary for any

design.

–  An ASIC chip might be correct in terms of logics, but will not work properly if its timing is wrong.

•  For instance, a chip can’t run at the expected clock rate if the critical path delay is longer than what the clock period permits.

–  Most, if not all, ASIC chips will have certain constraints on power consumption and performance.

•  Only after the layout is completed can these criterions be evaluated in a relatively accurate sense, since up to this point parasitic parameters have been available when needed for timing, power and performance analysis.

–  Testing involves two issues: one is the so-called design for testing and the other is the testing of fabricated chips.

•  The first issue requires the design of special circuit properties such that one can observe signals at the nodes of interest from the chip output.

–  It also requires the generation of corresponding input driving vectors since we can’t use a probe to reach an internal node to send or receive a signal.

•  The second issue is addressed by inserting extra testing circuits, which allow us to isolate functional blocks.

–  The most popular circuit for this purpose is the boundary scan circuit, which selects the input/output of the flip-flops to test if the combinational logic block or flip-flops work properly.

•  Verification and testing –  Verification and testing ensure the correctness of a design and

help find defects introduced by manufacture process. –  Verification is usually carried out through simulation, although

formal verification is used in some high-end microprocessor design.

–  Verification needs to be addressed at each level of the design process, including the system, functional/logical, circuit, and physical layout levels. •  CAD tools can assist a designer in doing this; for instance, SPICE

can run a circuit level simulation to see the waveform of a concerned signal.

•  It is still the designer’s decision to specify the inputs, outputs, and the necessary settings to see the features of a concerned signal or functionality.

•  We have looked at the VLSI technology trend and its broad application potential in everyday life via SoC.

•  We have studied different design styles, gate array, standard cell, FPGA and full custom design, and elaborated their pros and cons.

•  By analyzing the design domain we come up with a natural ASIC design flow.

•  The chapter further outlined the content of each task in the design flow.

•  In the following chapters we shall discuss these design tasks in details.

1.  Find out how many routing layers are available for today’s advanced VLSI process, and explain how each layer is used.

2.  What is high level synthesis in VLSI design? Give an example.

3.  What is the critical path delay in a digital circuit design? What is its relationship with clock rate?

4.  Explain the terminology of time closure in VLSI design. Given an example to illustrate this issue.

5.  What is the behavior model of a digital system? Use an example to present your answer?

6.  Study the design flow that uses FPGA. Describe the tasks and criteria used in the design.

7.  Describe in detail the process of technology mapping when using standard cell technology in a design. Give an example.

8.  Explain the difference between combinational and sequential circuits. Give a generic circuit structure of sequential circuit.

9.  What is the FSM and give an example.

10.  What is the logic synthesis? Give an example.

11.  Find out a “real industrial design flow” and explain how it works.