ArrowDevices M-PHY Verification Checklist

Sheet1SMAP SECTION CATEGORY LOGNAME TESTNAME TEST DESCRIPTIONERR M-PHY ERROR transfers COMPLIANCE compliance_mphy_sync_pattern_width_corrupt.log mphy_sync_pattern_width_corrupt_testSYNC Pattern error injection Injecting the Errors in encoded Control symbols. SYNC pattern corruption keeps the width same as spec defined values but corrupts the pattern SYNC pattern width exceeds or sends lesser than specification defined width Stimulus: Randomly Corrupt the 8b/10b encoded control symbol values before driving it on the DP/DN lanes.

RESET MPHY RESET Cases COMPLIANCE compliance_mphy_line_reset_during_ls_burst.log mphy_line_reset_during_ls_burst_testLINE-RESET at different speed and state with TX_Controlled_ActTimer Lowest level reset mechanism in order to reset the M-RX via the LINE during operation in case of malfunction. LINE-RESET condition is a long DIF-P period, which can never occur during normal operation.Stimulus: LINE-RESET can be initiated by the Protocol Layer on the M-TX side of a LINK using the M-CTRL-LINERESET.request primitive Value of TX_Controlled_ActTimer is one

*NOTE : This LINE-RESET should be done in all ACTIVATED states.

Expectations : - M-TX drives DIF-N for TACTIVATE before driving the LINE-RESET condition - LINE-RESET exits to SLEEP on a transition to DIF-N. - Exit of LINE_RESET should go to SLEEP state.

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_ls_G5_to_hs_G3.log mphy_ls_G5_to_hs_G3_testMPHY INTER MODE_CHANGE Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument

Expectation :

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_mphy_hs_burst_with_hs_G2_in_DigitalEnd_loopback_mode.log mphy_hs_burst_with_hs_G2_in_DigitalEnd_loopback_mode_testDigitalEnd loopback tests

Stimulus:


Expectation :

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_mphy_hs_G1_hs_burst_with_TX_lanes_3_and_RX_lanes_4.log mphy_hs_G1_hs_burst_with_TX_lanes_3_and_RX_lanes_4_testMulti-lane tests (taffic on all lanes)

Stimulus:

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_ls_intra_mode_G6_to_G7.log mphy_ls_intra_mode_G6_to_G7_testMPHY LS INTRA MODE_CHANGE Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument

Expectation :

DATA_XFER M-PHY - RANDOM TEST CASES RANDOM rand_mphy_mode_test_uvm.log mphy_tb_random_mode_testM-PHY RANDOM SPEED MODE TEST -- Running MPHY in different modes(LS and HS) randomly, enter and exit from hibern8 randomly. -- Bursts are performed with random gear values to cover all speed grades. -- writing in configuration registers during burst which will be updated after transiting in a save state. -- Randomizing the HS_PREPARE_LENGTH value from minimum to maximum values. Stimulus: --

Expectation : -- All the transactions should be completed without any failure.

DATA_XFER M-PHY DATA transfers COMPLIANCE compliance_mphy_hs_G2_SB_burst_xfer.log mphy_hs_G2_SB_burst_xfer_testData transfer in HS Burst with all gears Normal Data transfer in BurstsStimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts.

Expectation : Between the bursts the M-PHY StateMachine should wait in the STALL State. Data integrity on the Peer RMMI interface.

FSM_TR M-PHY state transition COMPLIANCE compliance_mphy_state_transition_from_ls_burst_to_line_cfg.log mphy_state_transition_from_ls_burst_to_line_cfg_testState transition from LS_BURST to other states Mphy state transition from LS_BURST to other states

Stimulus:

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_mphy_PWM_G1_ls_burst_with_TX_lanes_4_and_RX_lanes_1.log mphy_PWM_G1_ls_burst_with_TX_lanes_4_and_RX_lanes_1_testMulti-lane tests (taffic on all lanes)

Stimulus:

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_hs_G1_to_ls_G1.log mphy_hs_G1_to_ls_G1_testMPHY INTER MODE_CHANGE Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument

Expectation :


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Expectation :

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_rmmi_cntl_if_wr_tx_rx_in_stall_state_wo_inlncfg.log rmmi_cntl_if_wr_tx_rx_in_stall_state_wo_inlncfg_testRMMI Control IF Write in different states without RX_InLnCfg RMMI Control I/F Writes on TX & RX interface in different states without RX_InLnCfgStimulus:

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_burst_hs_G3_HS_PREPARE_length_0.log mphy_burst_hs_G3_HS_PREPARE_length_0_testdata transfer with typical value of prepare Normal Data transfer in ls and hs mode with typical values of prepare lengthStimulus:

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_mphy_ls_burst_with_PWM_G6_in_NearEnd_loopback_mode.log mphy_ls_burst_with_PWM_G6_in_NearEnd_loopback_mode_testNearEnd loopback tests

Stimulus:

DATA_XFER M-PHY DATA transfers COMPLIANCE compliance_mphy_ls_PWM_G0_max_burst_xfer.log mphy_ls_PWM_G0_max_burst_xfer_testData transfer in LS Burst with all gears Normal Data transfer in BurstsStimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts.

Expectation : Between the bursts the M-PHY StateMachine should wait in the SLEEP State. Data integrity on the Peer RMMI interface.

FSM_TR M-PHY state transition COMPLIANCE compliance_mphy_state_transition_from_stall_to_sleep.log mphy_state_transition_from_stall_to_sleep_testState transition from STALL to other states Mphy state transition from STALL to other states

Stimulus:

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_burst_ls_G1_LS_PREPARE_length_0.log mphy_burst_ls_G1_LS_PREPARE_length_0_testdata transfer with typical value of prepare Normal Data transfer in ls and hs mode with typical values of prepare lengthStimulus:

RESET MPHY RESET Cases COMPLIANCE compliance_mphy_reset_during_hs_burst.log mphy_reset_during_hs_burst_testTX / RX RESET at different state and speeds Apply the reset in Different state of module

Stimulus: Apply the Reset to TX or RX with a random delay between them and see that TX & RX will come back to HIBERN8 after the reset release. All the registers have degault values.

DATA_XFER M-PHY - TEST MODES CASES COMPLIANCE compliance_mphy_rx_to_tx_loopback_bfm.log mphy_rx_to_tx_loopback_bfm_testMPHY RX-to-TX LOOPBACK IN BFM RX-to-TX LOOPBACK By Enabling the Loopback mode the incoming data on RX can be transmitted on TX path before the decoding is done. Stimulus: -- Enable the RX-to-TX Loopback in BFM.

Expectation : -- Check the Data sent from DUT is recieved without any Errors by DUT.

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_burst_ls_G7_with_min_tob.log mphy_burst_ls_G7_with_min_tob_testdata transfer with typical values of TOB ls and hs burst Normal Data transfer in ls and hs mode with typical values of TOB Stimulus:

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_burst_ls_G7_SYNC_length_0_SYNC_range_1.log mphy_burst_ls_G7_SYNC_length_0_SYNC_range_1_testdata transfer with typical values of sync length and sync range Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:


Expectation :


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Expectation :

DATA_XFER M-PHY DATA transfers COMPLIANCE compliance_mphy_ls_PWM_G7_min_burst_xfer.log mphy_ls_PWM_G7_min_burst_xfer_testData transfer in LS Burst with all gears Normal Data transfer in BurstsStimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts.


ERR M-PHY ERROR transfers COMPLIANCE compliance_mphy_TOB_corrupt.log mphy_TOB_corrupt_testTOB corruption Injecting the Errors in encoded Control symbols.Stimulus: Randomly Corrupt the 8b/10b encoded control symbol values before driving it on the DP/DN lanes. +INJECT_MPHY_TOB_SYMBOL_ERR=1

ERR M-PHY ERROR transfers COMPLIANCE compliance_mphy_DIF_P_hibern8.log mphy_DIF_P_hibern8_testDIF_P in HIBERN8 state -- MPHY DIF_P in HIBERN8 stateStimulus: Randomly insert DIF_P in HIBERN8 state





FSM_TR M-PHY state transition COMPLIANCE compliance_mphy_state_transition_from_sleep_to_hibern8.log mphy_state_transition_from_sleep_to_hibern8_testState transition from SLEEP to other states Mphy state transition from SLEEP to other states

Stimulus:


Expectation :

RESET MPHY RESET Cases COMPLIANCE compliance_mphy_reset_during_hs_sync.log mphy_reset_during_hs_sync_testTX / RX RESET at different state and speeds Apply the reset in Different state of module



Stimulus:


Expectation :

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_mphy_ls_burst_with_PWM_G5_in_DigitalEnd_loopback_mode.log mphy_ls_burst_with_PWM_G5_in_DigitalEnd_loopback_mode_testDigitalEnd loopback tests

Stimulus:

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_burst_hs_G2_SYNC_length_15_SYNC_range_1.log mphy_burst_hs_G2_SYNC_length_15_SYNC_range_1_testdata transfer with typical values of sync length and sync range Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:





FSM_TR M-PHY state transition COMPLIANCE compliance_mphy_state_transition_from_hs_burst_to_line_cfg.log mphy_state_transition_from_hs_burst_to_line_cfg_testState transition from HS_BURST to other states Mphy state transition from HS_BURST to other states

Stimulus:



DATA_XFER M-PHY - JITTER & PPM Cases COMPLIANCE compliance_mphy_rnd_xcess_ppm.log mphy_rnd_xcess_ppm_testMPHY PPM ERROR Cases ( If DUT Supports it ) ( in one million ideal clocks period ) This happens due to the minute error in the crystal Oscillating frequency. Induce the PPM (exceeding the limits ) On TX CLK Stimulus: By Enabling the ppm ( exceeding the limits) on the Clock of TX. +INJ_EXCESS_PPM = (NONE, POS, NEG, RAND)

Expectation : Thresholds of the Shallow FIFO's should exceed when WR clk is faster. Shallow FIFO should become empty when RD Clk is faster.

RESET MPHY RESET Cases COMPLIANCE compliance_mphy_rx_reset_removal_while_tx_in_sleep.log mphy_rx_reset_removal_while_tx_in_sleep_testRX wakeup cases Stimulus: Remove the reset from RX when 1.TX is in HIBERN8, 2.TX is in sleep


Expectation :


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Stimulus:


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REG_W/R M-PHY Control transfers COMPLIANCE compliance_mphy_reg_wr_rd.log mphy_reg_wr_rd_testRegister Write / Read Transfers Register Write / Read Transfers

Stimulus: Do the Register Write/Read operations in RTL for MPHY Registers thriugh the RMMI CNTL interface Valid Addr range : 'h0001 -to- 'h00E6

** NOTE ** NOT Applicable for BFM


DATA_XFER M-PHY - MODE/GEAR/SERIES/DATA BUS/PATTAREN LENGTH/SYNC LENGTH CHANGE CASES COMPLIANCE compliance_mphy_hs_intra_mode_G2_to_G1.log mphy_hs_intra_mode_G2_to_G1_testMPHY HS INTRA MODE_CHANGE Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR/SERIES Change.

Expectation :


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FSM_TR M-PHY state transition COMPLIANCE compliance_mphy_state_transition_from_sleep_to_stall.log mphy_state_transition_from_sleep_to_stall_testState transition from SLEEP to other states Mphy state transition from SLEEP to other states

Stimulus:


Expectation :




Expectation :

ERR M-PHY ERROR transfers COMPLIANCE compliance_mphy_DIF_Z_burst.log mphy_DIF_Z_burst_testDIF_Z in BURST state -- MPHY DIF_Z in BURST state

Stimulus: Randomly insert DIF_Z in BURST state


Stimulus:

DATA_XFER M-PHY - JITTER & PPM Cases COMPLIANCE compliance_mphy_neg_jitter.log mphy_neg_jitter_testMPHY JITTER Cases Induce the Jitter On TX CLK Stimulus: By Enabling the jitter on the Clock of TX. +INJ_JITTER = (NONE, POS, NEG, RND)

Expectation : No Data Loss*NOTE* : Random permissible Jitter should be part of all Test cases.

RESET MPHY RESET Cases COMPLIANCE compliance_mphy_line_reset_during_hs_prepare.log mphy_line_reset_during_hs_prepare_testLINE-RESET at different speed and state with TX_Controlled_ActTimer Lowest level reset mechanism in order to reset the M-RX via the LINE during operation in case of malfunction. LINE-RESET condition is a long DIF-P period, which can never occur during normal operation.Stimulus: LINE-RESET can be initiated by the Protocol Layer on the M-TX side of a LINK using the M-CTRL-LINERESET.request primitive Value of TX_Controlled_ActTimer is one



FSM_TR M-PHY state transition COMPLIANCE compliance_mphy_state_transition_from_sleep_to_ls_burst.log mphy_state_transition_from_sleep_to_ls_burst_testState transition from SLEEP to other states Mphy state transition from SLEEP to other states

Stimulus:


Expectation :

FSM_TR M-PHY state transition COMPLIANCE compliance_mphy_state_transition_from_stall_to_hibern8.log mphy_state_transition_from_stall_to_hibern8_testState transition from STALL to other states Mphy state transition from STALL to other states

Stimulus:

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_rmmi_cntl_if_rd_tx_rx_in_sleep_state.log rmmi_cntl_if_rd_tx_rx_in_sleep_state_testRMMI Control IF Read in all states RMMI Control I/F Reads on TX & RX interface with random attribute ID

Stimulus:

ERR M-PHY ERROR transfers COMPLIANCE compliance_mphy_data_8b_10b_corrupt.log mphy_data_8b_10b_corrupt_testData Encoding Error Injecting the Data Errors while encoding.Stimulus: Randomly Corrupt the 8b/10b encoded data values before driving it on the DP/DN lanes. +INJECT_MPHY_DATA_SYMBOL_ERR=1 +INJECT_MPHY_DATA_SYMBOL_ERR_PC= (


Expectation :

DATA_XFER M-PHY - JITTER & PPM Cases COMPLIANCE compliance_mphy_pos_jitter.log mphy_pos_jitter_testMPHY JITTER Cases Induce the Jitter On TX CLK Stimulus: By Enabling the jitter on the Clock of TX. +INJ_JITTER = (NONE, POS, NEG, RND)



Expectation :


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DATA_XFER M-PHY - TEST MODES CASES COMPLIANCE compliance_mphy_rx_to_tx_loopback_dut.log mphy_rx_to_tx_loopback_dut_testMPHY RX-to-TX LOOPBACK IN DUT RX-to-TX LOOPBACK By Enabling the Loopback mode the incoming data on RX can be transmitted on TX path before the decoding is done. Stimulus: -- Enable the RX-to-TX Loopback in DUT.

Expectation : -- Check the Data sent from BFM is recieved without any Errors by BFM.


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Stimulus:

ERR M-PHY ERROR transfers COMPLIANCE compliance_mphy_DP_DN_same.log mphy_DP_DN_same_testDIF-P and DIF-N having Same value DIF-P and DIF-N having Same value

Stimulus: Randomly do DIF-P and DIF-N having Same value






REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_rmmi_cntl_if_wr_tx_rx_in_hibern8_state_wo_inlncfg.log rmmi_cntl_if_wr_tx_rx_in_hibern8_state_wo_inlncfg_testRMMI Control IF Write in different states without RX_InLnCfg RMMI Control I/F Writes on TX & RX interface in different states without RX_InLnCfgStimulus:

DATA_XFER M-PHY - MISC CASES COMPLIANCE compliance_mphy_tx_driver_polarity.log mphy_tx_driver_polarity_testTX_DRIVER_POLARITY change Line 1011 : - TX_DRIVER_POLARITY is used to change the polarity of the LINE if DP and DN of the M-TX are cross connected to the DN and DP of the M-RX. Stimulus: Write to the TX_DRIVER_POLARITY Attribute. If TX_DRIVER_POLARITY is changed to a new value by the Protocol after the initial local RESET, the Protocol should change this attribute value to the new value after a subsequent local RESET is applied and de-asserted, and before M-TX is requested to exit HIBERN8 state.

Expectation :


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Stimulus:


Expectation :

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_rmmi_cntl_if_wr_tx_rx_in_hibern8_state.log rmmi_cntl_if_wr_tx_rx_in_hibern8_state_testRMMI Control IF Write in different states with RX_InLnCfg RMMI Control I/F Writes on TX & RX interface in different states with RX_InLnCfgStimulus:


Stimulus:

RESET MPHY RESET Cases COMPLIANCE compliance_mphy_reset_during_hibern8.log mphy_reset_during_hibern8_testTX / RX RESET at different state and speeds Apply the reset in Different state of module


RESET MPHY RESET Cases COMPLIANCE compliance_mphy_rx_reset_removal_while_tx_in_hibern8.log mphy_rx_reset_removal_while_tx_in_hibern8_testRX wakeup cases Stimulus: Remove the reset from RX when 1.TX is in HIBERN8, 2.TX is in sleep


Stimulus:


Stimulus:

RESET MPHY RESET Cases COMPLIANCE compliance_mphy_line_reset_during_ls_sync.log mphy_line_reset_during_ls_sync_testLINE-RESET at different speed and state with TX_Controlled_ActTimer Lowest level reset mechanism in order to reset the M-RX via the LINE during operation in case of malfunction. LINE-RESET condition is a long DIF-P period, which can never occur during normal operation.Stimulus: LINE-RESET can be initiated by the Protocol Layer on the M-TX side of a LINK using the M-CTRL-LINERESET.request primitive Value of TX_Controlled_ActTimer is one




Stimulus:


RESET MPHY RESET Cases COMPLIANCE compliance_mphy_reset_during_ls_sync.log mphy_reset_during_ls_sync_testTX / RX RESET at different state and speeds Apply the reset in Different state of module



Stimulus:



Expectation :


Expectation :

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_rmmi_cntl_if_wr_tx_rx_in_sleep_state_wo_inlncfg.log rmmi_cntl_if_wr_tx_rx_in_sleep_state_wo_inlncfg_testRMMI Control IF Write in different states without RX_InLnCfg RMMI Control I/F Writes on TX & RX interface in different states without RX_InLnCfgStimulus:



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FSM_TR M-PHY state transition COMPLIANCE compliance_mphy_state_transition_from_line_cfg_to_sleep.log mphy_state_transition_from_line_cfg_to_sleep_testState transition from LINE-CFG to other states Mphy state transition from LINE-CFG to other states

Stimulus:

FSM_TR M-PHY state transition COMPLIANCE compliance_mphy_state_transition_from_line_cfg_to_stall.log mphy_state_transition_from_line_cfg_to_stall_testState transition from LINE-CFG to other states Mphy state transition from LINE-CFG to other states

Stimulus:


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DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_burst_hs_G1_with_data_bus_40_bits.log mphy_burst_hs_G1_with_data_bus_40_bits_testdata transfer with all data bus sizes Normal Data transfer in ls and hs mode with all data bus sizesStimulus:

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_rmmi_cntl_if_rd_tx_rx_in_hibern8_state.log rmmi_cntl_if_rd_tx_rx_in_hibern8_state_testRMMI Control IF Read in all states RMMI Control I/F Reads on TX & RX interface with random attribute ID

Stimulus:




Expectation :

DATA_XFER M-PHY - RANDOM TEST CASES RANDOM rand_mphy_line_cfg_test_uvm.log mphy_tb_random_line_cfg_testM-PHY RANDOM LINE CFG TRANSITION TEST -- Performing LS_BURST to LINE_CFG and HS_BURST to LINE_CFG transitions with driving some data in LINE_CFG. -- Performing LINE_CFG to SLEEP and LINE_CFG to STALL transitions. -- Performing LINE_CFG to LINE_RESET transition. -- Randomly varying LS_PREPARE_LENGTH for its minimum to maximum values.Stimulus: --



Expectation :


Stimulus:

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_burst_ls_G7_with_data_bus_40_bits.log mphy_burst_ls_G7_with_data_bus_40_bits_testdata transfer with all data bus sizes Normal Data transfer in ls and hs mode with all data bus sizesStimulus:


Expectation :

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_burst_hs_G1_with_max_tob.log mphy_burst_hs_G1_with_max_tob_testdata transfer with typical values of TOB ls and hs burst Normal Data transfer in ls and hs mode with typical values of TOB Stimulus:



RESET MPHY RESET Cases COMPLIANCE compliance_mphy_line_reset_during_hs_burst.log mphy_line_reset_during_hs_burst_testLINE-RESET at different speed and state with TX_Controlled_ActTimer Lowest level reset mechanism in order to reset the M-RX via the LINE during operation in case of malfunction. LINE-RESET condition is a long DIF-P period, which can never occur during normal operation.Stimulus: LINE-RESET can be initiated by the Protocol Layer on the M-TX side of a LINK using the M-CTRL-LINERESET.request primitive Value of TX_Controlled_ActTimer is one







Expectation :

ERR M-PHY ERROR transfers COMPLIANCE compliance_mphy_DIF_N_hibern8.log mphy_DIF_N_hibern8_testDIF_N in HIBERN8 state -- MPHY DIF_N in HIBERN8 stateStimulus: Randomly insert DIF_N in HIBERN8 state




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Expectation :

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_rmmi_cntl_if_rd_tx_rx_in_line_cfg_state.log rmmi_cntl_if_rd_tx_rx_in_line_cfg_state_testRMMI Control IF Read in all states RMMI Control I/F Reads on TX & RX interface with random attribute ID

Stimulus:


Expectation :

ERR M-PHY ERROR transfers COMPLIANCE compliance_mphy_DIF_Z_LR.log mphy_DIF_Z_LR_testDIF_Z in LINE_RESET state -- MPHY DIF_Z in LINE_RESET state

Stimulus: Randomly insert DIF_Z in LINE_RESET state

DATA_XFER M-PHY - JITTER & PPM Cases COMPLIANCE compliance_mphy_neg_xcess_ppm.log mphy_neg_xcess_ppm_testMPHY PPM ERROR Cases ( If DUT Supports it ) ( in one million ideal clocks period ) This happens due to the minute error in the crystal Oscillating frequency. Induce the PPM (exceeding the limits ) On TX CLK Stimulus: By Enabling the ppm ( exceeding the limits) on the Clock of TX. +INJ_EXCESS_PPM = (NONE, POS, NEG, RAND)

Expectation : Thresholds of the Shallow FIFO's should exceed when WR clk is faster. Shallow FIFO should become empty when RD Clk is faster.

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_burst_ls_G6_random_sync_pattern.log mphy_burst_ls_G6_random_sync_pattern_testdata transfer with all possible values of sync pattern Normal Data transfer in ls and hs mode with all possible values of sync patterns Stimulus:


Expectation :


Stimulus:

RESET MPHY RESET Cases COMPLIANCE compliance_mphy_line_reset_during_sleep.log mphy_line_reset_during_sleep_testLINE-RESET at different speed and state without TX_Controlled_ActTimer Lowest level reset mechanism in order to reset the M-RX via the LINE during operation in case of malfunction. LINE-RESET condition is a long DIF-P period, which can never occur during normal operation.Stimulus: LINE-RESET can be initiated by the Protocol Layer on the M-TX side of a LINK using the M-CTRL-LINERESET.request primitive Value of TX_Controlled_ActTimer is zero




Expectation :

RESET MPHY RESET Cases COMPLIANCE compliance_mphy_reset_during_hs_prepare.log mphy_reset_during_hs_prepare_testTX / RX RESET at different state and speeds Apply the reset in Different state of module


REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_rmmi_cntl_if_wr_tx_rx_in_line_cfg_state.log rmmi_cntl_if_wr_tx_rx_in_line_cfg_state_testRMMI Control IF Write in different states with RX_InLnCfg RMMI Control I/F Writes on TX & RX interface in different states with RX_InLnCfgStimulus:


Expectation :

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_rmmi_cntl_if_rd_tx_rx_in_hs_burst_state.log rmmi_cntl_if_rd_tx_rx_in_hs_burst_state_testRMMI Control IF Read in all states RMMI Control I/F Reads on TX & RX interface with random attribute ID

Stimulus:



REG_W/R M-PHY Control transfers COMPLIANCE compliance_mphy_reg_wr_rd_err.log mphy_reg_wr_rd_err_testRegister Write / Read ERROR Transfers Accesses invalid registers(Invalid Attribute Index) on Attribute Write / Read Transfers

Stimulus: Do the Attribute Write/Read operations in RTL for MPHY Registers thriugh the RMMI CNTL interface Valid Addr range : 'h0001 -to- 'h00E6

Types of Errors : -- Invalid Attribute Index -- Try to write any Invalid value to the Attribute

** NOTE ** NOT Applicable for BFM

ERR M-PHY ERROR transfers COMPLIANCE compliance_mphy_DIF_Z_prepare.log mphy_DIF_Z_prepare_testDIF_Z in PREPARE state -- MPHY DIF_Z in PREPARE state

Stimulus: Randomly insert DIF_Z in PREPARE state


Stimulus:

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_burst_ls_G7_with_max_tob.log mphy_burst_ls_G7_with_max_tob_testdata transfer with typical values of TOB ls and hs burst Normal Data transfer in ls and hs mode with typical values of TOB Stimulus:


Expectation :


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FSM_TR M-PHY state transition COMPLIANCE compliance_mphy_state_transition_from_hibern8_to_sleep.log mphy_state_transition_from_hibern8_to_sleep_testState transition from HIBERN8 to other states Mphy state transition from HIBERN8 to other states

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Expectation :

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_burst_ls_G1_with_min_tob.log mphy_burst_ls_G1_with_min_tob_testdata transfer with typical values of TOB ls and hs burst Normal Data transfer in ls and hs mode with typical values of TOB Stimulus:

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_hs_G3_to_ls_mode.log mphy_hs_G3_to_ls_mode_testMPHY INTER MODE_CHANGE Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument

Expectation :

DATA_XFER M-PHY - RANDOM TEST CASES RANDOM rand_mphy_long_burst_test_uvm.log mphy_tb_random_long_burst_testM-PHY RANDOM STATE TRANSITION TEST -- Performing various state transitions in SLEEP, STALL, LS_BURST, HS_BURST, HIBERN8, LINE_CFG, LINE_RESET states. -- Line reset is asserting with both tx_act_timer enable and disable randomly. -- Line reset is asserting during a burst. -- Burst to Line cfg trnasition is being performed. -- Randomizing the HS_SYNC_LENGTH value from minimum to maximum value.Stimulus: --



Expectation :


Stimulus:


Expectation :

DATA_XFER M-PHY DATA transfers COMPLIANCE compliance_mphy_hs_G3_SA_burst_xfer.log mphy_hs_G3_SA_burst_xfer_testData transfer in HS Burst with all gears Normal Data transfer in BurstsStimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts.


FSM_TR M-PHY state transition COMPLIANCE compliance_mphy_state_transition_from_stall_to_hs_burst.log mphy_state_transition_from_stall_to_hs_burst_testState transition from STALL to other states Mphy state transition from STALL to other states

Stimulus:

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_rmmi_cntl_if_rd_tx_rx_in_ls_burst_state.log rmmi_cntl_if_rd_tx_rx_in_ls_burst_state_testRMMI Control IF Read in all states RMMI Control I/F Reads on TX & RX interface with random attribute ID

Stimulus:

ERR M-PHY ERROR transfers COMPLIANCE compliance_mphy_rd_err.log mphy_rd_err_testRD Error Injecting the RD Errors in encoded data.Stimulus: Randomly 8b/10b encoding should insert the RD Error.

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_rmmi_cntl_if_wr_tx_rx_in_save_state.log rmmi_cntl_if_wr_tx_rx_in_save_state_testRMMI Control IF Write in different states with RX_InLnCfg RMMI Control I/F Writes on TX & RX interface in different states with RX_InLnCfgStimulus:




RESET MPHY RESET Cases COMPLIANCE compliance_mphy_reset_during_line_cfg.log mphy_reset_during_line_cfg_testTX / RX RESET at different state and speeds Apply the reset in Different state of module


RESET MPHY RESET Cases COMPLIANCE compliance_mphy_line_reset_during_hs_sync.log mphy_line_reset_during_hs_sync_testLINE-RESET at different speed and state with TX_Controlled_ActTimer Lowest level reset mechanism in order to reset the M-RX via the LINE during operation in case of malfunction. LINE-RESET condition is a long DIF-P period, which can never occur during normal operation.Stimulus: LINE-RESET can be initiated by the Protocol Layer on the M-TX side of a LINK using the M-CTRL-LINERESET.request primitive Value of TX_Controlled_ActTimer is one




Expectation :

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_rmmi_cntl_if_rd_tx_rx_in_disable_state.log rmmi_cntl_if_rd_tx_rx_in_disable_state_testRMMI Control IF Read in all states RMMI Control I/F Reads on TX & RX interface with random attribute ID

Stimulus:

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_rmmi_cntl_if_wr_cfgupdt_during_save_state_tx_rx.log rmmi_cntl_if_wr_cfgupdt_during_save_state_tx_rx_testRMMI Control IF CfgUpdate after Writes RMMI Control I/F Writes on TX & RX interface during Data Burst and issue a Cfgupdt after/during the burstStimulus:






ERR M-PHY ERROR transfers COMPLIANCE compliance_mphy_DIF_Z_save.log mphy_DIF_Z_save_testDIF_Z in SAVE state -- MPHY DIF_Z in SAVE stateStimulus: Randomly insert DIF_Z in SAVE state


Stimulus:


Stimulus:


Expectation :

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_rmmi_cntl_if_wr_tx_rx_in_line_cfg_state_wo_inlncfg.log rmmi_cntl_if_wr_tx_rx_in_line_cfg_state_wo_inlncfg_testRMMI Control IF Write in different states without RX_InLnCfg RMMI Control I/F Writes on TX & RX interface in different states without RX_InLnCfgStimulus:


Expectation :

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_mphy_hs_burst_with_hs_G3_in_NearEnd_loopback_mode.log mphy_hs_burst_with_hs_G3_in_NearEnd_loopback_mode_testNearEnd loopback tests

Stimulus:


Stimulus:

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_rmmi_cntl_if_wr_tx_rx_in_stall_state.log rmmi_cntl_if_wr_tx_rx_in_stall_state_testRMMI Control IF Write in different states with RX_InLnCfg RMMI Control I/F Writes on TX & RX interface in different states with RX_InLnCfgStimulus:

FSM_TR M-PHY state transition COMPLIANCE compliance_mphy_state_transition_from_hibern8_to_stall.log mphy_state_transition_from_hibern8_to_stall_testState transition from HIBERN8 to other states Mphy state transition from HIBERN8 to other states

Stimulus:


Expectation :

DATA_XFER M-PHY DATA transfers COMPLIANCE compliance_mphy_hs_G2_SA_burst_xfer.log mphy_hs_G2_SA_burst_xfer_testData transfer in HS Burst with all gears Normal Data transfer in BurstsStimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts.




Stimulus:


Expectation :

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_burst_hs_G3_random_sync_pattern.log mphy_burst_hs_G3_random_sync_pattern_testdata transfer with all possible values of sync pattern Normal Data transfer in ls and hs mode with all possible values of sync patterns Stimulus:

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_burst_ls_G7_random_sync_pattern.log mphy_burst_ls_G7_random_sync_pattern_testdata transfer with all possible values of sync pattern Normal Data transfer in ls and hs mode with all possible values of sync patterns Stimulus:

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_burst_hs_G3_with_min_tob.log mphy_burst_hs_G3_with_min_tob_testdata transfer with typical values of TOB ls and hs burst Normal Data transfer in ls and hs mode with typical values of TOB Stimulus:


DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_ls_mode_to_hs_G3.log mphy_ls_mode_to_hs_G3_testMPHY INTER MODE_CHANGE Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument

Expectation :

REG_W/R MPHY RMMI Interface tests COMPLIANCE compliance_rmmi_cntl_if_wr_cfgupdt_during_burst_state_tx_rx.log rmmi_cntl_if_wr_cfgupdt_during_burst_state_tx_rx_testRMMI Control IF CfgUpdate after Writes RMMI Control I/F Writes on TX & RX interface during Data Burst and issue a Cfgupdt after/during the burstStimulus:


Expectation :

RESET MPHY RESET Cases COMPLIANCE compliance_mphy_reset_during_ls_prepare.log mphy_reset_during_ls_prepare_testTX / RX RESET at different state and speeds Apply the reset in Different state of module



Expectation :

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_burst_hs_G1_random_sync_pattern.log mphy_burst_hs_G1_random_sync_pattern_testdata transfer with all possible values of sync pattern Normal Data transfer in ls and hs mode with all possible values of sync patterns Stimulus:


Expectation :


FSM_TR M-PHY state transition COMPLIANCE compliance_mphy_state_transition_from_hs_burst_to_stall.log mphy_state_transition_from_hs_burst_to_stall_testState transition from HS_BURST to other states Mphy state transition from HS_BURST to other states

Stimulus:

RESET MPHY RESET Cases COMPLIANCE compliance_mphy_line_reset_during_tob.log mphy_line_reset_during_tob_testLINE-RESET at different speed and state with TX_Controlled_ActTimer Lowest level reset mechanism in order to reset the M-RX via the LINE during operation in case of malfunction. LINE-RESET condition is a long DIF-P period, which can never occur during normal operation.Stimulus: LINE-RESET can be initiated by the Protocol Layer on the M-TX side of a LINK using the M-CTRL-LINERESET.request primitive Value of TX_Controlled_ActTimer is one



DATA_XFER M-PHY - JITTER & PPM Cases COMPLIANCE compliance_mphy_pos_xcess_jitter.log mphy_pos_xcess_jitter_testMPHY JITTER ERROR Cases Induce Excess Jitter On TX CLK Stimulus: Enable the jitter and induce excess jitter on the Clock of TX. +INJ_EXCESS_JITTER = (NONE, POS, NEG, RAND)

Expectation : Data Loss / Multiple samples of same bit can happen

DATA_XFER M-PHY - JITTER & PPM Cases COMPLIANCE compliance_mphy_rnd_jitter.log mphy_rnd_jitter_testMPHY JITTER Cases Induce the Jitter On TX CLK Stimulus: By Enabling the jitter on the Clock of TX. +INJ_JITTER = (NONE, POS, NEG, RND)


ERR M-PHY ERROR transfers COMPLIANCE compliance_mphy_sync_pattern_corrupt.log mphy_sync_pattern_corrupt_testSYNC Pattern error injection Injecting the Errors in encoded Control symbols. SYNC pattern corruption keeps the width same as spec defined values but corrupts the pattern SYNC pattern width exceeds or sends lesser than specification defined width Stimulus: Randomly Corrupt the 8b/10b encoded control symbol values before driving it on the DP/DN lanes.


Expectation :


Expectation :


DATA_XFER M-PHY - MISC CASES COMPLIANCE compliance_mphy_line_config.log mphy_line_config_testMPHY LINE_CFG D.3.1 TX_LCC_Enable Stimulus: LINE CFG when the OMC is present.

Expectation :


Expectation :


Expectation :

FSM_TR M-PHY state transition COMPLIANCE compliance_mphy_state_transition_from_ls_burst_to_sleep.log mphy_state_transition_from_ls_burst_to_sleep_testState transition from LS_BURST to other states Mphy state transition from LS_BURST to other states

Stimulus:


Expectation :


Expectation :


Expectation :

DATA_XFER M-PHY - MODE/GEAR/SERIES CHANGE CASES COMPLIANCE compliance_mphy_ls_mode_to_hs_G1.log mphy_ls_mode_to_hs_G1_testMPHY INTER MODE_CHANGE Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument

Expectation :



Expectation :


Stimulus:

DATA_XFER M-PHY - JITTER & PPM Cases COMPLIANCE compliance_mphy_pos_xcess_ppm.log mphy_pos_xcess_ppm_testMPHY PPM ERROR Cases ( If DUT Supports it ) ( in one million ideal clocks period ) This happens due to the minute error in the crystal Oscillating frequency. Induce the PPM (exceeding the limits ) On TX CLK Stimulus: By Enabling the ppm ( exceeding the limits) on the Clock of TX. +INJ_EXCESS_PPM = (NONE, POS, NEG, RAND)

Expectation : Thresholds of the Shallow FIFO's should exceed when WR clk is faster. Shallow FIFO should become empty when RD

Documents

ArrowDevices M-PHY Verification Checklist