Array Subsystem

8/4/2019 Array Subsystem

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Array subsystem


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Chip Functions

ta path OperatorsMemory ElementsControl Structures SpecialPurposeCells

I/OPower DistributiClock Generatio

Analog

Trade off factors:

Speed, Density,

Programmability,


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Array : Repetition of basic cell in two dimensions .

A cell is carefully optimized to provide very high density.

Many a times due to high density problems, full o/pvoltage swings are not available at various nodes. Theperiphery circuit is used to restore it to nodes to full

logic levels.

Types of Arrays:

1 Logic - PLAs

2. Storage Memory.

In a CMOS SOC , memory arrays are responsible formajority transistors.

Study of memory involves: Issues of cell design,Decodin Column circuit desi n etc.


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MEMORY

RAM CAM

SAM

Shift reg /Queues

SIPO / PISO

FIFO /LIFO

RWM/ROM

SRAM / DRAM

MROM

PROM

EPROM

EEPROM

Flash

Addresscontains adata thatmatches aspecific

key.

Addressed

sequentially. Doesnot need anyaddress.

Accessed withaddress.

Haslatencyindependent ofaddress.


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SRAM DRAMUse flip-flops. Use charge storage in a

parasitic capacitor .

Use f/b to maintain theirstate.

Use charge stored on afloating capacitor throughan access transistor.

Faster and lesstroublesome.

Charge leaks thru accesstransistor even while

transistor is off.

Requires more area per bitthan DRAMs

Hence they need aperiodical read andrewritten to refresh their

state.


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MaskROM

Hardwired during fabrication.

Cannot be changed.

PROM Can be programmed once after fabrication byblowing on chip fuses with a special highprogramming voltage.

EPROM Is programmed by storing charge on a floating

gate. It can be erased by exposure to use lightfor several minutes to knock the charge off thegate. Then EPROM can be reprogrammed.

EEPROM

Can be erased in microsecond with on chipcircuitry.

Flash Variant of EEPROM

Erases entire blocks instead of individual bits.

Erase circuitry is shared among larger blocks.

So, area per bit is reduced. Hence high densityand ease of reprogram ability in the system is


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Read access time:

Time it takes to retrieve from the memory. It is the time

difference between read request and the moment at whichdata is available at the output.

Write access time:

Time elapsed between a write request and the final writingof the input data into the memory.

Read / Write cycle time:

Minimum time required between successive reads andwrites. This is normally greater than the access time .

Read / Write cycles need not have same time. But forsimplicity of system design, they are considered to be

same.


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Timing parameters

READ

READ cycle

WRITE cycle

WRITE

Read accessRead access

Write accessData Valid

Data written

DATA


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Typical signals and buses in an RWM chip.

M X N

Memory

M = 2 k

Address

bus

Input data bus

Output data bus

Chip select

Read/write

N

N

N

M A hit t f N


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Memory Architecture for N -Word Memory

Word 0

Word 1

Word 2

Word N-2

Word N-1

S0

S1

S2

SN-2

SN-1

I/p - O/p M

N

words

M bits

(Intuitive)

One word at a time is selected forreading / writing.

Since this is a single port

memory, only one signal Si can behigh at a time.

N select bits are needed.

Simple but works for very smallmemory.

For large memory, no. of selectlines increases.

These select lines are provided on


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Word 0

Word 1

Word 2

Word N-2Word N-1

S0

M bits

Decoder

(Reducesthe no. ofAddress

bits)

I/p - O/p M

A 0

A 1

A k-1

K =log2N

(UsingDecoder)

No. of select signals arereduced.

N = 2k select bits are

needed. One of which at atime is active for reading /writing.

Decoder is designed to

have a size matching to thatof a storage cell..

For large memory, no. ofselect lines decreases andlarge routing channels arenot required.

Wiring /packagingproblems can be eliminated.

Does not address memoryaspect ratio problem.(220 /23

St t d


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StructuredMemory

Organization

Bit Line

RowDecoder

Ak

A k+1

A L-1

2L-k

Equal vertical andhorizontaldimensions.

Multiple words arestored in a single rowand are selectedsimultaneously.

To route correctword, a columndecoder is used.

Address part is

Word Line

Sense amp /driver

M-2k

A0

Ak-1 I/p - O/p M

Column decoder


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Word Line: Horizontal select line thatenables single row of cells.

Bit Line: Wire that connect cells insingle column to I/P O/P circuitry.

Design metrics: Area, Noise margin,Logic swing, I/p O/p isolation, Fanout and Speed.


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Design Techniques

Propagation delay and power consumption can bereduced by reducing voltage swing substantiallybelow supply lines.

Within an array, careful control of crosstalk and

other disturbances is possible ensuring sufficientnoise margin even for small voltage swings.

Sense amplifiers amplify the internal swing to fullrail to rail swing amplitude so as to communicatewith the external world.


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Static and Dynamic RAMs

RAMs come in two varieties, static and dynamic.

However, the combination of a static RAM cache anda dynamic RAM main memory attempts to combinethe good properties of each.


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A typical SRAM cell uses Six transistors, connected insuch a way as to create a regenerative feedback.

In comparison with the DRAM, the information held isstable and requires no clocking or refresh cycles to sustainit.

Static RAMs are much faster compared to dynamic RAMs.

Typical access time is in the order of few nanoseconds.

For this reason ,SRAMs are popular as level 2 cachememory.

SRAM Cell


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A dynamic RAM is an array of cells, each cell containing one transistor anda tiny capacitor.

The capacitors can be charged or discharged, allowing 0s and 1s to bestored.

Because the electric charge tends to leak out, each bit in a dynamic RAMmust be refreshed every few milliseconds to prevent the data fromleaking away.

Because external logic must take care of the refreshing, dynamic RAMs

require more complex interfacing than static ones. They have larger capacities.

Since dynamic RAMs need only one transistor and one capacitor per bit,they can have a very high packing density. For this reason, main memoriesare nearly always built out of dynamic RAMs. However, DRAMs aregenerally slow with the delay in the order of tens of nanoseconds.

DRAM Cell


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The memory circuit is said to be static ifthe stored data can be retained, without anyneed for periodic refresh operation.

The data storage cell is the one bit memorycell in the static RAM arrays.

Consists of a simple latch circuit with twostable operating points.

Depending on the preserved state of thetwo inverter latch circuit, the data beingheld in the memory cell will be interpretedeither as logic 0 or as logic1.

To access the data contained in thememory cell via a bit line, we need at leastone switch( a pass transistor), which iscontrolled by the corresponding wordline as

shown in Figure .

SRAM

Cell


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The memory cell consist of a simple CMOS invertersconnected back to back , and two access transistors .

The access transistors are turned on whenever a wordlineis activated for read or write operation, connecting the cellto the complementary bitline columns.

BL


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CMOS SRAM cellwith precharge Transistor

We have to take intoaccount , the relativelylarge parasitic columncapacitance Cbit andCbitbar and column pull uptransistors.When none of the wordlines is selected, the pass

transistors M5, M6 areturned off and the data isretained in all memorycells.

The column capacitancesare charged by the pull uptransistors P1 and P2.The voltages across thecolumn capacitors reach

VDD-VT.

M2

M5

M4

M3M1

M6

BIT


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The two basic requirements, which dictate W/L ratios are

i) The data read operation should not destroy the stored information inthe cell.

ii) The cell should allow stored information modification during writeoperation.

Two phase operation:Phase II- SRAM is precharged.

Phase I written or read by raising appropriatewordline and either driving bitlines to the value that isto be written or leaving bitlines floating and observingwhich one is pulled down.

Erroneous triggering can also be prevented by prechargingthe bitlines to another value like VDD/2.In such case, Q does not reach the switching threshold ofinverter.

It also limits voltage swing on the bitlines and thus reducesthe power dissipation.


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DRAM Cell Charge storage in MOSFET parasitic

capacitances is used for temporary storage ofdata in dynamic RAMs. However because of gate leakage currents the

charge must be restored at periodic intervals

for long time storage. Usually, data refresh is carried out once every2 ms using support circuitry.

Due to inherent discharging, read out may bedestructive. Hence every read operation mustbe followed with a write operation.

It offers high density, low power dissipationand reduced complexity. Hence for large sizedmemories, ( above 1 MB) DRAMs are preferred

over SRAMs.


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4T DRAM cell Same as generic static RAM cell.

Charge is stored at the gate node ofQ1 or Q2 during high level of clock.

When the clock goes low, the chargeleaks through the R. B. drain-substrate junction.

Since the leakage rate is low(discharging current of the order offew pA) logic state of the latch is heldfor a short time.

Activating the clock for amicrosecond after approx. every 2msrestores the lost charge.


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If Q1 is ON, V1=VT and Q2 is off, V2=0.

As C1 loses charge through Q1, clock is turned high.

So, QR1, LX1, QR2 and LX2 are turned ON.Q1 conducts

and holds V2=0.V1 is thus restored and V2 remainsunchanged.

For writing, Databar line is taken to appropriate data, RAS,CAS are high.R/W is taken to high.

For reading, R/W is taken low, CAS, RAS are taken high.The voltage across C1 is then available at Dout via LX2,QC2 and Q0.

To avoid excessive discharge, C1 is large as compared todata line capacitance.


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Offers nondestructive reading by separating read and writeoperations.

To read the cell, Doutbar is made high and read line is also takenhigh.

If C is charged initially, Doutbar will go low, and vice versa. A 0 in Din makes capacitor discharge when Write signal is high. A 1 in Din makes capacitor charge when Write signal is high.

3T DRAM cell


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Further reduction in no. of active devices. High packaging density and speed.

Parasitic capacitor is accessed via Q for reading and writing.

To write the cell, row line is raised while Data line is low or high .Then, C is charged ordischarged to the value on the bitline.

Stored cell value is transferred to dataline by taking Row line high and floating the Dataline.

1T DRAM cell

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Array Subsystem