Array of Silicon Avalanche Pixels (ASAP) · Ø Brief status report and perspectives Ø FTE Ø Richieste in sezione P. S. Marrocchesi – 180703 -‐ INFN sez. di Pisa 2. APIX particle

University of Siena & INFN Pisa

University of Trento & TIFPA University of Padova & INFN Padova

University of Pavia & INFN Pavia

Array of Silicon Avalanche Pixels (ASAP)

P. S. Marrocchesi – 170705 -‐ INFN sez. di Pisa

Outline

Ø  Sensor concept and architecture

Ø  Brief status report and perspectives

Ø  FTE

Ø  Richieste in sezione

2 P. S. Marrocchesi – 180703 -‐ INFN sez. di Pisa

APIX particle detector concept

Discriminators

Coincidence detector

Quenching Particle detection

Dark counts

Basic idea: Use of two Geiger-mode avalanche detectors (SPADs) in coincidence to detect particles l  Digital read-out l  Reduced Dark Count Rate: DCR = DCR1 * DCR2 * 2ΔT l  Timing performances l  Low power consumption l  Low material budget


APIX demonstrator: pixel cross-section

è CMOS process allow integrated electronics (not feasible in SiPM integrated process)

è  Metal shielding to avoid optical cross-talk è  Vertical interconnection by bump bonding


APIX pixel array (1st prototype)

43µm x 45µm

40µm x 40µm

35µm x 35µm

30µm x 30µm

l  Sensor array of 16 rows x 48 SPADs

l  Pixel size: 50 µm x 75 µm

l  Total sensor dimensions: 1.2 x 2.4 mm2

Electronics

Detector area

Bonding pad

Shielded detectors Unshielded pixels with different active

area

Array partitioning: l  Two SPAD types: p+/nwell and p-

well/n-iso l  Different SPAD active areas:

30 – 35 – 40 – 45 micron side l  Some unshielded structures for

testing with light l  Coincidence between SPAD with the

same size and with different sizes 5 P. S. Marrocchesi – 180703 -‐ INFN sez. di Pisa

APIX final assembly Dark Count Rate

Dark Count Rate for different coincidence time ΔT: 10ns, 1.5ns, 0.75ns

DCRCOINC = DCR1 x DCR2 x 2ΔT

T = 20°C

DCRCOINC = 27 counts/s mm2

6

*

Type 2

P. S. Marrocchesi – 180703 -‐ INFN sez. di Pisa

Coincidence detection

Count rate in coincidence between two pixels in the same column Normalized rate:

1 2 3 4 5 6 7

Cross-talk

Cross-talk


Crosstalk vs substrate thickness


2016 Beam test at CERN SPS North Area (H4 beam line) Two APIX2 sensors under test + silicon Beam Tracker Charged parRcle beams with energy 50, 100, 150, 200 and 300 GeV

4 Si-‐strip detectors

2 APIX2 pixel detectors

6 Si-‐strip detectors

2 HD Si-‐strip detectors

2 HD Si-‐strip detectors

Beam Tracker

On-‐line event display beam – YZ view beam – XZ view


•  Measured efficiency 56.2 ± 5 % (stat+sys)

•  Expected (purely geometrical) FF = 52%

•  => EffecRve detector efficiency close to 100% (only limited by FF)

•  Higher staRsRcs and improved beam tracking accuracy foreseen for next beam test

Efficiency measurement in 6 different fiducial regions

DefiniRon of 6 areas covered by the reconstructed track impact point (IP)

4 different markers: residual between impact point and pixel center in units of σ


APIX2 imaging: Example of two regions-‐of-‐interest separated by ~ 100 um

•  Efficiency close to 100% (only limited by FF)


Papers and talks [1] N. D'Ascenzo et al, "Silicon avalanche pixel sensor for high precision tracking", 2014 JINST 9 C03027, doi:10.1088/1748-‐0221/9/03/C03027. [2] L. Pancheri et al., “First prototypes of two-‐Rer avalanche pixel sensors for parRcle detecRon”, 14th Vienna Conference on InstrumentaRon, Vienna, Austria, 15 – 19 February 2016. [3] A. Ficorella et al., "Crosstalk mapping in CMOS SPAD arrays," 2016 46th European Solid-‐State Devices Research Conference, ESSDERC, Lausanne, Switzerland, 12 – 15 September 2016. [4] L. Pancheri et al., “VerRcally-‐integrated CMOS Geiger-‐mode avalanche pixel sensors,” 14th Topical Seminar on InnovaRve ParRcle and RadiaRon Detectors (IPRD16), Siena, Italy, 3 -‐ 6 October 2016. [5] L. Pancheri et al., “Two-‐Tier Pixelated Avalanche Sensor for ParRcle DetecRon in 150nm CMOS”, IEEE NSS/MIC, Strasbourg, France, 29 October – 5 November 2016. [6] P. Brogi et al., “ A new Avalanche Pixel Sensor for charged parRcle detecRon (APIX2)”, 7th Young Researcher MeeRng, Torino, Italy, October 24-‐26, 2016 [7] L. Pancheri et al., ”First DemonstraRon of a Two-‐Tier Pixelated Avalanche Sensor for ParRcle DetecRon”, Journal of the Electron Devices Society, Vol. 5 NO.5, September 2017. [8] A. Ficorella et al.,‘Crosstalk CharacterizaRon of a Two-‐Tier Pixelated Avalanche Sensor for Charged ParRcle DetecRon”, IEEE Journal of Selected Topics in Quantum Electronics Vol. 24 Issue 2 (2017.09.21) [9] P. S. Marrocchesi et al., “APiX : a Geiger-‐mode avalanche digital sensor for charged parRcle detecRon“ , IEEE NSS/MIC/RTSD, Atlanta, 21-‐18 October 2017.


48x48 cells, 75 um pitch, 1 bit memory, 6-parallel readout

24x72 cells, 50 um pitch, 1 bit memory, 3-parallel readout

48x1

1 ce

lls, 7

5 um

pit

ch,

10 b

it c

ount

er

test structures

83% fill factor

43% fill factor

45% fill factor


2nd prototype delivered by LF in late Spring 2018.

Bump bonding order placed at the end of 2017.

ASAP 2019 run: Improvements w/r to APiX prototypes

§  Strategies to improve efficiency: –  Process scaling: improve geometrical Fill-Factor –  Thinning: improve efficiency for low-energy particles (e.g.: beta-emitters)

§  Dark count reduction: –  Reduce DCR of single layer: process tailoring (dedicated

implantations) –  Reduce contaminations (imaging process)

§  Large areas: –  Through-Silicon Vias (TSV): buttable modules


P. S. Marrocchesi – 180703 -‐ INFN sez. di Pisa 15

ASAP: Richieste di servizi in sezione per il 2019

•  Supporto gruppo alte-‐tecnologie (micro-‐bonding)

•  Supporto progetazione eletronica (2 mesi uomo)

•  Officina Meccanica (0.5 mese uomo) meccanica test arRcles


Documents

Array of Silicon Avalanche Pixels (ASAP) · Ø Brief status report and perspectives Ø FTE Ø Richieste in sezione P. S. Marrocchesi – 180703 -‐ INFN sez. di Pisa 2. APIX particle