ARM Architecture

3

ARM Ltd

!  Founded in November 1990 !  Spun out of Acorn Computers

!  Designs the ARM range of RISC processor cores !  Licenses ARM core designs to semiconductor

partners who fabricate and sell to their customers. !  ARM does not fabricate silicon itself

!  Also develop technologies to assist with the design-in of the ARM architecture !  Software tools, boards, debug hardware,

application software, graphics, bus architectures, peripherals, cell libraries

ARM small or big?

Revenue Mkt cap$1B $30 B$50B $165 B

ARM and Intel running different businesses•Intel: Number one semiconductor manufacturer•ARM: Leading IP & eco-system provider

5

ARM’s Activities

memory

SoC

Processors System Level IP: Data Engines Fabric 3D Graphics

Physical IP

Software IP

Development Tools

Connected Community

7

ARM Business Today ! Processor Shipped Last Year : ~4 Billion

! Processor Shipped In Total : >24 Billion

! Processor Licenses : 500+

! Semiconductor Partners : 200+

! Process Technology : 28 – 250 nm

! Connected Community Members : 700+

10

700+

12 12

ARM Processor Applications

Tele-parking

What is eco-system? Qualcomm announced its Snapdragon S4 class of SoC, which include an integrated modem on die. The 28nm SoC's micro-architecture is based on up to four independent ARM Cortex-A15 CPU cores, plus a 32 core GPU, a 128-bit SIMD engine, three DSPs, and hardwired codecs all running initially at

What is eco-system?

15

From 1mm3 to 1km3

The Architecture for the Digital World

1mm3 1km3

2mm

0.7mm 1.2mm

10¢ $1000

Mobile Embedded Consumer

Mobile Computing Server Enterprise PC

Home HPC

ARM Architecture

• The ARM is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by ARM Holdings.

• ARM also known as Advance RISC Machine

20

ARM Cortex Advanced Processors Architectural innovation, compatibility across diverse application spectrum

! ARM Cortex-A family: !  Applications processors for feature-

rich OS and 3rd party applications

! ARM Cortex-R family: !  Embedded processors for real-time

signal processing, control applications

! ARM Cortex-M family: !  Microcontroller-oriented processors

for MCU, ASSP, and SoC applications

Cortex-R4(F)

Cortex-A8

SC300™

Cortex-M1 Cortex™-M3

...2GHz

x1-4

Cortex-A9

x1-4

Cortex-A5

12k gates... Cortex-M0 U

npar

alle

led

App

licab

ility

Cortex-M4

Why ARM? • Simplicity is the key philosophy behind the ARM design

• RISC machine with small instruction set and consequently a small gate count.

• High Performance

• Low power consumption

• Small amount of silicon die area

• Open Source Development Tools

21

Data Sizes and Instruction Sets ! The ARM is a 32-bit architecture.

! When used in relation to the ARM: !  Byte means 8 bits

!  Halfword means 16 bits (two bytes)

!  Word means 32 bits (four bytes)

! Most ARM’s implement two instruction sets !  32-bit ARM Instruction Set

!  16-bit/32bit Thumb Instruction Set

! Jazelle cores can also execute Java bytecode

Architecture• Computer Organization (or Microarchitecture)

• Control and data paths

• I/D pipeline design

• Cache design

• System Design (or Platform Architecture)

• Memory and I/O buses

• Memory controllers

• Direct memory access

• Instruction Set Architecture (ISA)

ARM Cortex-M0

ARM Cortex-M0

55

Integer Core Pipeline! 3-stage pipeline core with von Neumann architecture

! Pipeline operates in lockstep all the time

! An instruction is advanced in the pipeline only when another instruction is executed

Fetch Decode Execute

ARM Cortex-M0

ARM Cortex-M0Register Set Address Space

Branching

Data processing

Load/Store

Exceptions

Miscellaneous

Instruction Set

32-bits 32-bits

Endianess Endianess

21

Cortex-M0 Register Set

! All registers are 32 bits wide

! 13 general purpose registers! Registers r0 – r7 (Low registers)! Registers r8 – r12 (High registers)

! 3 registers with special meaning/usage! Stack Pointer (SP) – r13! Link Register (LR) – r14! Program Counter (PC) – r15

! Special-purpose registers! xPSR shows a composite of the content of

! APSR, IPSR, EPSR

Process(Handler Mode)

r8

r9

r10

r11

r12

sp

lr

r15 (pc)

xPSR

r0

r1

r2

r3

r4

r5

r6

r7

Main (Thread Mode)

sp

22

Register Usage

r8r9r10r11

r12

r13/spr14/lrr15/pc

r0r1r2r3

r4r5r6r7Register variables

Must be preserved

Arguments into functionResult(s) from function

otherwise corruptible(Additional parameters

passed on stack)

Scratch register(corruptible)

Stack PointerLink Register

Program Counter

The compiler has a set of rules known as a Procedure Call Standard that determine how to pass parameters to a function (see AAPCS)

CPSR flags may be corrupted by function call

Assembler code which links with compiled code must follow the AAPCS at external interfaces

The AAPCS is part of the ABI for the ARM Architecture

Register

- r14 can be used as a temporary once value stacked

ARM Registers

42

The Thumb-2 instruction set! Variable-length instructions

! ARM instructions are a fixed length of 32 bits! Thumb instructions are a fixed length of 16

bits! Thumb-2 instructions can be either 16-bit or

32-bit

! Thumb-2 gives approximately 26% improvement in code density over ARM

! Thumb-2 gives approximately 25% improvement in performance over Thumb

43

Instruction Set Introduction! ARMv6-M supports a subset of Thumb-2 technology

! A subset of the full Thumb-2 instruction set is supported ! The ARM instruction set is not supported

! Thumb-2 technology supports mixed 16-bit/32-bit instructions

! Small number of additional 32-bit instructions supported

! Conditional execution is supported! Only one conditional instruction

! Optimized for compilation from C! Thumb-2 instructions are not designed to be written by hand! But easy to learn due to small number of mnemonics

44

Binary Upwards Compatibility

45

Instruction Classes! Branch instructions

! Data-processing instructions

! Load and store instructions

! Status register access instructions

! Miscellaneous instructions

Instruction Format

Label Mnemonic Operand1, Operand2, ...; Comments

Example

Movs R0, #0x12; Set R0 = 0x12

Use of a Suffix

With suffix “s”

MOVS R0, R1; Move R1 into R0 and update APSR (only low registers)

Without suffix “s”

MOV R0, R1; Move R1 into R0 (both high or low registers)

Use of a Suffix

With suffix “s”

ADDS R0, R1;R0 = R0 + R1 and update APSR (only low registers)

Without suffix “s”

ADD R0, R1; R0 = R0 + R1 (both high or low registers)

Branch MOVS R0, #3 ;Loop counter starting value is 3

loop ;“loop” is an address label

SUBS R0, #1 ;Decrement by 1 and update flag

BGT loop ;branch to loop if R0 is Greater Than (GT) 1

if (counter > 10) then counter = 0 else counter = counter + 1

———————————————————————————

CMP R0, #10 ; compare to 10

BLE incr_counter ; if less or equal, then branch

MOVS R0, #0 ; counter = 0

B counter_done ; branch to counter_done

incr_counter

ADDS R0, R0, #1 ; counter = counter +1

counter_done

Total = 0; for (i=0;i<5;i=i+1) Total = Total + i;

Assume “ Total” is R0 and “ i” is R1;

—————————————————————————————

MOVS R0, #0 ; Total = 0 MOVS R1, #0 ; i = 0 loop ADDS R0, R0, R1 ; Total = Total + i ADDS R1, R1, #1 ; i = i + 1 CMP R1, #5 ; compare i to 5 BLTloop ; if less than then branch to loop