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Arithmetic, Logic
Instructions and
Programs
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
1Lecture# 08
Microprocessor System and Interfacing
Rotate, Shift and Data Serialization
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
2
Shift Instructions
LSL Instruction
LSL Rd ; logical shift left
Shifted from Right to Left
0 in LSB and MSB in C flag
What it can be used for ?
LSR Instruction
LSR Rd ; logical shift right
Shifted from Left to Right
0 in MSB and LSB in C flag
What it can be used for ?
Cannot be used for Signed Division
Rotate, Shift and Data Serialization
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
3
Shift Instructions
ASR – Arithmetic Shift Right
ASR Rd ; shift right
Shifted from Right to Left
MSB is constant
LSB in C Flag
MSB is copied to next bit
Used for Signed Division
Rotate, Shift and Data Serialization
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
4
Class Example - 1
LDI R20, 0xD0 ; R20 = 1101 0000 (-48) C = 0
ASR R20 ; R20 = 1110 1000 (-24) C = 0
ASR R20 ; R20 = 1111 0100 (-12) C = 0
ASR R20 ; R20 = 1111 1010 (-6) C = 0
ASR R20 ; R20 = 1111 1101 (-3) C = 0
ASR R20 ; R20 = 1111 1110 (-1) C = 1
Rotate, Shift and Data Serialization
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
5
SWAP Instruction
SWAP Rd ; swap nibbles
Works on all Registers (R0 – R31)
Lower bits (D0 – D3) are Swapped with higher
bits (D4 – D7)
Rotate, Shift and Data Serialization
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
6
Class Exercise – 1
Assume that the R20 has the number 48. Show
how we can use ROR to divide R20 by 8
LDI R20, 0x30 ;
CLC ; Clear Carry flag
ROR R20 ; R20 = 24 (0001 1000)
CLC ; Clear Carry flag
ROR R20 ; R20 = 12 (0000 1100)
CLC ; Clear Carry flag
ROR R20 R20 = 6 (0000 0110)
Rotate, Shift and Data Serialization
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
7
Class Exercise – 2
Write a program equivalent to the following
instruction using ROL or ROR instructions
LDI R20, 0x72 ;
LDI R16, 4
LDI R21, 0
BEGIN:
CLC
ROL R20
ROL R21
DEC R16
BRNE BEGIN
OR R20, R21
HERE: JMP HERE
LDI R20, 0x72
SWAP R20
BCD and ASCII Conversion
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
8
BCD – Binary Coded Decimal
Unpacked BCD
Lower 4 bits represents a number (0 – 9)
Upper 4 bits are zero
Requires one byte of memory
Packed BCD
Single Byte Contains 2 BCD numbers
One in lower nibble and one in upper nibble
Efficient as it stores more data
BCD and ASCII Conversion
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
9
Home Assignment
Read about ASCII Numbers
Benefit of ASCII Conversion to Packed BCD
Over Unpacked BCD
AVR Advanced
Assembly Language
Programming
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
10
Introducing Some More Assembler Directives
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
11
Arithmetic Expressions with Constant
Define Constant values using .EQU
.EQU ALFA = 50
.EQU BETA = 40
LDI R23, ALFA
LDI R24, ((ALFA – BETA) * 2 ) + 9; ((50 – 40)*2)+9 = 29
Symbol Action
+ Addition
- Subtraction
* Multiplication
/ Division
% Modulo
Introducing Some More Assembler Directives
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
12
Logic Expressions with Constant
Define Constant values using .EQU
.EQU C1 = 0x50
.EQU C2 = 0x10
.EQU C3 = 0x04
LDI R21, (C1 & C2) | C3 ; R21 = (0x10 & 0x50)|0x04 = 0x14
Symbol Action
& Bitwise AND
| Bitwise OR
^ Bitwise XOR
~ Bitwise NOT
Introducing Some More Assembler Directives
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
13
Shift Operands
The shift operators to shift left and right aconstant value
LDI R16, 0b00000111 << 1 ; R16 = 0b00001110
What we have to do if we have to set Z andC flags ?
Load 0b00000011 in status register
What to do if we don’t have to use the bitnumber ?
I T H S V N Z C
Introducing Some More Assembler Directives
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
14
Shift Operands
Use shift operators to complete this task
Header file of each AVR contains this
definition (M32DEF.INC)
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
Introducing Some More Assembler Directives
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
15
Shift Operands
To set N flag of SREG register we will use
LDI R16, 1<<SREG_N ; R16 = 1<<2
; R16 = 0b00000100
OUT SREG, R16
Exercise:
Set H and V Flag of Status register using shift
operators
LDI R16, (1<<SREG_V) | (1<<SREG_H)
OUT SREG, R16
Introducing Some More Assembler Directives
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
16
HIGH () and LOW () Functions
Give high and low byte of 16-bit value
LDI R16, HIGH (RAMEND)
OUT SPH, R16
LDI R16, LOW (RAMEND)
OUT SPL, R16
How these instructions work?
RAMEND defines the address of RAM in
M32DEF.INC
.equ RAMEND = 0x085f
Register and Direct Addressing Modes
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
17
CPU can access data in various ways
Data could be in a register or a memory
The ways are known as Addressing Modes
Modes are determined when it is designed, itcannot be changed by programmer
13 distinct addressing modes are there(Categorized)
Single-Register (Immediate)
Register
Direct
Register Indirect
Flash Direct
Flash Indirect
Register and Direct Addressing Modes
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
18
Single – Register (Immediate)
The operand is a register
NEG R18
COM R19
In some cases there is a constant value with
register
LDI R18, 0x10
SUBI R19, 0x6
Register and Direct Addressing Modes
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
19
Two – Register
Two registers are involved to hold the data to be
manipulated
ADD R20, R23
AND R03, R04
Register and Direct Addressing Modes
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
20
Direct Addressing Mode
Entire data memory can be accessed
LDS R19, 0x560
STS 0x40, R18
Address field is 16-bit address
Doesn’t support Immediate
addressing mode
Register and Direct Addressing Modes
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
21
I/O Direct Addressing Mode
Special mode
Can address only standard registers
IN and OUT instructions are used
IN R18, 0x16 ; PINB
OUT 0x15, R18 ; PORTC
Register and Direct Addressing Modes
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
22
I/O Direct Addressing Mode
OUT 0x15, R19 ; R19 to PORTC
OUT PORTC, R19 ; Same as Above
Register and Direct Addressing Modes
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
23
I/O Direct Addressing Mode
Remember
Address b/w $20 - $5F is assigned to IO registers
IO registers have two addresses
IO Address
Data Memory Address
Some AVRs have more than 64 IO registers known
as Extended IO memory
IO registers can have different address in different
AVRs
OUT 0x15, R19 ; PORTC = R19
STS 0x35, R19 ; PORTC = R19
Register and Direct Addressing Modes
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
24
Exercise No - 3
Write Code to send $55 to Port B using
The register Name
The IO Address
The Data Memory Address
Register and Direct Addressing Modes
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
25
Register Indirect Addressing Mode
Register is used as a pointer to the data memory
Three registers (X, Y, Z) are used
All are 16-bit registers
Made by combining two GPRS (X = R27:R26, Y =R29:R28, Z = R31:R30)
Can be referred as XL and XH (Low and High)
LD R24, X ; copies value at location X in R24
To a value from location 0x0130 to R18 use
LDI XL, 0x30
LDI XH, 0x01
LD R18, X
Class Exercise - 4
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
26
Write a program to bring in a byte of data serially via pin PC7 and
save it in R20 register. The byte comes in with the LSB first.