Embed Size (px)
Citation preview
IJDACR
ISSN: 2319-4863
International Journal of Digital Application & Contemporary Research
Website: www.ijdacr.com (Volume 5, Issue 7, February 2017)
Area Optimized Implementation of AMBA based Memory
Controller in VHDL
Ashutosh Kumar Singh
Anshul Soni
Ashish Chouhan
Abstract –This paper elaborates the AMBA bus interface
bridge between the memory controller and other
supporting peripheral. The work claims the integration
with FIFO, RAM and ROM with slave interface and the
master of AHB bus. The AHB master initiates the
operation and generates the necessary control signal. A
memory controller is implemented with finite state
machine considering with all the peripheral works in
synchronous mode.
Despite these shortcomings of the work performed to
study and development that followed have led the
development of a memory controller on AMBA-AHB
bus at a very advanced stage and next to prototyping.
VHDL code is utilized to develop the design and it is
synthesized in Xilinx Spartan 3 device (3s100evq100-5).
The design claims a minor area overhead with
improvement in speed 185.134 MHz.
Keywords –AHB, AMBA, FIFO, RAM, ROM, VHDL.
I. INTRODUCTION
Technological developments in the world
industrialization have allowed the integration of
more and more functions on the same digital
integrated circuit. Today, several microprocessors,
hardware accelerators, communications systems
diverse and with even operating systems. this allows
therefore perform all the functions necessary to
perform complex computer processing on the same
chip, hence the birth of the concept of systems on
chip (System on Chip), successors of specialized
circuits ASIC (Application Specific Integrated
Circuit) [1].
The choice of the communication system, in a
system On-chip, remains a major problem. This
choice depends on components constituting the
system and especially the processor used. SoCs
design software platforms, proposed by the
manufacturers of the FPGA circuits, proposes a
well-defined type of communication system [2].
These systems are generally standard buses modeled
in one language description of hardware like the
VHDL. Recently, with the aim of improving quality
and speed communication systems in new systems,
networks On-chip (NoC: Network-On-Chip) have
been introduced [3]. The principle of NoCs is to
ensure parallel between the components of a system
on chip.
The increase in computational capacity measured in
recent years in all device electronic is bound to
double flush with the miniaturization of
components, and then with the integration of
multiple structures on the same chip. Incorporating,
for example, on the same die (the chip of
semiconductor material that all enclosed inside of
the package is the real CPU chip) the
communication devices with the external
(coprocessors, Ethernet controller, controller USB,
memory controller, etc.) allows at the same time to
reduce in size and consumption but also to increase
the overall performance of the overall system
increasing the speed with which data can be
transferred between the different structures
integrated.
As increasing numbers of companies adopting the
AMBA system, it has rapidly emerged as the de-
facto standard for SoC interconnection and IP
library development. AMBA enhances a reusable
design methodology by defining a common
backbone for SoC modules.
In this work, the design and implementation of an
AMBA based Memory controller is proposed. The
AMBA based Memory controller gives an ease of
integration for sub-frame extraction of various data
structures in SOC. AMBA based interaction deals
with role specific operation. It is majorly categorized
in two dedicated feature i.e. decision (AHB
MASTER) and response (AHB SLAVE).
II. PROPOSED METHODOLOGY
AHB compliant’s master’s top architecture is
depicted in Figure 1.
IJDACR
ISSN: 2319-4863
International Journal of Digital Application & Contemporary Research
Website: www.ijdacr.com (Volume 5, Issue 7, February 2017)
Figure 1: Top architecture of AHB memory controller
Figure 2: Address generator of master
AHB
Master
AHB
Slave
AHB
Slave
Interface
Data
ADD
Counter
Memory
Controller
Interface
RAM
ROM
FIFO
WRAP4
LOGICAL
BLOCK
WRAP8
LOGICAL
BLOCK
WRAP16
LOGICAL
BLOCK
INCR,
INCR4
INCR8,
INCR16
LOGICAL
BLOCK
8:1 mux
BURST
&
OUTPUT
32 bit
Adder
2:1
Mux
Hsize
Mux
NON_SEQ HSIZE [2:0]
HBURST [2:0]
as_Haddr [31:0]
Sum output
From adder
HADDR [31:0]
SUM
IJDACR
ISSN: 2319-4863
International Journal of Digital Application & Contemporary Research
Website: www.ijdacr.com (Volume 5, Issue 7, February 2017)
Here in the proposed method FIFO is used for data
and control buffering. This is done with the goals of
assigning different clock cycles (CLK) to slave and
memory which in turn gives a fool proof
communication and also decrease the complexity.
Depending upon the READ and WRITE operations
data is further communicated through RAM or
ROM. Figure 2 shows the structural implementation
of Address generator block. While the Figure 3
shows the top structure of AHB master.
Figure 3: Top architecture of AHB master
Single Transfer
Logic for Single Transfer:
Address<=Address; (this is the address which is
coming from slave and it supports single transfer at
a time so the address is decided by input address
only and it is independent from size).
INCR
Logic For incrementing transfer for unspecified
length:
Case as_hsize(2:0) is
000=>
Address<= address+1;
001=>
Address<=address+2;
010=>
Address<=address+4;
100=>
Address<=address+16;
101=>
Address<=address+32;
When others=>
End case;
The above logic is written for unspecified
incrementing transfer, the address generation is
depends upon the As_hisze[2:0]. Which is coming
from salve .this address generation is generated in
sequential transfer,by simply incrementing of
previous address which is dependent on hsize.
WRAP4
Logic for 4 beat wrapping burst transfer:
Suppose that some address<= 34.
(hex_representation)
The second address will be address <=38.
(hex_code)
The third address will be address <=3C.
(hex_code)
The next address will be address <=30.
(hex_code)
These type of address we can achive from
following logic:
So the binary form of given hex code is,
34- 0011_0100.
2:1
Mux
Address
Generator
2:1
Mux
Counter
Controller
Interface of various
control
Sel
Sel
CPU add
Hsize
HTrans
HAdder
HAdder
Reg
IJDACR
ISSN: 2319-4863
International Journal of Digital Application & Contemporary Research
Website: www.ijdacr.com (Volume 5, Issue 7, February 2017)
38- 0111_0000.
3C- 0011_1100.
30- 0011-0000.
Therefore, if the start address of the transfer is 0×34,
then it consists of four transfers to addresses 0×34,
0×38, 0×3C and 0×30.
How to get: because the size of burst is word hence
I will add 4 to my address, at 16 byte boundary.
Second address:
256_128_64_32_16_8_4_2
𝑎𝑑𝑑𝑟𝑒𝑠𝑠: 0 0 1 1 0 1 0 0
This is kept unchanged + 1 0 0
0 0 1 1 1 0 0 0(𝒃𝒊𝒏𝒂𝒓𝒚_𝒄𝒐𝒅𝒆)
𝒂𝒅𝒅𝒓𝒆𝒔𝒔 <= 3 8 (𝒉𝒆𝒙_𝒄𝒐𝒅𝒆).
III. SIMULATION AND RESULTS
RTL schematic of MASTER has been shown in the
Figure 4. Synthesis has been carried out using Xilinx
14.5 ISE.
Figure 4: RTL view of Master
Figure 5: RTL view of memory controller
Figure 6: Simulation result of FIFO
Figure 7: Simulation result of AHB Master
Figure 8: Simulation result of memory controller
Figure 9: Simulation result of ROM
IJDACR
ISSN: 2319-4863
International Journal of Digital Application & Contemporary Research
Website: www.ijdacr.com (Volume 5, Issue 7, February 2017)
Figure 10: Simulation result of Slave and slave interface
IV. CONCLUSION
The work performed study and development that
followed has led the development of a memory
controller on AMBA AHB bus at a very innovative
phase and next to prototyping. The design has been
developed using VHDL code and synthesized using
Xilinx Spartan 3 device (3s100evq100-5). The
design claims a minor area overhead with
improvement in speed 185.134 MHz
REFERENCES [1] Shilpa Rao and Arati S. Phadke, “Implementation of
AMBA compliant Memory Controller on a FPGA”,
IJETEE, 2013.
[2] Archana C. Sharma, Prof. Zoonubiya Ali, “Construct
High-Speed SDRAM Memory Controller Using
Multiple FIFO's for AHB Memory Slave Interface”,
IJETAE, 2013.
[3] S. Lakshma Reddy, A. Krishna Kumari, “Architecture
of an AHB Compliant SDRAM Memory Controller”,
International Journal of Innovations in Engineering
and Technology, 2013.
[4] Arm AMBA 2 speciation. [Online]. Available at:
http://www.arm.com/products/solutions/AMBA
Spec.html
[5] Arun G, Vijaykumar T, “Improving Memory Access
time by Building an AMBA AHB compliant Memory
Controller”, IJARCET, 2012.
[6] Ch.Vijayalakshmi, Mr B. Raghavaiah,
“Implementation of AMBA AHB Compliant Memory
Controller with Peripherals”, ICITEC, 2012.
[7] Jayapraveen. D and T. Geetha Priya, “Design of
memory controller based on AMBA AHB protocol”,
Elixir International Journal, 2012.
[8] Kareemullah Shaik, Mohammad Mohiddin, Md.
Zabirullah, “A Reduced Latency Architecture for
Obtaining High System Performance”, IJRTE, 2012.
[9] Kees Goossens, Om Prakash Gangwal, Jens R¨over,
and A. P. Niranjan. Interconnect and Memory
Organization in SOCs for advanced Set-Top
Boxesand TV-Evolution, Analysis, and Trends. In Jari
Nurmi, Hannu Tenhunen, Jouni Isoaho, and Axel
Jantsch, editors, Interconnect-Centric Design for
Advanced SoC and NoC, chapter 15, pages 399–423.
Kluwer, April 2004.
[10] McGee, S.W.; Klenke, R.H.; Aylor, J.H.; Schwab,
A.J., “Design of a processor bus interface ASIC for
the stream memory controller”, IEEE, 1994.
[11] S. Ramakrishna, K. Venugopal, B. Vijay Bhasker, R.
Surya Prakash Rao, “HDL Implementation of AMBA-
Ahb Compatible Memory Controller”, IJCER, 2012.
[12] Shashi sekhar Ramagundam, Sunil R. Das, Scott
Morton, Satyendra N. Biswas, Voicu Groza, Mansour
H. Assaf, and Emil M. Petriu, “Design and
Implementation of High-Performance Master/Slave
Memory Controller with Microcontroller Bus
Architecture”, IEEE International Conference on
Instrumentation and Measurement Technology
(I2MTC) Proceedings, pp. 10 – 15, May 2014.
