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Computer Architecture (CS 493)

Name: Enanko Basak Roll Number: 1351047 Computer Science And Engineering 2nd Year

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DAY 1:

15 .01.2015 Data Flow Architecture for Basic Gates

AND GATE

Code:

entity and_gate is Port ( a : in std_logic; b : in std_logic; x : out std_logic); end and_gate;

architecture DataFlow of and_gate is

begin x

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OR Gate

Code:

entity or_gate is Port ( a : in std_logic; b : in std_logic; x : out std_logic); end or_gate;

architecture dataflow of or_gate is

begin

x

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XOR Gate

Code:

entity xor_gate is Port ( a : in std_logic; b : in std_logic; x : out std_logic); end xor_gate;

architecture DataFlow of xor_gate is

begin

x

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NOT Gate

Code:

entity not_gate is Port ( a : in std_logic; x : out std_logic); end notgt;

architecture dataflow of not_gate is

begin

x

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NAND Gate

Code:

entity nand_gate is Port ( a : in std_logic; b : in std_logic; x : out std_logic); end nand_gate;

architecture DataFlow of nand_gate is

begin

x

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NOR Gate

Code:

entity nor_gate is Port ( a : in std_logic; b : in std_logic; y : out std_logic); end nor_gate;

architecture DataFlow of nor_gate is

begin

y

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DAY 2: 22.01.2015 DataFlow Architecture for Basic Gates using Universal Gates.

AND GATE using NAND Gates

Code:

entity And_Nand is Port ( A : in std_logic; B : in std_logic; X : out std_logic); end And_Nand;

architecture DataFlow of And_Nand is

begin

X

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OR GATE using NAND Gates

Code:

entity Or_Nor is Port ( A : in std_logic; B : in std_logic; X : out std_logic); end Or_Nor;

architecture DataFlow of Or_Nor is

begin

X

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NOT GATE using NAND Gates

Code:

entity Not_nand is Port ( A : in std_logic; X : out std_logic); end Not_nand;

architecture DataFlow of Not_nand is

begin

X

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AND GATE using NOR Gates

Code:

entity ANo1 is Port ( A : in std_logic; B : in std_logic; X : out std_logic); end ANo1;

architecture DataFlow of ANo1 is

begin

X

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OR GATE using NOR Gates

Code:

entity Or_nor is Port ( A : in std_logic; B : in std_logic; X : out std_logic); end Or_nor;

architecture DataFlow of Or_nor is

begin

X

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NOT GATE using NOR Gates

Code:

entity not_or is Port ( A : in std_logic; X : out std_logic); end not_or;

architecture DataFlow of not_or is

begin

X

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Half Adder:

Code:

entity Half_Adder is Port ( A : in std_logic; B : in std_logic; S : out std_logic; C : out std_logic); end Half_Adder;

architecture DataFlow of Half_Adder is

begin

S

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Truth Table:

Sum: Carry :

Waveform:

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Full Adder

Code:

entity full_adder is Port ( A : in std_logic; B : in std_logic; Cin : in std_logic; Sum : out std_logic; Cout : out std_logic); end full_adder;

architecture DataFlow of full_adder is

begin

Sum

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Sum:

Truth Table: Sum: Carry:

Waveform:

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DAY 3: 29.01.2015 Behavioral Architecture of Basic Gates

AND Gate: Code:

entity and is Port ( A : in std_logic; B : in std_logic; X : out std_logic); end and; architecture Behavioral of and is begin

process(A,B) begin if(A='0') then X

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OR Gate

Code:

Entity or is Port ( A : in std_logic; B : in std_logic; X : out std_logic); end or;

architecture Behavioral of or is

begin process(A,B) begin if(A='1')then X

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NOT Gate

Code:

entity not is Port ( A : in std_logic; X : out std_logic); end behavnot;

architecture Behavioral of not is

begin process(A) begin if(A='0')then X

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NAND Gate Code:

entity nand is Port ( A : in std_logic; B : in std_logic; X : out std_logic); end nand; architecture Behavioral of nand is begin process(A,B) begin

if(A='0')then X

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NOR Gate Code:

entity nor is Port ( A : in std_logic; B : in std_logic; X : out std_logic); end nor;

architecture Behavioral of nor is

begin process(A,B) begin if(A='1')then X

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XOR Gate

Code:

entity xor is Port ( A : in std_logic; B : in std_logic; X : out std_logic); end xor;

architecture Behavioral of xor is

begin process(A,B) begin if(A=B)then X

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Half Adder: Behavioral Model

Code:

entity Half_Adder is Port ( A : in std_logic; B : in std_logic; C : out std_logic; S : out std_logic); end Half_Adder;

architecture Behavioral of Half_Adder is

begin process(A,B) begin if(A=B)then S

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Full Adder: Behavioral Model

Code:

entity Full_Adder is Port ( A : in std_logic; B : in std_logic; Cin : in std_logic; Cout : out std_logic; Sum : out std_logic); end Full_Adder;

architecture Behavioral of Full_Adder is

begin process(A,B,Cin) begin if(A='0')then if(B=Cin) then Sum

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Waveform:

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DAY 4: 5 . 02. 2015 Design 2:1 MUX using Behavioral and DataFlow

Behavioral:

Code: entity mux_b is Port ( S : in std_logic; I : in std_logic_vector(1 downto 0); Y : out std_logic); end mux_b;

architecture Behavioral of mux_b is

begin process(I,S) begin case S is when '0' => y y null; end case; end process;

end Behavioral;

Schematic Diagram:

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Truth Table:

Waveform:

MUX 2 : 1 Using Dataflow

Code:

entity mux_data is Port ( I : in std_logic_vector(1 downto 0); S : in std_logic; Y : out std_logic); end mux_data;

architecture DataFlow of mux_data is

begin

process(I,S) begin Y

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Schematic Diagram:

Truth Table:

Waveform:

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Design 4:1 MUX using Behavioral Code: entity mux_41 is Port ( I : in std_logic_vector(3 downto 0); S : in std_logic_vector(1 downto 0); Y : out std_logic); end mux_41;

architecture Behavioral of mux_41 is

begin process(I,S) begin case S is when "00" => Y Y Y Y null; end case; end process; end Behavioral;

DataFlow

Code: entity mux_data is Port ( I : in std_logic_vector(3 downto 0); S : in std_logic_vector(1 downto 0); Y : out std_logic); end mux_data;

architecture DataFlow of mux_data is

begin

process(I,S) begin

Y

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Design a Decoder using DataFlow and Behavioral Architecture

DataFlow

Code: entity 38decoder_d is Port ( B : in std_logic_vector(2 downto 0); D : out std_logic_vector(7 downto 0)); end 38decoder_d;

architecture DataFlow of 38decoder_d is

begin process(B) begin D

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Behavioral

Code:

entity 38mux_b is Port ( B : in std_logic_vector(2 downto 0); O : out std_logic_vector(7 downto 0)); end 38mux_b;

architecture Behavioral of 38mux_b is

begin process(B) begin O O(0) O(1) O(2) O(3) O(4) O(5) O(6) O(7) null; end case; end process;

end Behavioral;

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Design a 4:1 MUX using when-else

Code:

entity muxwhen is Port ( I : in std_logic_vector(3 downto 0); S : in std_logic_vector(1 downto 0); Y : out std_logic); end muxwhen;

architecture DataFlow of muxwhen is

begin Y

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DAY 5: 12 .02 . 2015

Design 4 bit ALU Behavioral

Code

entity alu_4bit_vhd is Port ( A : in std_logic_vector(3 downto 0); B : in std_logic_vector(3 downto 0); S : in std_logic_vector(2 downto 0); Y : out std_logic_vector(3 downto 0)); end alu_4bit_vhd;

architecture Behavioral of alu_4bit_vhd is

begin process(A, B, S) begin

case S is when "000" => Y Y Y Y Y Y Y Y NULL; end case; end process end Behavioral;

Truth Table: Select Line Operation

000 A And B 001 A Or B 010 A Xor B 011 Not A 100 A + B 101 A B 110 A + 1 111 A - 1

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Waveform :

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4-bit Comparator (DataFlow)

Code:

entity Comparator is Port ( A : in std_logic_vector(3 downto 0); B : in std_logic_vector(3 downto 0); Gr : out std_logic; Eq : out std_logic; Ls : out std_logic); end Comparator;

architecture Dataflow of Comparator is begin Gr B else '0'; Ls

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Parity Checker (Behavioral)

Code:

entityParity_checker is Port ( A : in std_logic_vector(3 downto 0); P_odd : out std_logic; P_even : out std_logic); endParity_checker;

architecture Behavioral of Parity_checker is begin process(A) variable temp : std_logic; begin temp := A(0) xor A(1); for i in 2 to 3 loop temp := temp xor A(i); end loop; P_odd

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DAY 5: 19 .02. 2015 Realisation Of Flip Flops

SR Flip Flop Behavioral

Code: entityS_R_FlipFlop is Port ( S : in std_logic; R : in std_logic; C : in std_logic; Q : out std_logic; Qout : out std_logic); endS_R_FlipFlop;

architecture Behavioral of S_R_FlipFlop is begin process(S,R,C) begin if(C'event and C='1') then if(S='0' and R='1')then Q

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D-Flip Flop

Code:

entityD_FlipFlop is Port ( D : in std_logic; C : in std_logic; Q : out std_logic; Qnot : out std_logic); endD_FlipFlop;

architecture Behavioral of D_FlipFlop is begin process(D,C) begin if(C'event and C='1') then if(D='0') then Q

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JK Flip Flop

Code:

entityJK_FlipFlop is Port ( J : in std_logic; K : in std_logic; C : in std_logic; Q :inoutstd_logic; Qnot :inoutstd_logic); endJK_FlipFlop;

architecture Behavioral of JK_FlipFlop is

begin process(J,K,C) begin if(C'event and C='1') then if(J='0' and K ='1')then Q

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T Flip Flop

Code: entity tff is Port ( T : in std_logic; C : in std_logic; Q : inout std_logic; QNOT : inout std_logic); end tff;

architecture Behavioral of tff is

begin process(T,C) begin Q

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UP Counter

Code:

entityUP_Cnt is Port ( C : in std_logic; clear : in std_logic; Q : out std_logic_vector(2 downto 0)); endUP_Cnt;

architecture Behavioral of UP_Cnt is

Signal tmp :std_logic_vector(2 downto 0); Begin

process(clear,C) begin if(clear = '1')then tmp

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Down Counter:

Code: entity Dn_Cnt is Port ( C : in std_logic; clear : in std_logic; Q : out std_logic_vector(2 downto 0)); endDn_Cnt;

architecture Behavioral of Dn_Cnt is

Signal tmp :std_logic_vector(2 downto 0);

begin process(clear,C) begin if(clear = '1')then tmp

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DAY 6: 26 . 02 .2015 Full adder using two half adders (Structural approach)

Code: entityFull_Adder_s is Port ( x : in std_logic; y : in std_logic; cin : in std_logic; sum : out std_logic; cout : out std_logic); endFull_Adder_s;

architecture Structural of Full_Adder_s is componentHalf_adder is Port ( A : in std_logic; B : in std_logic; S : out std_logic; C : out std_logic); end component;

signali,j,k : std_logic;

begin ha1: Half_adder port map (x,y,i,j); ha2: Half_adder port map (i,cin,sum,k); cout

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Waveform:

Ripple Carry Adder Code:

entityRipple_carry_adder is Port ( x : in std_logic_vector(3 downto 0); y : in std_logic_vector(3 downto 0); cin : in std_logic; sum : out std_logic_vector(3 downto 0); carry : out std_logic); endRipple_carry_adder;

architecture Structural of Ripple_carry_adder is

componentFull_adder_impl is Port ( A : in std_logic; B : in std_logic; Cin : in std_logic; S : out std_logic; Cout : out std_logic); end component;

signal c1,c2,c3 : std_logic; begin fa1 :Full_adder_impl port map (x(0),y(0), cin ,sum(0),c1); fa2 :Full_adder_impl port map (x(1),y(1), c1 ,sum(1),c2); fa3 :Full_adder_impl port map (x(2),y(2), c2 ,sum(2),c3); fa4 :Full_adder_impl port map (x(3),y(3), c3 ,sum(3),carry); end Structural;

Waveform:

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Adder Subtractor Composite Unit Code

entity Composite_adder is Port ( x : in std_logic_vector(3 downto 0); y : in std_logic_vector(3 downto 0); cin : in std_logic; sum : out std_logic_vector(3 downto 0); carry : out std_logic); end Composite _adder;

architecture Structural of Composite_adder is

componentFull_adder_impl is Port ( A : in std_logic; B : in std_logic; Cin : in std_logic; S : out std_logic; Cout : out std_logic); end component;

signal t : std_logic_vector(3 downto 0); signal c1,c2,c3: std_logic;

begin t(0)

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Full Adder using loop (Structural)

Code: entityRipple_carry_adder is Port ( x : in std_logic_vector(3 downto 0); y : in std_logic_vector(3 downto 0); cin : in std_logic; sum : out std_logic_vector(3 downto 0); carry : out std_logic); endRipple_carry_adder;

architecture Structural of Ripple_carry_adder is

componentFull_adder_impl is Port ( A : in std_logic; B : in std_logic; Cin : in std_logic; S : out std_logic; Cout : out std_logic); end component;

signal t : std_logic_vector(3 downto 0); signal c: std_logic_vector(4 downto 0);

begin c(0)

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DAY 8: 2 .03. 2015

8to1 MUX(Structural) Code:

entity mux81 is Port ( I : in std_logic_vector(7 downto 0); S : in std_logic_vector(2 downto 0); Y : out std_logic); end mux81;

architecture Structural of mux81 is

component Mux4_dataflow is Port ( I : in std_logic_vector(3 downto 0); S : in std_logic_vector(1 downto 0); Y : out std_logic); end component;

component mux_2 is

Port ( I : in std_logic_vector(1 downto 0); S : in std_logic; Y : out std_logic); end component; signalya: std_logic_vector(1 downto 0); begin mux1 : Mux4_dataflow port map (I(3 downto 0),S(1 downto 0),ya(0)); mux2 : Mux4_dataflow port map (I(7 downto 4),S(1 downto 0),ya(1)); mux3 : mux_2 port map (ya(1 downto 0),S(2),Y);

end Structural;

RTL Schematic:

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Waveform:

4-bit Serial In Serial Out Register Code:

entity SISO is Port ( I : in std_logic; C : in std_logic; Q1 : inout std_logic_vector(3 downto 0); QNOT1 : inout std_logic_vector(3 downto 0)); end SISO;

architecture Structural of SISO is

component dff is Port ( D : in std_logic; C : in std_logic; Q : out std_logic; QNOT : out std_logic); end component; begin

d1: dff port map(I, C, Q1(0), QNOT1(0)); d2: dff port map(Q1(0), C, Q1(1), QNOT1(1)); d3: dff port map(Q1(1), C, Q1(2), QNOT1(2)); d4: dff port map(Q1(2), C, Q1(3), QNOT1(3));

end Structural;

Schematic Diagram:

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Waveform: