Architecture-Level Power Modeling

Slide 1

U.Va.Department of Computer Science LAVA

Architecture-LevelPower Modeling

N. Kim, T. Austin, T. Mudge, and D. Grunwald. “Challenges for Architectural Level Power Modeling.”

In Power Aware Computing, (R. Melhem and R. Graybill eds.), Kluwer, 2001.

Kevin Skadron

Mircea Stan

Slide 2


Who Cares?

Power is now a first-level design constraint for both embedded/mobile and high-performance/general-purpose processors

Battery life (eg, laptops) Heat removal and package cost Degradation and lifetime

Architects don’t have good tools to model this

Slide 3


Modeling

What architects normally do: model behavior/performance at the cycle level (eg, SimpleScalar)Many abstractions and simplifications

–Examples: I-cache, memory buses

Faster than a more detailed model; still good enough

Power and heat, however, require more implementation detail

Current power-performance simulators try to omit the extra detail by using abstractions or analytic models

Slide 4


Current Arch.-Level Power Simulators

Wattch (Brooks et al.)Doesn’t model anything outside the core (eg, external bus)CACTI-based models for large structures (cache, branch

predictor, register file, instruction window, etc.)–Tuned using Intel data

SimplePower (Vijaykrishnan et al.)Adds bus and memory modeling, also I/O padsLook-up-tables (LUTs)

Tempest (Cai & Lim)Power densityChip-level thermal modeling

No one: data sensitivity, clock tree, global interconnect

Slide 5


Typical Power-Performance Modeling

Technologyparameters

Micro-arch.config

Staticpower model

Cycle-accurate

performancemodel

Dynamicpower

estimationactivityfactors

cycle-by-cyclestatistics

Slide 6


Power Basics

P = ½ACV2f + AVIshort + VIleak

A = activity factor C = capacitance V = dynamic voltage f = frequency

Ishort = short-circuit current during switching

Ileak = leakage current

Slide 7


Power Basics


P = ACVDDVswingf + AVIshort + VIleak

A = activity factor C = capacitance V = dynamic voltage f = frequency

Ishort = short-circuit current during switching

= duration of short-circuit current

Ileak = leakage current

Why averages don’t work:Bursty behavior, dI/dt, peak current, temperature

Slide 8


Better Simulation Method

P = ACVDDVswingf + AVIshort + Vileak

sum over all blocks

Slide 9


Typical Power-Performance Modeling

Technologyparameters

Micro-arch.config

Staticpower model

Cycle-accurate

performancemodel

Dynamicpower

estimationactivityfactors

cycle-by-cyclestatistics

Slide 10


Metrics

What metrics do we care about?Execution time [sec or IPC]Energy (battery life) [W]Energy-delay product [Ws]Energy-delay2 product? [Ws2]Power density (temperature) [W / mm2]Temperature [K or °C]DI/dtPeak power dissipation

Might also care about these at finer granularities:micro-arch. blocks, decoders, circuits, etc.

Slide 11


Basic Techniques for Power Efficiency

Leakage: turn things off (but you lose the data)Resize structuresTurn off idle structuresTurn off entries, eg cache decay4T RAM cells?

Dynamic: reduce activity factorsClock gatingResize structures “Utility” predictorThrottle processor width (eg, fetch width)Filter cachesDatapath resizingetc.


Slide 12


Simulating Power for Greater Accuracy


In all these cases, we want to find relevant power-related parameters (esp. effective switching capacitance C)

-- performance model provides A

More detailed block-specific power information(circuit design style, etc.)

Switching activity (Hamming distance) Interconnect (floorplanning, approx. area) Clock tree (H-tree vs. balanced H-tree) Random logic (empirical models) Busses, transactions, durations (pull-up/pull-down/hi-Z, read

vs. write, etc.)

Slide 13


Simulation Challenges

Need leakage models - f(T) Need temperature models Eventually want to integrate all these into a fast simulator

This is a research challenge in its own right

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Architecture-Level Power Modeling