Architecture Analysis and Evaluation - CORDIS...“Optimization and Analysis Tool”, September 2013 PowerSWIPE (Grant agreement 318529) page 4 of 72 1. Introduction This report details

FP7-ICT-2011-8 – Collaborative Project (STREP)

PowerSWIPE (Grant agreement 318529)

Objective ICT-2011.3.1 – Very advanced nanoelectronic components: design,

engineering, technology and manufacturability

PowerSWIPE (Project no. 318529)

“POWER SoC With Integrated PassivEs”

D2.1: Status Report

“Architecture Analysis and

Evaluation” Dissemination level: PUBLIC

Responsible Beneficiary

Centro de Electrónica Industrial, Universidad Politécnica de Madrid

“Optimization and Analysis Tool”, September 2013


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Summary

Name Optimization and Analysis Tool

Status Due Month 12 Date 30-September-2013

Author(s) Vladimir Šviković, Jorge Cortes, Pedro Alou, Jesús Ángel Oliver

Editor(s) Vladimir Šviković, Jorge Cortes, Pedro Alou, Jesús Ángel Oliver

DoW Report on Optimization and Analysis Tool

Dissemination

Level PUBLIC

Nature Report

Document history

V Date Author Description

Draft 15-September-2013 Vladimir Šviković Draft

Final 15-October-2013 Jesús Ángel Oliver



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Content

1. Introduction ............................................................................................................................................... 4

2. High Voltage DC-DC Converter System (HVDC-DC) ............................................................................. 5

2.1. ISO pulses ......................................................................................................................................... 5

2.2. HVDC-DC topologies....................................................................................................................... 6 2.2.1. HV technology challenges ....................................................................................................... 6 2.2.2. Option A: Single-phase Buck converter................................................................................... 6 2.2.3. Option B: Switched capacitors converter + Single-phase Buck converter ............................... 7 2.2.4. Option C: External protection + Single-phase Buck converter ................................................ 8 2.2.5. Conclusions ............................................................................. Error! Bookmark not defined.

3. Low Voltage DC-DC Converter System (LVDC-DC) and Computer Aided Design Tool (CAD) ......... 11

3.1. Graphic User Interface (GUI) ......................................................................................................... 12 3.1.1. Power Stage Specification part .............................................................................................. 12 3.1.2. System Specification part and Dynamic Test part ................................................................. 13 3.1.3. Dynamic Tests part ................................................................................................................ 14 3.1.4. Control part ............................................................................................................................ 14

3.2. Structure of the Software ................................................................................................................ 15 3.2.1. Main Functions ...................................................................................................................... 16 3.2.2. Optimization Functions .......................................................................................................... 16 3.2.3. Analysis Functions ................................................................................................................. 17 3.2.4. Simulation and Presentation Functions .................................................................................. 17 3.2.5. Modeling Functions ............................................................................................................... 19

3.3. Models ............................................................................................................................................ 22 3.3.1. Magnetics model .................................................................................................................... 22 3.3.2. Capacitor model ..................................................................................................................... 23 3.3.3. Semiconductor model ............................................................................................................ 25 3.3.4. Converter models ................................................................................................................... 31

3.4. Algorithms ...................................................................................................................................... 40 3.4.1. Single-variable single-point search algorithm ........................................................................ 40 3.4.2. Steady-state operating point calculation ................................................................................ 40 3.4.3. Steady-state Losses calculation .............................................................................................. 44 3.4.4. Single-variable multi-point search algorithm ......................................................................... 48 3.4.5. Optimization function algorithm ............................................................................................ 49 3.4.6. Analysis function algorithm ................................................................................................... 50

3.5. Results of the Optimization ............................................................................................................ 54

4. Conclusions and future work ................................................................................................................... 58

5. References ............................................................................................................................................... 59

APPENDIX I .................................................................................................................................................. 61

APPENDIX II ................................................................................................................................................. 66



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1. Introduction

This report details Architecture Analysis and Evaluation of Power Swipe project system [1], targeted for

automotive power supply and distribution system. Current trends in automotive industry [2] are showing

significant increase of car electronics, shifting the functionality form mechanical to electrical systems.

According to the study, during the period 1993-2008, vehicle production has increased by 44%, while the

automotive electronic content has grown by 155% and the semiconductor content by 325%. These growing

trends are imposing efficiency and miniaturization as main drivers for power supply system due to the mass and

CO2 reduction. On the other hand, different studies of the trends in power electronics [3]-[7] are showing that

significant effort is invested in integration and miniaturization of the power system. Special effort is given to

implementation of the passives [8]-[14] and improvement of the semiconductor design and models for losses

estimation [15]-[20].

Figure 1. Power Swipe System.

Power Swipe project system, having in mind current trends, is proposing a fully integrated solution for

automotive power supply chain from the battery to a microcontroller. The system, presented in Fig. 1, is

composed of two integrated sub-systems where the first, Demonstrator 1, is used to stabilize the input voltage

from the battery to a bus voltage and the second, Demonstrator 2, which consists of two Point-of-Load DC-DC

converters and its corresponding micro-processor loads. Both subsystems are designed using Infineon

semiconductor technology [21], Tyndall inductor technology [22] and IPDiA capacitor technology [23]. In order

to improve system performance, both subsystems are optimized with closed loop considering the impact of the

dynamics on the system design. Therefore, the system is analyzed under various control technics [24]-[29].

The report is composed of two parts where the first part is dedicated to the High Voltage DC-DC Converter

System (HVDC-DC), while the second details the Computer Aided Design Tool (CAD) designed for system

level optimization and analysis of a Low Voltage DC-DC Converter (LV-DCDC) of Power Swipe project

system.



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2. High Voltage DC-DC Converter System (HVDC-DC)

This chapter evaluates several topologies for the HVDC-DC converter. The main problem is the electrical

transients that the converter has to withstand. This report is divided in two sections where the ISO pulses are

explained and three topologies are evaluated according to the voltage rating needed for the components.

2.1. ISO pulses

Although the standard battery voltage rating of PowerSwipe requirements is from 6V to 16V with a nominal

voltage of 14V, the battery car suffers from several electrical transients that severely affect the design of the

high-voltage topology. These transients only affect the battery at certain moments such as in the start-up of the

engine. The automotive electrical transients are represented by the ISO pulses where the waveforms of the

transients are defined and the behavior of the converter during these transients is explained.

The behavior of the converter during the electrical transients is classified in three classes:

CLASS A: All functions of the device/system perform as designed during and after the test.

CLASS B: All functions of the device/system perform as designed during the test. However, one or more of

them may go beyond the specified tolerance. All functions return automatically to within normal limits after

the test. Memory functions shall remain class A. It shall be specified by the vehicle manufacturer which

function of the DUT must perform as designed during the test and which function can be beyond the

specified tolerance.

CLASS C: One or more functions of a device/system do not perform as designed during the test, but return

automatically to normal operation after the test.

The most severed ISO pulses are shown below:

R-1.1.34: Overvoltage of 40V. The generator regulator fails and the battery voltage can be above 14V for

400ms. Class A.

Figure 2. First vervoltage pulse of 40V.

R-1.1.48: Overvoltage of 40V. Due to a dynamo effect when battery is disconnected and the vehicle

wheels are steered. Class A.

Figure 3. Second overvoltage pulse of 40V.

R-1.1.32: Cranking pulse. Undervoltage of 4.5V. Class B when below 5V.



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Figure 4. Fitst undervoltage pulse of 4.5V.

R-1.1.37: Discontinuities in the supply voltage. Undervoltage of 4.5V. Class B when below 5V.

Figure 5. Second undervoltage pulse of 4.5V.

R-1.1.36: Reversed voltage of -14V. The converter cannot break when applying -14V for 60s. Class C.

To sum up the requirements, the converter needs to work within required tolerances when there is an

overvoltage up to 40V, it can work outside required tolerances for undervoltages below 5V and it cannot break

when applied a reversed voltage of -14V.

2.2. HVDC-DC topologies

In order to meet the requirements of the PowerSwipe project, several topologies are evaluated. As the main

concern is the feasibility of integrating high voltage components, the evaluation of the topologies is made

according to the voltage rating needed for each component.

2.2.1. HV technology challenges

The use of high voltage integrated components represents a great challenge:

Infineon MOSFETs will use SPT9 (Smart Power) technology [30] which can be of 20V or 40V voltage

rating. The 20V technology is better in terms on conduction and switching losses.

The reliability of the HV IPDiA capacitors highly depend on the voltage applied to the capacitors. The

design of the capacitors would be less challenging if the maximum voltage applied to the capacitor does not

surpass 20V.

The design of the HV inductors by Tyndall is also very challenging. Due to space constraints, several

laminations of the core might be needed to reduce the size and the losses of the inductor. Consequently, a 40V

inductor might not be feasible with the current technology and the use of a 20V inductor would be very

beneficial for its design.

For these reasons, solutions for the HVDC-DC converter that use 20V components need to be evaluated.

2.2.2. Option A: Single-phase Buck converter

A Buck converter (Fig. 6) with 40V MOSFETs with SPT9 technology [30] and high voltage capacitor

technology could withstand the 40V battery voltage transients. However, a high voltage integrated inductor may

not be feasible due to space restrictions. Furthermore, the use of 40V technology greatly worsens the efficiency

of the system.



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Figure 6. Buck converter

Table I shows the maximum voltage stored in the capacitors and the maximum voltage blocked by the

switches at their worst-case which is when Vbat = 40V.

TABLE I. VOLTAGE RATING OF COMPONENTS OF BUCK CONVERTER TOPOLOGY

Maximum voltage in capacitors Maximum voltage in switches Maximum voltage across inductor

Cin 40V S1, S2 40V L 35V

Co 5V

The voltage rating of the input capacitor, the switches and the inductor must be over 40V.

Also, in order to protect the converter against a short-circuit of the input due to a reversed input voltage, a

diode has to be placed in series with the battery voltage to disconnect the converter (Fig. 7)

Figure 7. Option A: Buck converter with a diode in series with the battery voltage to protect against reversed battery voltage.

2.2.3. Option B: Switched capacitors converter + Single-phase Buck converter

This is a two-stage topology composed by a switched capacitors (SC) converter and a single-phase Buck

converter (Fig. 8). Several switched capacitor converter topologies were evaluated and the Ladder topology was

chosen because it is the topology where the lower needed voltage rating of the switches and capacitors [31].

In normal operation where the battery voltage has a nominal voltage of 14V, the SC converter is short-

circuited by activating the switch Sbypass so that the battery voltage, Vbat, is connected to the input of the Buck

converter, Vint. When Vbat surpasses a certain threshold (for example 20V), the switch Sbypass is deactivated and

the SC converter starts to work. The SC converter provides a fixed ratio 1:3 so Vin = Vbat/3. At Vbat = 30V, Vint =

10V and when Vbat = 40V which is the maximum battery voltage, Vin = 14V.

Figure 8. Option B: SC converter and Buck converter

Table II shows the maximum voltage stored in the capacitors and the maximum voltage blocked by the

switches at their worst-case, which for the SC converter is when Vbat = 40V and for the Buck converter is when

Vint = 20V.



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TABLE II. VOLTAGE RATING OF COMPONENTS OF SC CONVERTER + BUCK CONVERTER TOPOLOGY


C1, C2, C3 14V S1, S2, S3, S4, S5, S6 7V L 15V

Cint 20V Sbypass 27V

Cin 40V SH, SL 20V

Co 5V

As seen only the input capacitor of the SC converter, Cint, needs to have a voltage rating of 40V. The voltage

ratings of the components of the Buck converter have been drastically reduced with this two-stage approach.

The rating of the switches changed from 40V to 20V and the rating of the inductor changed from 35V to 15V.

With this solution, 20V SPT9 technology can be used for the MOSFETs and the bypass MOSFET could be

placed outside the chip, achieving greater efficiency.

Fig. 9 shows the operation of the SC converter + Buck converter topology. The figure shows the battery

voltage, Vbat, in green, the threshold voltage of 20V in blue and input voltage of the Buck converter, V int, in red.

When the battery voltage is below 20V, then Vint is equal to Vbat. When the battery voltage is above 20V, then

Vint is 1/3Vbat, and, consequently, the input voltage of the Buck converter is kept always below 20V.

Figure 9. Operation of the SC converter and Buck converter topology

2.2.4. Option C: External protection + Single-phase Buck converter

As in normal operation the maximum voltage battery is 16V, it makes sense to study the addition of an

external IC protection circuit that protects the converter from the electrical surges and, consequently, the design

of the converter can be optimized for the normal operation. Then, in the case of adding an external protection

circuit, it has to offer overvoltage protection and protection against negative input voltage and, optionally, also

undervoltage protection.

Several commercial Off-The-Shelf chips that protect from the most severe ISO pulses are available. They are

specific for the automotive electrical transients and therefore they are automotive qualified. A concern is that all

of them need additional circuitry although some of the components could be integrated in the same chip of the

HVDC-DC converter.

MAX16127: this IC (Fig. 10) [32] tolerates a battery voltage from -36V to +90V. It offers overvoltage and

Undervoltage protections which are set with the resistances R3, R4 and R1, R2, respectively. Also, it presents

protection against negative battery voltage. If the voltage battery overpasses the overvoltage value, the IC

enters into a single-phase PFM mode that regulates the voltage that is entering into the DC-DC converter

(Fig. 11).



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Figure 10. MAX16127 with additional circuitry.

Figure 11. Overvoltage protection limiter.

MAX16129: this IC (Fig. 12) [33] has the same specifications as MAX16127 but the overvoltage and

Undervoltage protection are predetermined and thus, the additional circuitry is reduced. Depending on the

numbering part, the overvoltage can be 15V, 18.6V or 20.93V. The Undervoltage can be 3V or 5V. For the

specifications of the PowerSwipe project, and overvoltage limit of 18.6V and an Undervoltage limit of 3V

would be enough.

Figure 12. MAX16129 with additional circuitry.



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LT4356: this IC (Fig. 13) [34] does not present undervoltage protection but this is not a requirement for the

PowerSwipe specifications. LT4356 presents overvoltage (Fig. 14) and overcurrent protection plus

protection against negative battery voltage.

Figure 13. LT4356 with additional circuitry.

Figure 14. Overvoltage protection limiter.

Fig. 15 shows the proposed architecture of a Buck converter with an external protection circuit.

Figure 15. Option C: Buck converter with external protection circuit.

With this solution, SPT9 technology of 20V can be used for the MOSFETs and the design of the capacitors

and the inductor greatly improves (Table III).

TABLE III. VOLTAGE RATING OF COMPONENTS OF BUCK CONVERTER TOPOLOGY.


Cin 18V S1, S2 18V L 13V

Co 5V



page 11 of 72

3. Low Voltage DC-DC Converter System (LVDC-DC) and Computer

Aided Design Tool (CAD)

This chapter details the Computer Aided Design Tool (CAD) designed for system level optimization and

analysis of a Low Voltage DC-DC Converter (LV-DCDC) of Power Swipe project system. The primary

objective of the project is full integration of the LV-DCDC converter with its load using state of the art

technology while achieving the highest possible efficiency. Various architectures have been analyzed as a

potential solution operating both in Continues-Conduction-Mode (CCM) and Discontinues-Conduction-Mode

(DCM) using different controlling methods. After preliminary analysis, based only on conduction losses,

considering available technology, the following topologies, shown in Fig. 16, are chosen as candidates for final

design:

a) Single-Phase Synchronous Buck Converter operating in CCM and/or DCM mode with Voltage Mode

Control (VMC), Fig. 16a, or Peak Current Mode Control (PCMC), Fig. 16b,

b) Two-Phase Buck Converter operating in CCM and/or DCM mode with PCMC, Fig. 16c, and

c) Coupled Two-Phase Buck Converter operating in CCM mode with PCMC, Fig. 16d.

Figure 16. LV-DCDC Converter topologyes: a) Single Phase Synchronous CCM/DCM – VMC Buck Converter, b) Single Phase

Synchronous CCM/DCM – PCMC Buck Converter, c) Two-Phase Synchronous CCM/DCM – PCMC Buck Converter and d) Coupled Two-

Phase Synchronous CCM– PCMC Buck Converter.

The CAD tool performs system level optimization for each topology operating only in CCM or in CCM and

DCM mode (depending on the topology) varying system level parameters and it saves the results in a output file

which can be loaded for the analysis. The models used are based on the models provided by the manufactures or

the models derived from measurements also provided by the manufactures. The system parameters that can be

varied are the capacitance of the output capacitor, inductance of the output inductor or leakage inductance in the

case of the Coupled Two-Phase Buck and the widths of the power MOSFETs. While optimizing the system,

considered designs need to satisfy both static and dynamic constrains imposed by the user.

Additionally, the CAD tool can perform analysis of chosen topology, providing an insight on the system

behavior both static and dynamic. Regarding the static behavior, the CAD tool can provide time-domain

waveforms of the system variables as well as losses breakdown in three points of operation: typical load,

minimal load and maximal load. On the other hand, running dynamic tests the user can obtain bode-plots of the

open-loop and closed-loop transfer functions and regulator design. Furthermore, the tool can perform time-

domain tests presenting reaction of the system on the load or input voltage jumps. Finally, the tool can calculate

what are the minimal input and output capacitance for a given system which are satisfying specifications.

This report consists of two chapters. In the first the CAD tool is explained in details. Firstly, the Graphic-

User-Interface (GUI) is presented following the structure of the software and the used models. After,

Optimization algorithm and Analysis are presented. The third chapter of this report is dealing with obtained

results of performed optimizations. Finally, conclusions are presented in the fourth chapter, followed by the

used literature.

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a) b)

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c) d)



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3.1. Graphic User Interface (GUI)

Graphic User Interface is presented in Fig. 17. It is consisted of five main parts used to define the system and

its static specification:

1. Power Stage Specification,

2. System Specification,

3. Dynamic tests,

4. Control and

5. Status field.

Figure 17. Graphic User Interface (GUI) of the CAD tool.

3.1.1. Power Stage Specification part

Power Stage Specification part is used to define parameters of the power stage and it is divided into

Capacitors section, Inductor section, MOSFETs section and it has a control section where the user can load

design obtained by an optimization.

The Capacitor section is used to define the values of the output and input capacitors for analysis. The section

has two fields where the user can define the values of the input and output capacitance for analysis purposes

and, in addition, the results, obtained by optimization, can be loaded to those fields. Further, for optimizations, a

user can define the precision of the capacitance, capacitance density and the available area for both capacitors.

The precision of the capacitance is a parameter which is used in optimization algorithm and it finishes the

optimization process when the optimal capacitance range is reduced to a value less than the one defined by the

parameter. The capacitor density and area are defining the biggest capacitors that can be placed in the die with

assumptions that both input and output capacitors are the same and that 70 % of the area can be used for

capacitors while the rest is used for interconnections and Thought-Silicon-Vias (TSV). In addition, the

Capacitor section has two fields where maximum peak-to-peak voltage ripples of the both input and the output

capacitors are loaded from the results files obtained from the optimizations. The last four fields represent

parasitic series impedance of the output and input capacitors and they are used for both optimization and

analysis. These impedances represent equivalent impedances of Thought-Silicon-Vias (TSV) used to

interconnect the interposer and they are modeled as equivalent series resistance and inductance.

The Inductor section is used to define the output inductor of the power stage in the case of Single-Phase and

Two-Phase Buck converter or to define the leakage inductance in the case of Coupled Two-Phase Buck

converter. The first field is used to define the value of the inductance for analysis and to this field the results of

the optimization can be loaded. Further, for optimizations, a user can define the maximal inductance allowed in

the system, the precision of the inductance, maximal peak-to-peak inductor current value, the metal strip

thickness (used both for analysis and optimization) and the available area for the magnetics. The maximal



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inductance value is parameter which is defining initial maximum value of the optimal range of inductor value

(the details of the algorithm will be explained later). The precision of the inductance, as in the case with

capacitance precision, is used to terminate the optimization of the inductance when the optimal inductance range

is reduced to a value less than the one defined by the parameter. The maximal peak-to-peak inductor current

value is used to limit both the maximal peak current in the system and the minimal inductance. The metal strip

thickness parameter is used for estimation of the high-frequency losses in the magnetics, while the available area

is used to define the maximal area that can be occupied by the magnetics. Furthermore, the inductor section has

an output field where the maximal peak-to-peak ripple can be loaded from the results of the optimizations. The

two last fields define equivalent series RL impedance of TSVs.

MOSFETs section is used to define semiconductors parameters and it is divided into three sub-sections: HI

side (Pmos), LOW side (Nmos) and Dead Time section. The HI side and LOW side sub-sections are defining

parameters of the corresponding MOSFETs and they consist of the same fields. A user can define the widths of

the MOSFETs for analysis and the minimal and maximal values of the widths for the optimizations. Further, a

user can choose the driving gate-to-source voltage and maximal gate current. The last field is dynamically

providing an on resistance of the defined MOSFET based on the previous parameters. Dead time sub-section is

defining durations of the turn-on and turn-off transients and they are used in dynamic losses estimations.

Figure 18. Loading contol pop-up menu.

The loading results control section is used to load results of the optimizations in to the CAD tool for later

analysis and it consists of pop-up menu, presented in Fig. 18, and load control button, presented in Fig. 17. A

user can select the solution from the pop-up menu and based on the selected switching frequency, if the

optimization has been performed, the solution will be loaded in to the tool. In the case that optimization has not

been performed a warning note is shown.

3.1.2. System Specification part and Dynamic Test part

System Specification part is used to define static specification of the system and it consists of switching

frequency field, number of harmonic field, Output section, Input section, Load section and Target Efficiency

section. All fields and sections of the System Specification part are used both for analysis and optimization. The

switching frequency field is used to define the operating frequency of the system, assuming that for Two-Phase

systems the phases are phase shifted by 180 degrees. The number of harmonic field is used for estimation of the

high-frequency losses in the magnetics together with the metal strip thickness of the magnetics. A user can

define with this parameter how many harmonic components of the inductor current will be considered for the

calculations of the losses.

The Output section defines the output voltage specifications such as the nominal output voltage, the static

peak-to-peak output voltage ripple, for the steady-state operation, and dynamic peak-to-peak output voltage

ripple for dynamic tests. The Input section is used to define the input voltage characteristics such as nominal

input voltage, the static peak-to-peak input voltage ripple, for the steady-state operation, and dynamic peak-to-

peak input voltage ripple.

The Load section defines three static operating points of interest: typical load current, which is used as a load

for the optimization process, maximal load current and minimal load current. On the other hand, the Target

Efficiency section is defining for its corresponding load currents minimal desirable efficiency and it will be used

in later versions of the tool to define the cost function for the optimal design considering all three operating

points.



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3.1.3. Dynamic Tests part

Dynamic Test part is used to define the dynamic tests of the system and it consists of two sections: Load

Step section and Input Voltage section. The tests are used for analysis of the system.

The Load step section has two fields where the first is defining the amplitude of a load step, while the second

is defining its settling times. A user can define several Load-steps by separating the values with comma. In order

to proper functioning, there must be the same number of the amplitudes as settling times. Assuming that the load

steps are occurring with constant frequency and 50% duty cycle, the mean value of the output current is half of

the maximal current defined in System Specification part, Load section.

Similarly, the Input Voltage steps section consists of two fields, where the first is defining the amplitude of

the step, while the second is defining its settling time. Again, a user can define several steps by separating the

values by comma. The mean value of the input voltage is equal to nominal input voltage defined in System

Specification part, Input section.

3.1.4. Control part

Control part is used to control the CAD tool. It consists of Topology Control section, which is used to select

the topology, operating mode and control, and controlling section where the user can select what the CAD tool

will do. Additionally, in the case when the Coupled Two-Phase Buck is selected, a user can define what is

magnetizing inductance of an equivalent transformer. A user can select several topologies to perform

successively optimizations or analysis.

In the controlling section, a user can select will the CAD tool perform optimization or analysis (they are

mutually exclusive) of topologies selected in the Topology Control section. In the case of analysis, the user can

select the types of analysis between Static Behavior, Dynamic Behavior and Minimal Capacitor Calculations.

The Static Behavior demonstrates static characteristics of the system and the CAD tool plots for each

selected load current, defined in System Specification part, time domain waveforms of all state variables of the

system and breakdown of the losses. In addition, if selected, the CAD tool performs a sweep of efficiency from

the minimal load current to the maximal load current.

The Dynamic Behavior demonstrates dynamic characteristics of the system and the CAD tool can present

regulator design with open-loop and closed-loop transfer functions. Furthermore, a user can perform Load-steps

or Input Voltage steps, defined in Dynamic Test part, and the CAD tool plots them in time domain.

Minimal Capacitor Calculations are calculating the minimal capacitors, both input and output independently,

which are satisfying both static and dynamic specifications for a given inductor and semiconductor design. This

provides a user an information what is the cost of reduction of the capacitors in terms of efficiency and dynamic

behavior.



page 15 of 72

3.2. Structure of the Software

The Computer Aided Design Tool (CAD tool) has been written in Matlab 7.10.0.499 (R2010a) using built-in

tool of the software. The structure of the CAD tool is presented in Fig. 19 and the tool consists of three main

parts: GUI (defined by PowerSwipeGUI.fig and PowerSwipeGUI.m), data loader (defined by load_data.m) and

main function (defined by PowerSwipeOptimization_v2.m).

The two GUI functions are obtained using Matlab GUI toolbox and PowerSwipeGUI.fig represents the

graphical part of the GUI where all the objects are defined, while PowerSwipeGUI.m is its corresponding m-file

with kernel and callback functions. The most of the callback functions are void functions except the checkboxes

of the Control part which are mutually dependent. The higher level checkboxes, when checked, activate the next

corresponding level of the checkboxes, and when unchecked, they deactivate the lower level of checkboxes. In

addition, the edit fields of MOSFETs section in Power Stage Specification part have callback functions which

are recalculating on-resistance of corresponding MOSFETs every time when some of the MOSFET input

parameters changes and load it in Ron field. The GUI has two Push-buttons whose callback functions are

activating data loader (pressing Load Design kernel calls load_data.m) and the main function (pressing RUN

activates PowerSwipeOptimization_v2.m). Aside of mentioned functions, the tool is using excel files to store

results of optimizations and to load them directly.

The data loader is activated by pressing Load Design pushbutton and based on the selected design from the

design selection pop-up-menu and operating frequency, it checks if desired design has been saved and if it is,

the loader reads the file and loads the design parameters into the GUI. If desired design has not been optimized

on selected switching frequency, it pops-up an error message notifying the user about the problem.

Figure 19. Structure of the CAD tool program.

The main function, PowerSwipeOptimization_v2.m, is activated by pressing RUN pushbutton and, in the

case that the tools parameters have been selected correctly, the tool reeds the specifications, sets-up the status

flags and runs selected optimizations and/or analysis, using functions presented in Fig. 19. If the optimizations

were selected, upon finishing, the tool writes the results in its corresponding excel files. Note that the different

results of the optimization of the same topology (e.g. Single Buck CMC with VMC) may exists since the name

of the file depends on the operating frequency, thus if several optimizations have been run on a different

frequencies, there were be several different result files. In the case that a optimization has been run and the file

already has existed, the tool will overwrite the existing file.

PSAnalisis_TwoBuckPMC_Coupled_v2

PSAnalisis_TwoBuckPMC_v2(‘DCM’)

PSAnalisis_TwoBuckPMC_v2(‘CCM’)

PSAnalisis_SingleBuckPCMC_v2(‘DCM’)

PSAnalisis_SingleBuckPCMC_v2(‘CCM’)

PSAnalisis_SingleBuckVMC_v2(‘DCM’)

PSAnalisis_SingleBuckVMC_v2(‘CCM’)

PowerSwipeOptimization_v2.m

results_TwoBuckPMC_Coupled_**MHz.xls

results_TwoPhBuckPCMC_DCM_**MHz.xls

results_TwoPhBuckPCMC_CCM_**MHz.xls

results_SingleBuckPCMC_DCM_**MHz.xls

results_SingleBuckPCMC_CCM_**MHz.xls

results_SingleBuckVMC_DCM_**MHz.xls

results_SingleBuckVMC_CCM_**MHz.xls

results.xls

PSOpt_TwoBuckPMC_Coupled_v2

PSOpt_TwoBuckPMC_v2(‘DCM’)

PSOpt_TwoBuckPMC_v2(‘CCM’)

PSOpt_SingleBuckPMC_v2(‘DCM’)

PSOpt_SingleBuckPMC_v2(‘CCM’)

PSOpt_SingleBuckVMC_v2(‘DCM’)

PSOpt_SingleBuckVMC_v2(‘CCM’)

load_data.m PowerSwipeGUI.m

PowerSwipeGUI.figData flow

Control flow

Main functions

Optimization functions

Analysis functions

Results



page 16 of 72

The CAD tool in total has 32 functions excluding PowerSwipeGUI.fig and PowerSwipeGUI.m which are

generated by Matlab toolbox. The functions are exchanging data via input variables of the functions and using

global variables which are presented in APPENDIX I. The functions used by the tool can be divided in six

groups:

1. Main functions (2),

2. Optimization functions (4),

3. Analysis functions (4),

4. Simulation and presentation functions (11) and

5. Modeling functions (12).

3.2.1. Main Functions

function PowerSwipeOptimization_v2(handles)

Description: the main function is used to manage the CAD tool. As mentioned, based on selected options form

the GUI, it runs either optimization or analysis functions and it saves results of optimizations in

corresponding excel files.

Inputs: handles (type: struc, description: it contains the handles (pointers) to the objects of the GUI)

Outputs: -

function load_data(handles)

Description: Data loading function is one of two essential functions and, as mentioned, it loads the results of

optimizations into the GUI if the optimization has been performed for a selected topology, control and

mode of operation at given switching frequency.


Outputs: -

3.2.2. Optimization Functions

function sol=PSOpt_SingleBuckVMC_v2(type)

Description: the function performs optimization of a Single-Phase Buck converter with VMC and the type of

operation (CCM or DCM) is defined with input variable.

Inputs: type (type: string, description: defines a type of operation with available options ‘CMC’ and ‘DMC’)

Outputs: sol (type: struc, description: contains information about optimal design. The fields are given in

APPENDIX I)

function sol=PSOpt_SingleBuckPMC_v2(type)

Description: the function performs optimization of a Single-Phase Buck converter with PCMC and the type of




APPENDIX I)function sol=PSOpt_TwoBuckPMC_v2(type)

function sol=PSOpt_TwoBuckPMC_ v2

Description: the function performs optimization of Two-Phase Buck converter with PCMC and the type of




APPENDIX I)

function sol=PSOpt_TwoBuckPMC_Coupled_v2

Description: the function performs optimization of Coupled Two-Phase Buck converter with PCMC in CCM.

Inputs: -



page 17 of 72


APPENDIX I)

3.2.3. Analysis Functions

function PSAnalisis_SingleBuckVMC_v2(type, handles)

Description: the function performs analysis of a Single-Phase Buck converter with VMC and the type of



handles (type: struc, description: it contains the handles (pointers) to the objects of the GUI)

Outputs: -

function PSAnalisis_SingleBuckPMC_v2(type, handles)

Description: the function performs analysis of a Single-Phase Buck converter with PCMC and the type of




Outputs: -

function PSAnalisis_TwoBuckPMC_v2(type, handles)

Description: the function performs analysis of a Two-Phase Buck converter with PCMC and the type of




Outputs: -

function PSAnalisis_TwoBuckPMC_Coupled_v2 (handles)

Description: the function performs analysis of a Coupled Two-Phase Buck converter with PCMC operating in

CCM.


Outputs: -

3.2.4. Simulation and Presentation Functions

function h=draw_pie(Losses, eta)

Description: the function draws a Pie-plot presenting the breakdown of the losses

Inputs: Losses (type: double vector, description: contains losses of the converter in [W])

eta (type: double, description: efficiency of the system)

Outputs: h (type: handle, description: handle at the figure (plot))

function [D, Xk]=GetSteadyState_OpenLoop(system,Topology,mode,Iout)

Description: the function calculates steady-state opetaing point

Inputs: system (type: struc, description: contains model of a converter, details in APPENDIX I)

Topology (type: string, description: selects the topology using 'SingleBuck', '2PhBuck' or

'2PhBuck_Coupled')

mode (type: string, description: defines a type of operation with available options ‘CMC’ and ‘DMC’)

Iout (type: double, description: output current)

Outputs: D (type: double vector, description: contains normalized time instance when commutations occur)

Xk (type: double matrix, description: contains values of the state variables for each commutation.

Columns represent the state vectors)

function [X0, Xh, Xrms]=harmonic(t, x, N)



page 18 of 72

Description: the function calculates the mean value, effective value and N harmonics defined with periodic

signal x and one normalized period t

Inputs: t (type: double vector, description: defines a normalized period)

x (type: double vector, description: analyzed signal)

N (type: double, description: number of harmonics)

Outputs: X0 (type: double, description: mean value of the signal x)

Xh (type: double vector, description: amplitudes of first N harmonics starting with fundamental)

Xrms (type: double, description: effective value of the signal x)

function Input_Capacitor_initial_design

Description: the function, based on the global parameters, calculate initial minimal and maximal value of the

input capacitor.

Inputs: -

Outputs: -

function Output_Capacitor_initial_design

Description: the function, based on the global parameters, calculate initial minimal and maximal value of the

output capacitor.

Inputs: -

Outputs: -

function ripple=PlotSteadyState_OpenLoop(system,Topology,mode,Iout,Nperiod)

Description: the function plots Nperiod periods of the system variables waveforms in an operating point defined

with Iout. The system is defined with variables system and Topology

Inputs: system (type: struc, description: contains model of a converter, details in APPENDIX I)

Topology (type: string, description: selects the topology using 'SingleBuck', '2PhBuck' or

'2PhBuck_Coupled')

mode (type: string, description: defines a type of operation with available options ‘CMC’ and ‘DMC’)

Iout (type: double, description: output current in [A])

Nperiod (type: double, description: number of periods)

Outputs:

function [Losses,Pout,eta]=SinglePhase_dcdc_loss_calc_burst(wn,wp,Iout,Vout_pp)

Description: The function calculates the efficiency and the losses of a Single-Phase Buck converter in BURST

mode of operation

Inputs: wn (type: double, description: width of the NMOS in [m])

wp (type: double, description: width of the PMOS in [m])

Iout (type: double, description: load current in [A])

Vout_pp (type: double, description: Peak-to-peak value of the output voltage for the burst operation in

[V])

Outputs: Losses (type: double vector, contains losses of the converter in [W])

Pout (type: double, description: output power of the system at Iout in [W])


function [Losses,Pout,eta]=SinglePhase_dcdc_loss_calc_v2(wn,wp,Iout,type)

Description: The function calculates the efficiency and the losses of a Single-Phase Buck converter in CCM or

DCM mode of operation




type (type: string, description: defines a type of operation with available options ‘CMC’ and ‘DMC’)






page 19 of 72

function [Losses,Pout,eta]=TwoPhase_dcdc_loss_calc_burst(wn,wp,Iout,Vout_pp)

Description: The function calculates the efficiency and the losses of a Two-Phase Buck converter in BURST

mode of operation




Vout_pp (type: double, description: Peak-to-peak value of the output voltage for the burst operation in

[V])




function [Losses,Pout,eta]=TwoPhase_dcdc_loss_calc_v2(wn,wp,Iout,type)

Description: The function calculates the efficiency and the losses of a Two-Phase Buck converter in CCM or

DCM mode of operation




type (type: string, description: defines a type of operation with available options ‘CMC’ and ‘DMC’)




function [Losses,Pout,eta]=TwoPhaseCoupled_dcdc_loss_calc_v2(wn,wp,Iout)

Description: The function calculates the efficiency and the losses of a Coupled Two-Phase Buck converter in

CCM mode of operation







3.2.5. Modeling Functions

function Y=calc_bodyD_Vd(w,Ids)

Description: the function calculates NMOS body-diode voltage drop depending of the channel width and the

instantaneous current Ids

Inputs: w (type: double, description: width of the NMOS in [m])

Ids (type: double, description: MOSFET current in [A])

Outputs: Y (type: double, description: body-diode voltage drop in [V])

function Y=calc_Qg_N(Vgs,w,Ids)

Description: the function calculates the charge injected in Gate terminal of a NMOS with channel width w

during the turn-on transient with driving voltage Vgs and the current Ids

Inputs: Vgs (type: double, description: driving voltage of the NMOS in [V])

w (type: double, description: width of the NMOS in [m])


Outputs: Y (type: double, description: gate charge in [C])

function Y=calc_Qg_P(Vgs,w,Ids)

Description: the function calculates the charge injected in Gate terminal of a PMOS with channel width w

during the turn-on transient with driving voltage Vgs and the current Ids




page 20 of 72

w (type: double, description: width of the PMOS in [m])


Outputs: Y (type: double, description: gate charge in [C])

function Y=calc_Rev_rec(w,Ids)

Description: the function calculates reverse recovery energy lost on NMOS body diode during the turn-on

transient of the PMOS.



Outputs: Y (type: double, description: reverse recovery energy in [J])

function Y=calc_Ron_N(Vgs,w,Ids)

Description: the function calculate static on-resistance of NMOS with width of the channel w, driving voltage of

Vgs with the current Ids


w (type: double, description: width of the NMOS in [m])


Outputs: Y (type: double, description: on-resistance in [Ohm])

function Y=calc_Ron_P(Vgs,w,Ids)

Description: the function calculate static on-resistance of PMOS with width of the channel w, driving voltage of

Vgs with the current Ids

Inputs: Vgs (type: double, description: driving voltage of the PMOS in [V])

w (type: double, description: width of the PMOS in [m])


Outputs: Y (type: double, description: on-resistance in [Ohm])

function Y=calc_TurnOff_P(w,Ids)

Description: the function calculates energy lost in PMOS with the width of the channel w during the turn-off

transient with MOSFET current Ids

Inputs: w (type: double, description: width of the PMOS in [m])


Outputs: Y (type: double, description: turn-off energy in [J])

function Y=calc_TurnOn_N(w,Ids)

Description: the function calculates energy lost in NMOS with the width of the channel w during the turn-on




Outputs: Y (type: double, description: turn-on energy in [J])

function Y=calc_TurnOn_P(w,Ids)

Description: the function calculates energy lost in PMOS with the width of the channel w during the turn-on


Inputs: w (type: double, description: width of the PMOS in [m])


Outputs: Y (type: double, description: turn-on energy in [J])

function [Cout, C_ESR, C_ESL, N12n,N3n9,N1n6]=CapDesign(C)

Description: the function designs the capacitor with desired capacitance C using basic cells of 12 nF, 3.9 nF and

1.6 nF

Inputs: C (type: double, description: desired capacitance in [C])



page 21 of 72

Outputs: Cout (type: double, description: obtained equivalent capacitance in [F])

C_ESR (type: double, description: equivalent series resistance in [Ohm])

C_ESL (type: double, description: equivalent series inductance in [H])

N12n (type: double, description: number of 12nF cells)

N3n9 (type: double, description: number of 3.9nF cells)

N1n6 (type: double, description: number of 1.6nF cells)

function system=GetSystem(Topology)

Description: the function defines a state-space model of a converter system using global variables (APPENDIX

I) and variable topology

Inputs: Topology (type: string, description: selects the topology using 'SingleBuck', '2PhBuck' or

'2PhBuck_Coupled')

Outputs: system (type: struc, description: contains model of a converter, details in APPENDIX I)

function components = function_regulator_design(reg_type, R1, fc, Gain_system, angGwc, FM)

Description: the function designs the regulator of the system

Inputs: reg_type (type: double, description: selects the type of the regulator to be design. Available options are

1, 2, 2.5 and 3)

R1 (type: double, description: input resistance of the regulator)

fc (type: double, description: desired bandwidth of the closed-loop gain)

Gain_system (type: double, description: gain of the system at bandwidth frequency)

angGwc (type: double, description: phase of the system at bandwidth frequency)

FM (type: double, description: desired phase margin of the closed-loop gain)

Outputs: components (type: double vector, description: contains the values of the components needed to

implement designed regulator)



page 22 of 72

3.3. Models

In this chapter component and converter models are presented. The component models are provided by

manufactures of the components or derived based on the simulations provided by the manufactures and they are

used for the estimation of the power losses. On the other hand, the models of the system are based on the

literature and can be divided as the switching model, implemented as a hybrid state-space model [24], and

average model, implemented as a liner state-space model based on [24] for VMC and [25] for PCMC.

3.3.1. Magnetics model

The magnetic components are designed using Tyndall National Institute [22] technology. The components

are based on “Magnetics on Silicon” process which is used for fabrication of micro-inductor and micro-

transformer structures. The process is currently employed to fabricate ‘elongated spiral’ or ‘racetrack’ device

structures. The top view and the cross-section of the racetrack magnetic structure are shown in Fig. 20.

Figure 20. Top view and cross-section of the Magnetic structure (ILD- Inter layer dielectric, IMD- Inter metal dielectric).

The model of a basic inductor has been implemented in the CAD tool having in mind constrains of the

technology and, for this version of the tool, is has been implemented as a series impedance of an inductor and

frequency dependent resistance, as shown in Fig. 21a.

Figure 21. The models of magnetic: a) basic inductor (L – inductance, R’(f) – frequency dependant resistance), b) modified inductors for

Two-phase Buck converter (L – inductance, R’’(f) – frequency dependant resistances) and c) equivalent model of Coupled Two-Phase Buck

inductors (L – leakage inductance, LM – magnetsing inductance, R’’(f) – frequency dependant resistances).

The frequency dependent resistance R’(f) is composed of the DC component, RDC, which is dependent on

desired inductance L, and AC components which represent the skin effect in the metal strips. For each frequency

of interest, defined by the number of harmonic, the skin depth is calculated and based on DC resistance and the

thickness of the metal strip h, AC resistances are calculated. The DC component of resistance is calculated using

vOUT

L

L

1:1

LM

R’’(f)

vOUT

L

L

R’’(f)

R’(f) L

vOUT

R’’(f)

R’’(f)

a)

b)

c)



page 23 of 72

nH

mkLkRDC 1',' ,

while the AC components are calculated using

0

)(,)(2

,max)(R

DCDCACnf

nfnf

hRRnfR , (2)

where ρ is resistivity of metal, μR relative magnetic permeability and μ0 magnetic permeability of vacuum. Any

component of the AC resistance of cannot be smaller than the DC resistance, thus max function has been

implemented.

Further, the power losses of the inductor can be calculated using

Nharm

n

nACLmeanDCL

InfRIRP

1

22

2)( , (3)

where is mean value of the inductor current, Nharm is the number of harmonics of interest and is the

amplitude of nth

component of the Fourier series if the inductor current.

Furthermore, in Fig. 21b, two inductors for Two-Phase Buck converter have been presented. The difference

between the basic inductor and the two inductors is how the DC component is calculated. Since the available

area is the same for both topologies, the two inductors system has to store twice as much energy in the same

area, resulting the increment of the losses, which is modeled modifying the constant k’ in equation (1). The DC

resistance is calculated using

nH

mkLkRDC 2'',''

The AC resistance components and losses are calculated using the same equations as in the basic inductor

case. Finally, in Fig. 21c, a coupled inductor system has been presented. The difference with the other two

models is that the user is defining the leakage inductance and magnetizing inductance, and the resistance and

losses are calculated using (4) for DC resistance and (2) and (3) for AC resistances and Power Losses,

respectively.

3.3.2. Capacitor model

The capacitors used in LV-DCDC converter are designed using IPDiA [23] low voltage MOSAIC PICS3

capacitor technology presented in Fig. 22.

Figure 22. MOSAIC PICS3 capacitor.

Two capacitors models are developed for designing both input and output capacitors. The first model is spice

based model used for initial estimations and the second model is building block based model implemented in the

Optimization and Analysis Tool. The spice model, presented in Fig. 23a, describes the capacitor with both free

terminals, A and B, where the terminal A is top metal electrode and terminal B is n+ Si lower electrode, as noted

in Fig. 22. Due to the fact that terminal B is free, n+ Si lower electrode and n- Si substrate create parasitic

capacitor CBOT and parasitic diode D. on the other hand, metal top electrode creates parasitic capacitor with

e

SC S0



page 24 of 72

substrate CTOP. All the parameters have been characterized by the IPDiA and characteristics are presented in a

table IV.

TABLE IV. ELECTRICAL CHARACTERISTICS OF A MOSAIC PICS3 CAPACITOR

Ca

pa

cito

rs Parameters min typical max

Pits Capacitance [nF/mm2] 200 250 300

Planar capacitance [nF/mm2] 4 5.4 6.8

Metal M1 to metal M2 [pF/mm2] 76 80 84

Metal M1 to substrate [pF/mm2] 75 100 125

DIO

DE

Parameters

BV [V] 30

IS [A] 1.83e-16*perimeter + 2.9e-15 * surface

IBVL 2 * IS

M 0.3

CJ0 [pF/mm2] 10

EG [eV] 1.11

In the case when the terminal B is connected to the minimal voltage of the system and since the substrate is

connected to the same voltage, the parasitic diode D and bottom capacitor CBOT are short-circuited and they are

not figuring in the model of the capacitor. This is the case for Buck converter systems implementation since

both input and output capacitors are connected to the ground.

Figure 23. The Spice capacitor: a) model and b) Dependancy of ESR on Capacitance.

Furthermore, in Fig. 23b the dependence of equivalent series resistance ESR on desired capacitance is

presented. It can be seen that ESR·C product is not constant and that for bigger values of capacitance the product

increases. In other words, the zero of the capacitor, defined by the ERS and C goes down on the lower

frequencies thus influencing the converter dynamic behavior. Moreover, the losses of the capacitor do not

reduce linearly with increase of capacitance. Thus a second model, as already stated, has been developed based

on a basic capacitor blocks with low capacitance, presented in Fig. 24. Doing so, constant ESR·C product is

maintained, so the dominate zero is kept on higher frequencies and the losses reduce linearly with the

capacitance.

Figure 24. The capacitor: a) basic building block and b) Equivalent capacitor built using 12 nF (blue), 3.6 nF (red) and 1.6 nF (green) basic

building blocks.

a) b)

PICS3 - Std designy = 0.0003x-0.4266

R2 = 0.8047

0.01

0.1

1

10

1.00E-11 1.00E-10 1.00E-09 1.00E-08 1.00E-07 1.00E-06 1.00E-05

Capacitor (F)

ES

R (

Oh

m)CTOPCBOT

PICS C A terminal

D

RSUB

B terminal

N12n x 12 nF

12.6 nF

0.2 nF

274 mΩ

2 pH

N3n6 x 3.6 nF

3.64 nF

62 pF

860 mΩ

8 pH

N1n6 x 1.6 nF

1.6 nF

27 pF

1.85 Ω

18 pH

C

CP

R

L

a) b)



page 25 of 72

The impedance of the basic building block is

P

PP

P

PP

Cbb

CC

CCsRCCs

CC

CCsRCCLssCR

Z

1)(

1)(1 2

,

where C is nominal capacitance of the building block, R is equivalent series resistance, CP is parasitic parallel

capacitance and L is equivalent series inductance. Since for all three building blocks, 12 nF, 3.6 nF and 1.6 nF,

the nominal capacitance C is around 60 times bigger than parasitic capacitance CP, the expression (5) can be

simplified to

PP

PPCbb

sRCCCs

sRCCCLssCRZ

1)(

1)(1 2

.

Further, since the resonance L(C+CP) is on lower frequencies the influence of time constant RCP is not dominant

and since it is located around 3GHz for all three cells, the equation can be further simplified to

)(

)(1 2

P

PCbb

CCs

CCLssCRZ .

In order to generate desired capacitance COUT, the basic building blocks are put in parallel in that manner that

minimal number of cells is used. The equivalent capacitance, series resistance and inductance obtained are given

with

61

61

63

63

12

12

61

61

63

63

12

12

616161636363121212

| || |

| || |

n

n

n

n

n

n

n

n

n

n

n

n

nPnnnPnnnPnnEQ

N

L

N

L

N

LESL

N

R

N

R

N

RESR

CCNCCNCCNC

.

The CAD tool uses function CapDesign, defined in chapter 3.5 Modeling functions, to generate the

capacitor. The power losses of the capacitor are given with

2

CeffC IESRP , (9)

where ICeff is effective value of the capacitor current.

3.3.3. Semiconductor model

The semiconductors used in LV-DCDC converter are implemented using Infineon [21] 40 nm c40fla

MOSFET technology. The model consists of nine functions, three static characteristics and five dynamic

characteristics:

1. NMOS body diode voltage drop,

2. NMOS on-resistance,

3. PMOS on-resistance,

4. NMOS gate charge,

5. PMOS gate charge,

6. NMOS body diode reverse-recovery energy loss,

7. PMOS turn-off energy loss,

8. PMOS turn-on energy loss.

Most of the functions are defined with two input variables and they are based on a finite number of

measurements. In order to perform interpolation between those measurements a model has been derived

utilizing piece-wise linear plains providing continuity of the estimation.

In general, the obtained results can be defined as Y(x1[i], x2[j]), where Y is the measured value and x1[i] and

x2[j] represent input variables of the modeling function. Both of the input variables are series where i and j are

indexes of the corresponding series and they can have value from 1 to N+1 and 1 to M+1, respectively.



page 26 of 72

Therefore, in the rest of the report the series x1[i] and x2[j] will be noted as x1i and x2j, while Y(x1[i], x2[j]) will

be noted as Yi,j.

Figure 25. Basic modelling cell.

As mentioned, in order to interpolate the output plane, for each four values of the output, Y i,j, Yi+1,j, Yi,j+1 and

Yi+1,j+1, with theirs corresponding input coordinates, (x1i, x2j), (x1i+1, x2j), (x1i, x2j+1) and (x1i+1, x2j+1), firstly,

additional point YINT i,j has been added as presented in Fig. 25. The additional point value is defined with

4

1,11,,1,

,

jijijiji

jiINT

YYYYY ,

while its input coordinates (x1INT i, x2INT j) are

2

2

122

2

1111

jj

jINT

iiiINT

xxx

xxx

.

Using additional point YINT i,j the output plain has been interpolated using four linear plains defined by

intermediate and two extreme points, while the input plain has been equally divided in to its corresponding sub

domains. In other words, the input plains defined with

),(),,(),,(:

),(),,(),,(:

),(),,(),,(:

),(),,(),,(:

2121121,4

211211211,3

211211211,2

2121121,1

jINTiINTjijijiIN

jINTiINTjijijiIN

jINTiINTjijijiIN

jINTiINTjijijiIN

xxxxxxS

xxxxxxS

xxxxxxS

xxxxxxS

,

are related with theirs corresponding output planes

jiINTjijijiOUTjiIN

jiINTjijijiOUTjiIN

jiINTjijijiOUTjiIN

jiINTjijijiOUTjiIN

YYYSS

YYYSS

YYYSS

YYYSS

,,1,,4,4

,1,1,1,3,3

,1,1,1,2,2

,,1,,1,1

,,:

,,:

,,:

,,:

.

Furthermore, the plains have been related with input variables x1 and x2

x1

Yi,j+1

Yi+1,j+1

YINT i,j

Yi,j

x1i

x1i+1

x2j

x2j+1

x2

Yi+1,j

y(x1, x2)



page 27 of 72

jijijijiIN

jijijijiIN

jijijijiIN

jijijijiIN

cxbxaxxySxx

cxbxaxxySxx

cxbxaxxySxx

cxbxaxxySxx

,42,41,421,421

,32,31,321,321

,22,21,221,221

,12,11,121,121

,,

,,

,,

,,

,

where ax i,j, bx i,j and cx i,j (x=1, 2, 3, 4) are constants obtained solving systems

jiINTjbijINTjiiINTji

jijijjiiji

jijijjiiji

jiINTjijINTjiiINTji

jijijjiiji

jijijjiiji

jiINTjijINTjiiINTji

jijijjiiji

jijijjiiji

jiINTjijINTjiiINTji

jijijjiiji

jijijjiiji

Ycxbxa

Ycxbxa

Ycxbxa

Ycxbxa

Ycxbxa

Ycxbxa

Ycxbxa

Ycxbxa

Ycxbxa

Ycxbxa

Ycxbxa

Ycxbxa

,,42,41,4

,,42,41,4

1,,412,41,4

,,22,21,2

1,1,212,211,2

,1,22,211,2

,,32,31,3

1,,312,31,3

1,1,312,311,3

,,12,11,1

,1,12,111,1

,,12,11,1

In order to use the models, to calculate the output for input variables x1 and x2, a three step procedure needs

to be followed:

1. Determine series indexes i and j which satisfy

1222

1111

ij

ii

xxx

xxx

2. Determine the sub-domain in the input plain

]4,1[,, ,21 xSxx jiINx

3. Load corresponding coefficients ax i,j, bx i,j and cx i,j from a look-up table and calculate the output

using (14)

Using the developed model all the functions are developed.

NMOS body diode voltage drop

NMOS body diode voltage drop is static characteristic of a low side switch and it is used for estimation of

the body diode conduction losses. The measurements are performed using circuit presented in Fig. 26. The input

variables are drain to source current IDS, which is equal to the load current, and the width of a MOSFET. The

simulations have been performed in a range of the load current ILoad from 0 mA to 800 mA and the width of the

MOSFET w from 2000 μm up to 12000 μm. The MOSFET length is 560 nm. The ranges of the width and the

current are also defining the range of the input variables where the model is valid.

Figure 26. Measuring of body diode voltage drop.

The estimation has been implemented in a modeling function, presented in 3.2.5, calc_bodyD_Vd. In order

to calculate conduction losses, the CAD tool calculates minimal and maximal inductor current, I0 and I1. With

the currents, if both of them are positive, voltage drops, VT0 and VT1, are estimated using above mentioned

function. Assuming that the current is constant during the transients, the losses for both transients are estimated

using

SWNtoPDTTNtoP

SWPtoNDTTPtoN

ftVIP

ftVIP

00

11

,

VSS

DUT

RG

ILoad

VSS

VF



page 28 of 72

where PPtoN is power loss during the turn-off transient of PMOS and tDT PtoN is the length of the transient defined

in GUI, PNtoP is power loss during the turn-on transient of PMOS and tDT NtoP is its length and fSW is the

switching frequency.

PMOS and NMOS on-resistance

PMOS and NMOS on resistance is a static parameter used to estimate conduction losses of the MOSFETs

and to create both switching and averaged models of power converter. The input parameters are gate to source

voltage VGS (measured between 2,5 V and 5 V with the step 0.5 V), the width of the MOSFET w (measured

between 2000 μm and 12000 μm) and the drain to source current IDS (measured between 0 A and 800 mA). The

circuit for measuring the on resistance of the NMOS is presented in Fig. 27, while the circuit for measuring

PMOS is complementary to the one presented in the figure.

Figure 27. Measuring on-resistance of a NMOS.

Since there are three input variables in the model, the gate to source voltage VGS has been selected as a

discrete input variable (without interpolation option), thus for each of the measured voltages a model, as

presented above, has been derived.

The on resistance estimation for both PMOS and NMOS are implemented modeling functions, presented in

3.2.5, calc_Ron_P and calc_Ron_N. The models have been developed for a PMOS with the length of a channel

650 nm and for a NMOS with the length of a channel of 550 nm.

PMOS and NMOS gate charge

PMOS and NMOS gate charge represent the dynamic parameter and it is used to evaluate driving losses of

the converter. Similarly as in previous case of on resistance, the input variables are gate to source voltage VGS

(measured between 2,5 V and 5 V with the step 0.5 V), the width of the MOSFET w (measured between 2000

μm and 12000 μm) and the drain to source current IDS (measured between 0 A and 800 mA). Once again, since

there are three input variables, gate to source voltage VGS has been selected as a discrete input variable and for

each value an independent model has been derived. The circuit for measurement of PMOS gate charge is

presented in Fig. 28, while for the NMOS is complementary to the presented one.

Figure 28. Measuring a gate charge of a PMOS.

VGS

VSS

VDD

ILoad

DUT

DUT

VX

VDD

ILoad

IDRV

VSS



page 29 of 72

The charge is used to estimate driving voltage using the equation

SWGSnNGSnGNN

SWGSpPGSpGPP

fVIwVQP

fVIwVQP

),,(

),,(

1

0,

where VGSp is gate to source voltage of a PMOS, wP its width, I0 the minimal current of the inductor and QGP

represents the estimation function, implemented in the CAD tool as calc_Qg_P. On the other hand, VGSn is gate

to source voltage of a NMOS, wN its width, I1 the maximal current of the inductor and QGN represents the

estimation function, implemented in the CAD tool as calc_Qg_N. The fSW represents switching frequency. The

both functions are presented in chapter 3.2.5.

NMOS body diode reverse-recovery energy loss

NMOS body diode reverse-recovery energy loss represents dynamic parameter of the NMOS and it is used

to estimate reverse-recovery losses of a NMOS which exists in a system as a consequence of conduction of a

body-diode. The input variables are the width of the NMOS wN (measured between 2000 μm and 12000 μm)

and the drain to source current IDS (measured between 0 A and 800 mA). The model is derived for a NMOS

switching with 5 V drain to source voltage and the length of a channel of 560 nm.

The measuring circuit is presented in Fig. 29. The NMOS is turned off and, while the switch S is off, the

body diode is conducting the current ILoad. When the switch is turned on, the diode starts to turn off and recovery

of diodes depilation zone occurs. The inductor L is placed in the circuit to limit the derivate of the NMOS

current.

Figure 29. Measuring NMOS reverse-recovery energy loss.

The power loss due to the reverse-recovery is calculated using

SWNRRRR fIwEP ),( 0 ,

where wN is NMOS width, I0 the minimal current of the inductor, ERR represents the estimation function,

implemented in the CAD tool as calc_Rev_rec and presented in 3.2.5, and the fSW represents switching

frequency.

PMOS turn-off energy loss

PMOS turn-off energy loss represents dynamic parameter of the system and it is used to estimate turn-off

losses of the PMOS which occurs in a system due to the hard switch-off. The input variables are the width of the

PMOS wP (measured between 2000 μm and 12000 μm) and the drain to source current IDS (measured between 0

A and 800 mA). The model is derived for a PMOS switching with 5 V drain to source voltage and the length of

a channel of 650 nm.

VSS

DUT

RG

ILoad

VDD

S

L

VSS



page 30 of 72

Figure 30. Measuring PMOS turn-off energy loss.

The measuring circuit is presented in Fig. 30. The PMOS is turned on and it conducts the current ILoad. When

the driver starts to turn off the PMOS, the voltage across drain and source starts to increase due to the difference

between the load current and the MOSFET current, defined with its dimensions and gate to source voltage.

Since the MOSFET is still conducting while the voltage is increasing the losses are produced on the PMOS. The

current shuts down when the body-diode of the low-side switch starts to conduct.

The turn-off power loss is calculated using

SWPoffPturnoffPturn fIwEP ),( 1 ,

where wP is PMOS width, I1 the maximal current of the inductor, Eturn-offP represents the estimation function,

implemented in the CAD tool as calc_TurnOff_P and presented in 3.2.5, and the fSW represents switching

frequency.

PMOS turn-on energy loss

PMOS turn-on energy loss represents dynamic parameter of the system and it is used to estimate turn-on

losses of the PMOS which occurs in a system due to the hard switch-on. The input variables are the width of the

PMOS wP (measured between 2000 μm and 12000 μm) and the drain to source current IDS (measured between 0

A and 800 mA). The model is derived for a PMOS switching with 5 V drain to source voltage and the length of

a channel of 650 nm.

Figure 31. Measuring PMOS turn-on energy loss.

The measuring circuit is presented in Fig. 31. The PMOS is turned off and the body-diode of a low side

NMOS conducts the current ILoad. When the driver starts to turn on the PMOS, the voltage across drain and

source remains constant until the diode turns-off by reaching zero current. After, the voltage across drain and

source starts to reduce until the PMOS enters in fully on state. Since the MOSFET is conducting while the

voltage no changing, the losses are produced on the PMOS.

The turn-on power loss is calculated using

SWPonPturnonPturn fIwEP ),( 0 ,

DUT

VX

VDD

ILoad

VSS

IDRV

DUT

VX

VDD

ILoad

IDRV

VSS



page 31 of 72

where wP is PMOS width, I0 the minimal current of the inductor, Eturn-onP represents the estimation function,

implemented in the CAD tool as calc_TurnOn_P and presented in 3.2.5, and the fSW represents switching

frequency.

3.3.4. Converter models

Converter models, presented in this chapter, are used to evaluate losses of the three implemented topologies

and to simulate them both in time and frequency domains. The models can be divided in to switching models,

which are implemented as hybrid state-space systems, and averaged linear state-space models. The switching

models are used for time domain simulations both in open-loop and in closed loop. The averaged models are

developed based on the steady-state simulation of switching models and they are used to simulate the system in

a frequency domain and to design the regulator.

Open-loop: Switching models

As mentioned, the switching models are implemented as hybrid state space models using equation

EUCXY

UBXAXdt

dii ,

where X is the state vector of the system, Ai is the system matrix during the state i, U is the input vector, Bi is the

input matrix during the state i, Y is the output vector, C is the output matrix and E is the feedthrough matrix of

the system. The extended state vector model has been implemented in the tool, redefining the system to

EXTEXT

EXTEXTiEXTi

EXT

ii

EXTiEXT

XCY

XAXdt

d

ECCBA

AU

XX ,

00,

.

Using the equations (24), the solutions in the time domain can be easily calculated using

)()( 0

)( 0 tXetX EXT

ttA

EXTEXTi .

Figure 32. Single-Phase Buck Converter sub-circuits.

In order to create the models, all topologies have been solved for each state of operation. In Fig. 32, Single

Buck converter states are presented. The state “1” corresponds to the state when high side switch is on and the

low side is off or during DTs phase of the cycle. The state “0” corresponds to the state when the low side is on

and the high side is off or during the (1-D)Ts for CCM operation and DxTs for DCM operation. Finally, the

state “X” corresponds to the state when the both switches are off for DCM operation or (1-D-Dx)Ts phase of the

cycle. The components used for building the sub-circuits in Fig. 32 represent equivalent components of the

system, defined with

parCC

parCC

parLOUT

parLDCLNMOS

parLDCLPMOS

RESRR

LESLL

LLL

RRRR

RRRR

0

1

,

L

COUT

vC

-

iC

iL

+

-vOUT

R1

RC

LC

RLOAD

+

VIN

+

IOUT

L

COUT

vC

-

iC

iL

+

-vOUT

RC

LC

RLOAD

+

IOUT

L

COUT

vC

-

iC

iL

+

-vOUT

R0

RC

LC

RLOAD

+

IOUT

State “1" State “0" State “X"



page 32 of 72

where R1 is equivalent resistance during the DTs phase of the cycle and it is composed of PMOS on resistance

RPMOS, the inductor DC resistance RL DC and the inductor parasitic resistance RL par. R0 resistance represents

equivalent resistance during (1-D)Ts phase of the cycle and it is composed of NMOS on resistance RNMOS, the

inductor DC resistance RL DC and the inductor parasitic resistance RL par. The inductor L is equivalent inductor

composed of the output inductor LOUT and parasitic inductance LL par. LC is equivalent capacitor inductance

composed of equivalent series inductance ESL and parasitic capacitor inductance LC par. RC is equivalent

capacitor resistance and it is composed of equivalent series resistance ESR and parasitic capacitor resistance

RC par. Finally, COUT is the output capacitor, and RLOAD represent parallel load resistance which serves to

decouple capacitor current from inductor current iL and output current IOUT. The state, input and output vectors

are defined with

T

LOUT

T

OUTIN

T

CLC

ivy

IVu

iivx

.

Figure 33. Two-Phase Buck Converter sub-circuits.

State “11" State “10" State “1X"

State “0X"

State “XX"State “X0"

State “01"

State “X1"

L

COUT

vC

-

iC

iL2

+

-vOUT

R1

RC

LC

RLOAD

+

VIN

+

IOUT

L iL1

L

COUT

vC

-

iC

iL2

+

-vOUT

R1

RC

LC

RLOAD

+

VIN

+

IOUT

L iL1R0

L

COUT

vC

-

iC

iL2

+

-vOUT

R1

RC

LC

RLOAD

+

VIN

+

IOUT

L iL1R1

L

COUT

vC

-

iC

iL2

+

-vOUT

RC

LC

RLOAD

+

VIN

+

IOUT

L iL1R1

L

COUT

vC

-

iC

iL2

+

-vOUT

RC

LC

RLOAD

+

IOUT

L iL1

L

COUT

vC

-

iC

iL2

+

-vOUT

R0

RC

LC

RLOAD

+

IOUT

L iL1

L

COUT

vC

-

iC

iL2

+

-vOUT

R0

RC

LC

RLOAD

+

IOUT

L iL1

L

COUT

vC

-

iC

iL2

+

-vOUT

R0

RC

LC

RLOAD

+

IOUT

L iL1R0

State “00"

L

COUT

vC

-

iC

iL2

+

-vOUT

R0

RC

LC

RLOAD

+

VIN

+

IOUT

L iL1R1



page 33 of 72

Figure 34. Coupled Two-Phase Buck Converter sub-circuits.

Furthermore, the extended state vector of the system is

T

OUTINCLCEXT IViivx .

The state matrixes Ai, as well as the input Bi, output C and feedthrough matrixes are presented in

APPENDIX II. Depending on the mode of operation, the system goes from state “1” to state “0” and back to

state “1” for CCM mode of operation, while for DCM the system goes from state “1” through state “0” to state

“X” if the condition that the inductor current reaches zero is met, and then. At the end of cycle, the system

returns back to state “1”.

Fig. 33 presents the sub-circuits of Two-Phase Buck converter. Components used in the modeling of the

states are defined with (26). Since the system can operate in DCM mode, the system has nine sub-circuits which

represent all combinations of the possible states for both phases. The system state, input and output vectors are

defined with

T

LLOUT

T

OUTIN

T

CLLC

iivy

IVu

iiivx

21

21

,

while extended state vector is defined with

T

OUTINCLLCEXT IViiivx 21 .

The system, while it operates in CCM and depending is duty cycle D bigger or smaller than 0.5, goes from

state “10” to state “00”, then to state “01” at half of the cycle and finish the cycle with “00” for the duty cycles

smaller than 0.5, or the system starts in state “11”, then goes to state “10”, returns back to state “11” at half of

the cycle and finish the cycle in state “01”. In DCM operation, the system can start from states “11”, “10” or

“1X” and depending on the duty cycle and when the currents reaches zero it can have various combinations with

constrain that each phase can change its state with pattern “1” to “0” to “X”.

Fig. 34 presents the sub-circuits of Couple Two-Phase Buck converter. As in previous cases, the components

used in the modeling of the states are defined with (26). Since the system cannot operate in DCM mode, the

system has four sub-circuits which represent all combinations of the possible states for both phases. The system

state, input and output vectors are defined with

State “11" State “10"

State “01" State “00"

L

COUT

vC

-

iC

iL2

+

-vOUT

R0

RC

LC

RLOAD

+

IOUT

L iL1R0iLm LM

L

COUT

vC

-

iC

iL2

+

-vOUT

R0

RC

LC

RLOAD

+

VIN

+

IOUT

L iL1R1iLm LM

L

COUT

vC

-

iC

iL2

+

-vOUT

R1

RC

LC

RLOAD

+

VIN

+

IOUT

L iL1R1iLm LM

L

COUT

vC

-

iC

iL2

+

-vOUT

R1

RC

LC

RLOAD

+

VIN

+

IOUT

L iL1R0iLm LM



page 34 of 72

T

LmLLOUT

T

OUTIN

T

CLLmC

iiivy

IVu

iiivx

21

2

,

while extended state vector is defined with

T

OUTINCLLmCEXT IViiivx 2 .

For both Two-Phase Buck and Coupled Two-Phase Buck converters the system, input, output and

feedthrough matrixes are presented in APPENDIX II. In order to prevent sub harmonics oscillations, external

ramp has been added in all PCMC systems. The ramp Peak-to-Peak amplitude, in the case of Single-Phase and

Two-Phase Buck is calculated using

9.0,53.0),05.0(maxmin

2

12PP ramp

DD

Lfsw

VDV

critical

INcritical

,

where VIN is input voltage, L is output inductance, fSW is switching frequency, Dcritical is critical duty cycle and D

is steady state duty cycle. In order to calculate critical duty cycle a margin of 5% is added to an actual duty cycle

thus avoiding problem due the tolerances. Additionally, the critical duty cycle has been limited between 53%,

avoiding negative slope of the ramp, and to 90%. In the case of Coupled Two-Phase Buck, the compensating

ramps are calculated using

PPmax rampPPmin ramp12

PP ramp ,,6.0maxmin VVf

mmV

SW

,

where m1 and m2 are positive and negative slopes of leakage inductor current, respectively, while Vramp PPmax and

Vramp PPmin are maximal and minimal amplitudes of the ramp voltage, set by CAD tool.

Open-loop: Linear models

In order to simulate the systems in frequency domain, as well to design regulator and calculate minimal

capacitances which can be employed in the system, linear averaged models have been developed of the systems

in CCM operation mode, presented in Fig. 35.

Figure 35. Linear averaged models of converters: a) Single Phase VMC Buck, b) Single Phase and Two-Phase PCMC Buck and c) Coupled

Two Phase PCMC Buck.

The linear model presented in Fig. 35a is open-loop model of a Single-Phase VMC Buck converter operating

in CCM. According to [24], the small-signal state-space model of the system is

L

COUT

vC

-

iC

iL

+

-vOUT

RAV

RC

LC

RLOAD

+

iOUT

+

+

Kd

˄d

˄KvinvIN

˄

˄

˄

˄˄

LAV

CevC

-

iC

iL

+

-

vOUT

RAV

RCRLOAD

+

iOUT

˄vIref

˄KvinvIN

˄

˄

˄

˄

˄

Re

a)

b)

c)

KIref

vC

-

iC

iL

+

- vOUT

RC

+

iOUT

˄

˄

˄

˄

˄˄vIref2

COUT

COUT



page 35 of 72

dUEEXCCuExCy

dUBBXAAuBxAxdt

d

OLuOL

OLuOL

ˆˆˆˆ

ˆˆˆˆ

0101

0101,

where x is small-signal state vector, u small-signal input vector, y small-signal output vector, d small-signal

control variable D and matrixes AOL, BOLu, COL and EOLu are averaged state, input, output and feedthrough

matrixes, respectively, defined with

01

01

01

01

)1(

)1(

)1(

)1(

EDDEE

CDDCC

BDDBB

ADDAA

OLu

OL

OLu

OL

.

Furthermore, X and U are DC steady-state state and input vector. Since d is an input variable of the open-loop

system and introducing

UEEXCCE

UBBXAAB

OLd

OLd

0101

0101,

the system can be redefined as

OLOLOL

OLOLOL

uExCy

uBxAxdt

d

ˆˆˆ

ˆˆˆ,

where

OLdOLuOL

OLdOLuOL

T

OL

EEE

BBB

duu ˆˆˆ

.

With (37) and (38) the open-loop averaged linear Single-Phase VMC Buck is defined.

In Fig. 35b linear averaged model of Single-Phase and Two-Phase PCMC Buck has been presented based on

[25]. The component values used to build the model are presented in Table V. The inductor LAV represents

equivalent inductor of the system and, for the Single-Phase Buck it is equal to total equivalent inductance L,

while for the Two-Phase Buck is equal to half of the total eq. inductance. Resistance RAV is averaged series

resistance of the Buck. Capacitor Ce creates the resonance at half of the switching frequency fSW with LAV and it

models the PCMC modulation. The resistance Re determines the dumping at half of the switching frequency and

it depends on positive and negative slope of the inductor current, m1 and m2, and on the slope of compensating

ramp mC. Gains KIref and Kvin are representing the influence of the inductor current reference voltage vIref and

input voltage vIN.

TABLE V. COMPONENTS OF THE PCMC CONVERTER MODEL

Single-Phase Buck Two-Phase Buck

LAV L 2

L

RAV 01 )1( RDDR 2

)1( 01 RDDR

Ce LfSW

22

1

LfSW

22

2

Re

2

1

21

1

mm

mm

Lf

C

SW

1221

1

mm

mm

Lf

C

SW

KIref 1 2



page 36 of 72

Kvin Lf

DRD

SW

e

2

)1(1

Lf

DRD

SW

e

2

)1(12

The system, input and output vectors are defined with

T

LOUTOL

T

IrefOUTINOL

T

CeLCOL

ivy

vivu

vivx

ˆˆˆ

ˆˆˆˆ

ˆˆˆˆ

,

while the state, input, output and feedthrough matrixes are

000

00

0

0)(

0

0)(

0

010

0

110

1

)(

0)()(

1

LOADC

LOADC

OL

e

Iref

ee

IN

AVLOADC

LOADC

OUTLOADC

LOAD

OL

LOADC

LOADC

LOADC

LOAD

OL

eee

AVAV

LOADC

LOADCAV

AVLOADC

LOAD

OUTLOADC

LOAD

OUTLOADC

OL

RR

RR

E

C

K

RC

K

LRR

RR

CRR

R

B

RR

RR

RR

R

C

RCC

LL

RR

RRR

LRR

R

CRR

R

CRR

A

.

Finally, in Fig. 35c the first order model of a Coupled Two-Phase Buck has been presented. The model is

used only for minimal capacitor calculations. For designing a switching closed-loop model of the system, a

simulation with a small perturbation in inductor current reference vIref on an open-loop switching model of the

system is run. The perturbation has a frequency of desired bandwidth of the system. Further, the amplitude and

the phase of the output voltage deviation are calculated and the regulator is designed.

The model in Fig. 35c is used, as mentioned, only for minimal capacitor calculation. The transfer function of

the system is defined as

OUT

OUTCOL

OUTvoutvirefsC

CsRZG

12 ,

which is used to design regulator R and the close-loop gain L. further, the closed-loop output impedance CL

OUTZ

is calculated with

L

ZZ

OL

OUTCL

OUT1

,

which is further used to estimate the response of the system under the load steps.

Regulator models

Closed-loop systems have been designed using regulators presented in Fig. 36. In Fig. 36a regulator type II

is presented which is used to design the loop of current mode controlled converters since it is compensating the

phase margin up to 90 degrees. On the other hand, the regulator type III is presented in Fig. 36b and it is used

for Single-Phase VMC Buck, since the regulator can compensate up to 180 degrees of the phase margin.



page 37 of 72

Figure 36. Regulator: type II and b) type III.

TABLE VI. REGULATOR MODEL

Type II Type III

xREG T

PCSC vv 22 T

PCSCSC vvv 221

uREG errv errv

yREG ctrv ctrv

AREG

PSPS

SSSS

CRCR

CRCR

2222

2222

11

11

pSpSpS

SSSS

SS

CRCRCR

CRCR

CR

222221

2222

11

111

110

001

BREG PiPCR 2

10

PPS

PS

SS CRR

RR

CR 211

11

11

01

CREG 10 100

Assuming that ideal Operational amplifiers are used, egulators model are presented in Table VI. TABLE VI.

The feedthrough matrix E, in both cases, is zero matrix. The input variable verr represents an error signal

between the output voltage vOUT and the reference voltage VREF and it is defined as

REFOUTerr Vvv .

When a linear averaged model of a power stage is obtained, the CAD tool calculates amplitude and phase of

control to output gain. Afterwards, using the function function_regulator_design, regulator is designed and the

switching and linear closed-loop models of the converters can be implemented combining open-loop models and

regulator models.

Closed loop: Switching models

Closed-loop switching models of power converters are develop only for CCM operation mode and they are

defined with hybrid state-space model and a switching surface which is defining the time instance when the

system changes its state. The model is used for time simulations under dynamic tests. In general, for all three

cases, close-loop state, input and output vectors are defined with

REG

OL

CL

Iref

OL

CL

REG

OL

CL

y

yy

V

uu

x

xx

,

where xCL, uCL and yCL are closed-loop state, input and output vectors, xOL, uOL and yOL are open-loop state, input

and output vectors and xREG and yREG are regulator state and output vectors. Corresponding closed-loop state,

input, output and feedthrough matrixes (ACLi, BCLi, CCLi and ECLi) for each state i are obtained combining its

corresponding open-loop state, input, output and feedthrough matrixes (Ai, Bi, Ci and Ei), defined in APPENDIX

II, with regulator matrixes (AREG, BREG and CREG), obtaining

R1P =1 kΩ +

-verr

vctr

R1S C1S R2S C2S

C2P

0

R1P =1 kΩ +

-verr

vctr

R2S C2S

C2P

0

a) b)



page 38 of 72

0,...),(

00

0

0

0

00

CLCL

REF

OLi

REG

OL

REG

i

CL

REF

OL

REGiREG

i

REG

OL

REGiREG

i

REG

OL

ux

V

uE

x

x

C

Cy

V

u

BEB

B

x

x

ACB

A

x

x

dt

d

,

or in short

,...),( CLCL

CLCLiCLCLiCL

CLCLiCLCLiCL

uxf

uExCy

uBxAxdt

d

,

where ACLi is the closed-loop state matrix during the state i, BCLi is the closed-loop input matrix during the state

i, CCLi is the closed-loop output matrix during the state i and ECLi is the closed-loop feedthrough matrix during

the state i. According to (21), extended state vector state-space model are derived and used for calculations.

The function σ is switching surface and it determines when the state is changed and it is different for each

type of modulation:

1. Single-Phase VMC Buck

For a Single-Phase VMC Buck converter, the switching surface is defied using control signal vd, which is

an output of the regulator, and the ramp signal ramp, which is synchronous with the set event of the duty

cycle and it has an amplitude of 1. The surface is defined with

0),mod()(: SWd fttv .

When the condition (47) is satisfied the system changes its state form state “1” to state “0” and remains

in the later state until the new set event occurs.

2. Single-Phase PCMC Buck

For a Single-Phase PCMC Buck converter, the switching surface is defied using control signal vIref,

which is an output of the regulator, and the ramp signal ramp, which is synchronous with the set event of

the duty cycle and it has an amplitude of VrampPP and inductor current iL. The surface is defined with

0),mod()(: LSWrampPPIref iftVtv .

Again, when the condition (48) is satisfied the system changes its state form state “1” to state “0” and

remains in the later state until the new set event occurs.

3. Two-Phase PCMC Buck and Coupled Two-Phase PCMC Buck

In the case of Two-Phase PCMC Buck and Coupled Two-Phase PCMC Buck, since there are two phases,

the system is defined using two switching surfaces which are resetting their corresponding phases. The

set signals are phase shifted one to another by half of the period, thus corresponding ramps are shifted as

well and they are synchronous with its set signal. The surfaces are defined with

0),2mod()(:

0),mod()(:

22

11

LSWSWrampPPIref

LSWrampPPIref

ifTtVtv

iftVtv,

where σ1 is switching surface of the first phase, σ2 is switching surface of the second phase, vIref is

inductor current reference, VrampPP is the amplitude of the ramps, TSW is the switching period and fSW is the

switching frequency. Again, when the condition (49) is satisfied for one of the phases, that phase changes

it state from state “1” to state “0” and it remains in state “0” until its set signal arrives.

Closed loop: Linear models

Closed-loop linear models of power converters are developed to present frequency characteristics and they

are used in minimal capacitor calculations to estimate dynamic response of the system under dynamic tests. The

tests are performed in order to ensure that the capacitor used is satisfying both static and dynamic specifications.

The model of Coupled Two-Phase Buck converter has been already presented with equations (41) and (42). In



page 39 of 72

the case of the other topologies, the model is built combining open-loop averaged linear model of the power

stage and the model of the regulator. In order to define the closed-loop model, open-loop models needs to be

redefined since the input variable CNTv ( d in Single-Phase VMC Buck and Irefv in Single-Phase and Two-

Phase PCMC Buck) is now controlled variable and depends on the regulator state vector. On the other hand,

according to (43), the input of the regulator is dependent on the output voltage OUTv which is the one of the

variables of the output of the system. The open-loop input vector is re-defined in general as

OUT

IN

OL

CNT

OL

CNT

OUT

IN

OLi

vu

v

u

v

i

v

uˆ

ˆ'ˆ,

ˆ

'ˆ

ˆ

ˆ

ˆ

ˆ ,

where OLu'ˆ is a basic input vector. Due to the redefinition, the open-loop system is redefined as

CNT

OLvout

OLOLiL

OL

vout

OL

L

OUT

CNT

OLCNT

OLOLOLOLOL

v

uEx

C

C

i

v

v

uBBxAx

dt

d

ˆ

'ˆ

00

0ˆ

ˆ

ˆ

ˆ

'ˆ'ˆˆ

,

where OLB' is the open-loop basic input matrix related to the influence of the basic input vector OLu'ˆ on the state

vector, CNT

OLB is the input matrix representing the influence of CNTv on the state vector, vout

OLC is the open-loop

output matrix related to the influence of the basic state vector OLx on the output OUTv , iL

OLC is the open-loop

output matrix related to the influence of the basic state vector OLx on the output Li , vout

OLE is the feedthrough

matrix related to the influence of the basic input vector OLu'ˆ on the output OUTv . The rest of the components of

the open-loop feedthrough matrix are zero matrixes since the controlling signal CNTv does not have influence on

neither on OUTv , neither on Li , while

Li is dependent only on the state variables.

The small signal closed-loop state, input and output vectors are defined with

OLCL

Iref

OL

CL

REG

OL

CL

yy

v

uu

x

xx

ˆˆ

ˆ

ˆˆ

ˆ

ˆˆ

.

Corresponding closed-loop state, input, output and feedthrough matrixes (ACL, BCL, CCL and ECL) are

obtained combining its corresponding open-loop state, input, output and feedthrough matrixes (AOL, BOL, COL

and EOL), presented above, with regulator matrixes (AREG, BREG and CREG) , obtaining

Iref

OLvout

OL

REG

OL

iL

OL

vout

OL

L

OUT

Iref

OL

REG

vout

OLREG

OL

REG

OL

REG

vout

OLREG

REG

CNT

OLOL

REG

OL

v

uE

x

x

C

C

i

v

v

u

BEB

B

x

x

ACB

CBA

x

x

dt

d

ˆ

'ˆ

00

0

ˆ

ˆ

0

0

ˆ

ˆ

ˆ

'ˆ0'

ˆ

ˆ

ˆ

ˆ

,

or in short

CLCLCLCLCL

CLCLCLCLCL

uExCy

uBxAxdt

d

ˆˆˆ

ˆˆˆ.



page 40 of 72

3.4. Algorithms

3.4.1. Single-variable single-point search algorithm

Single-variable single-point search algorithm (SVSP) is generic algorithm used to find an input variable

value x for which a continuous monotone function f(x) has a reference value Y0. The function f(x) is known but

its inverse function is not, thus the numerical solving approach is used. The algorithm is used in various

functions of the CAD tool when interception of a function with a constant value or of two functions is searched

(e.g. to find a duty cycle D for steady-state operation, to find a time instance when the controlling signal is

intercepting a ramp in VMC control mode…).

Figure 37. Single-variable single-point search algorithm: a) graphical interpretation (minimal values array(blue) and maximal values array

(red)) and b) implementation diagram.

The graphical interpretation of the SVSP algorithm is presented in Fig. 37a, while its implementation is

presented in Fig. 37b. The algorithm starts by setting the control flag DOit to true and minimal and maximal

input value, xMIN and xMAX. The algorithm enters in a while-loop and it executes set of instructions until the

DOit-flag is not set to false. In the loop, the algorithm sets current input variable value x as an arithmetic means

of minimal and maximal values, xMIN and xMAX. Then the current output value Y and the output error ΔY are

calculated. If the output error is smaller than the output precision Yprec or the difference of the maximal and

minimal input values Δx is smaller than the input precision Xprec, the algorithm sets DOit flag to false and

finishes the execution. The output of the system is the last used variable x. in the case that neither condition is

met, the sign of the output error ΔY is tested. If the function f(x) has a positive gradient, as illustrated in Fig.

37a, and in the case that the output error ΔY is positive, the maximal input value xMAX is set to be current value

x, thus reducing the search domain by half. In the next iteration, a new current input variable is calculated once

again as an arithmetic means of minimal and maximal values, the current output value Y and the output error

ΔY are evaluated and the condition for finishing the search is tested. If the condition is not met, the sign of the

output error is tested and the domain is one again reduced by half. In the Fig. 37a, the second iteration illustrates

the case when the sign of the output error ΔY is negative, thus assigning the new minimal value xMIN to be the

current value x. Doing so, two arrays xMIN[i] and xMAX[i] are created which are converging one to another while

the searched value is always between them.

In the case that the function f(x) has negative derivative, the algorithm is modified to assign the current value

x to minimal value xMIN when the output error ΔY is positive and to maximal value xMAX when the output error

ΔY is negative, as illustrated in Fig. 37b where assignations of x to xMIN and xMAX are placed in brackets.

3.4.2. Steady-state operating point calculation

Steady-state operating point calculation algorithm, shown in Fig. 38, is used to calculate open-loop steady-

state and it is implemented in CAD tool function GetSteadyState_OpenLoop, presented in chapter 3.2.5. The

inputs of the function are the system, Topology, mode and IOUT. The variables system and Topology are defining

the switching model of the system and for which topology the model is developed, the variable mode defines is

a) b)

true

false

true

false

true

false

DOit=true

xMAX

xMIN

while (DOit)

x=0.5*(xMAX-xMIN)

Y=f(x)

ΔY=Y-Y0

|ΔY|<Yprec

or

|Δx|<Xprec

DOit=false

ΔY>0

xMAX=x

(xMIN=x)

xMIN=x

(xMAX=x)

START

END

i=0

xMIN

1

2

3

4

5

xMAX

y=f(x[i])

Δx

Y0Δy



page 41 of 72

the system operating in CCM or DCM mode and IOUT is defining the operating point together with input and the

reference voltage which are passed to the function as global variables. The outputs of the function are vector D

and matrix Xk, where D contains or the duty cycle DCCM, for CCM mode, or both duty cycles DDCM (the on-time

of the high-side switch) and DX (the on-time of the low-side switch). The matrix Xk contains all the state vectors

at all switching instances, where the columns are the vectors and the rows represent theirs time evolution.

Figure 38. Steady-state operating point calculation algorithm.

Steady-state operating point calculation algorithm contains three main branches for each of the implemented

topologies. After the case-switch structure, depending on the variable Topology, the execution is redirected to

one of the branches where the calculation of the CCM operation is performed using the SVSP algorithm. The

outputs of the algorithm are the duty cycle DCCM, the initial state vector Xk0 and the state of the state vector at

the switching instance DCCM·TSW, Xk1. If the CCM operation mode is selected, the algorithm prepares the

outputs and jumps to the end. In the case for Single-Phase and Two-Phase Buck, that DCM mode is selected, the

inductor current value, iL or iL1 (for Two-Phase Buck), at the beginning of the cycle is tested. If the current is

negative the condition for DCM is satisfied and the algorithm performs two nested SVSP algorithms, where in

the first the input is the on-time of the high-side switch DDCM and the output is the output voltage vOUT. The goal

of the search is that the initial and final output voltage values are the same and equal to the reference voltage

VREF. The second, nested SVSP algorithm is used to calculate the on-time of the low-side switch so that the

inductor current reaches zero value. The input is on-time of the low-side switch DX, the output is inductor

current iL and the target value is 0A. In the case of the Coupled Two-Phase Buck, only the CCM operation is

calculated since the DCM mode is not allowed for that topology

SVSP search: CCM

The calculation of the CCM operating point is based, as mentioned, on SVSP search algorithm where the

input variable is the duty cycle DCCM, the output is the output capacitor voltage vC and the target value is the

output voltage reference VREF. In order to complete the algorithm, it is necessary to define the function f(x). The

function is based on the assumption that the state vector at the end of the cycle X(TSW) is the same as at the

beginning of the cycle X(0) and on the solution of the extended state vector state-space system, given with (25).

If the system goes through N states, and in each state ],1[ Ni the system remains for ti, the relation between

the previous value of the state vector EXT

iX 1 and the new EXT

iX is

false

true

“SingleBuck”

“2PhBuck”

“2PhBuck_Coupled”

true

SVSP search: CCM

Input: DCCM

Output: VOUT

Reference: VREF

START

END

switch(topology)

SVSP search: CCM

Input: DCCM

Output: VOUT

Reference: VREF

SVSP search: CCM

Input: DCCM

Output: VOUT

Reference: VREF

iL(t=0)<0A & DCM iL1(t=0)<0A & DCM

SVSP search: DCM

Input: DDCM

Output: VOUT

Reference: VREF

SVSP search: iLoff

Input: DX

Output: iL

Reference: 0A

SVSP search: DCM

@ IOUT/2

Input: DDCM

Output: VOUT

Reference: VREF

SVSP search: iLoff

Input: DX

Output: iL

Reference: 0A

false



page 42 of 72

EXT

i

tAEXT

i XeX ii

1 ,

where Ai is extended state matrix of the system. Due to the (55), the relation between the final state vector EXT

NX

and initial EXTX 0is

112211

112211

...

... 00

tAtAtAtA

EXTEXTtAtAtAtAEXT

N

eeeeM

XMXeeeeX

NNNN

NNNN

,

where M is transition matrix and it is dependent on the states and the time intervals the system remains in

corresponding states. Furthermore, the system can be disaggregated to the basic state vector and input vector,

giving

U

X

I

MM

U

X BAN 0

0,

where XN and X0 are state vector at the end and beginning of the cycle, MA and MB are sub-matrixes of the

transition matrix M demonstrating the impact of initial state and input vector on the final state vector. From the

assumption that the system is in steady state, (57) transforms to

UMXMX BA 00 ,

from which the solution for initial vector is

IM

UMX

A

B0 .

Having the initial state vector, the output capacitor voltage, which is one of the state variables, can be

extracted.

In the case of the Single-Phase Buck, the transition matrix is easily obtained since the system starts in state

“1” and it remains there for DCCMTSW and then changes to state “0” and remains in it until the end of the cycle

for (1- DCCM)TSW, giving the transition matrix

SWCCMSWCCM TDATDA

CCM eeDM 10 1)( .

For the Two-Phase and Coupled Two-Phase, the transition matrix has two versions since, depending is DCCM

bigger or smaller than 0.5, the system changes its states differently. In the case of smaller DCCM, the system

starts in state “10” where remains for DCCMTSW, then changes to state “00” where it remains for (0.5-DCCM)TSW,

than at half of the cycle it enters in state “01” for DCCMTSW and finally enters in “00” for (0.5-DCCM)TSW, thus

finishing the cycle. The transition matrix M<0.5 is then defined as

SWCCMSWCCMSWCCMSWCCM TDATDATDATDA

CCM eeeeDM 10000100 5.05.0

5.0 )( .

In the case that the duty cycle DCCM is bigger than 0.5, the system starts in state “11” where remains for

(DCCM-0.5)TSW, then changes to state “10” where it remains for (1-DCCM)TSW, than at half of the cycle it enters

in state “11” for (DCCM-0.5)TSW and finally enters in “01” for (1-DCCM)TSW, thus finishing the cycle. The

transition matrix M<0.5 is then defined as

SWCCMSWCCMSWCCMSWCCM TDATDATDATDA

CCM eeeeDM5.015.01

5.011101101)( .

Defining all the transition matrixes for all three topologies, it is possible to calculate the output capacitor

voltage vC and perform SVSP search algorithm. The function defined with (59)-(61) has positive gradient. The

first step in the algorithm is to define the minimal and maximal input values of the duty cycle DCCM which are 0

and 1, respectively. The system enters in the while loop, shown in Fig. 37b, sets the current duty cycle,

calculates transition matrix and then the output capacitor voltage vC and then calculates the error value between

vC and the output voltage reference VREF. According to the diagram in Fig. 37, the tool will remain in the loop

until the error value is less than the precision, which is 1 μV, or until the difference between the maximal and

minimal duty cycle is less than its precision, which is 10-6

.

Upon obtaining initial state vector and the duty cycle, the output matrix Xk is prepared by calculating each

state vector in the moments of switching the states. In the case of Single-Phase Buck only one vector is

calculated at DCCMTSW using relation (55), thus the output matrix is



page 43 of 72

001, XeXXXXk SWCCMTDA

DD .

while the output D is equal only to DCCM.

In the case of Two-Phase and Coupled Two-Phase Buck, depending is DCCM bigger or smaller than 0.5, the

matrix is

5.0

5.0

1

5.0

1

5.0

0

5.0

5.0

5.05.0

5.0

5.0

0

15.05.005.05.00

11

10

11

01

00

10

5.05.0

XeX

XeX

XeX

XeX

XeX

XeX

XXXXXkXXXXXk

DD

SWCCM

SWCCM

SWCCM

SWCCM

SWCCM

SWCCM

TDA

D

D

TDA

TDA

D

TDA

D

D

TDA

TDA

D

DDDD

CCMCCM

.

SVSP search: DCM

In the case that input variable type is equal to DCM and that inductor currents iL or iL1 of initial state vector

X0, calculated in CCM part of the algorithm, are negative, the condition for DCM operation is achieved and the

algorithm calculates state vectors and on-cycles of the high-side switch (DDCM) and of the low-side switch (DX).

The DCM calculations are implemented only for Single-Phase and Two-Phase Buck converters, as presented in

Fig. 28.

Upon checking the condition for DCM operation, for Single-Phase Buck, the algorithm enters in the first

SVSP search where the input is on-cycle of the high-side switch DDCM, the output is the output capacitor voltage

vC and the target value is output reference voltage VREF. Before entering and setting the control flag to true, the

algorithm sets minimal and maximal high-side switch on-cycle to 0 and DCCM, respectively, and initial state

vector. The assumption is that the inductor current iL is equal to 0 (DCM operation), thus resulting that initial

capacitor current iC is equal to negative load current IOUT. Since the goal of the search is that capacitor voltage vC

is equal at the beginning and the end of the cycle to the reference voltage VREF, its value in the initial state vector

is set to be VREF, having

T

OUTREF

T

CLC IViivX 00 .

After entering the while loop the current value high-side switch on-cycle DDCM is calculated and, since the

cycle starts in state “1” and using extended state-space model, the state after the time DDCM TSW is calculated

EXTTDAEXT XeX SWDCMEXT

011 .

The next step in the algorithm is to calculate the low-side switch on-cycle DX for which the inductor current

iL reaches zero. The calculation is performed using the second SVSP search algorithm where the input is DX, the

minimal and maximal values are 0 and 1- DDCM, the output is iL, the target value is 0 and the function f(x) is

EXTTDAEXT XeX SWXEXT

120 .

The function has a negative gradient and the algorithm is repeated until the absolute value of inductor

current is less than the precision, which is 1 μA, or until the difference between the maximal and minimal high-

side on-cycle is less than its precision, which is 10-6

.

Upon obtaining DX and the state vector at the end of the state “0” EXTX 2 , the final state vector EXTX 3 is

obtained using

EXTTDDAEXT XeX SWXDCMEXTX

2

)1(

3 .

From the final state vector EXTX 3 , the value of the output capacitor voltage vC is obtained which is compared

with the reference voltage VREF in the first SVSP search algorithm for DDCM. Creating the error in this way, the

created function f(x) has positive gradient. The first SVSP search will repeat until the error between the output

capacitor voltage and the voltage reference is less than the precision, which is 1 μV, or until the difference

between the maximal and minimal high-side on-cycle is less than its precision, which is 10-6

.

After finishing the calculation of the high-side on-cycle the outputs are prepared



page 44 of 72

210 XXXXk

DDD XDCM.

In the case of a Two-Phase Buck converter, the same algorithm is applied with differences that the output

current is half of its value and that the second phase is inactive (it is in state “X” with zero current). In other

words, initial extended state vector EXTX 0, defined with (30) is

T

OUTIN

OUTREF

EXT IV

IVX

22000 ,

while the system is going through states “1X”, “0X” and “XX”. Doing so, the impact of the first phase is

obtained without considering the second phase, which can be excluded from initial analysis due to the

symmetry.

The next step is to calculate the state vector at the half of the switching frequency to obtain the value of the

inductor current IL10.5. The obtained value represents initial value of the second phase inductor current. Having

all the variables, initial extended state vector EXTX 0 can be defined as

T

OUTINOUTLLREFEXT IVIIIVx 5.015.010 .

Finally, having the high-side switch on-cycle DDCM, the low-side switch on-cycle DX and extended initial

state vector EXTX 0 , the steady state is defined. In order to prepare the outputs, calculations of the state vectors in

the switching instances are performed. Depending on DDCM and DX, there are four possible paths for the system

to change states. Possible paths are presented in Fig. 39.

Figure 39. Two-Phase Buck – DCM operation mode: a) DDCM<0.5 and DX<0.5-DDCM; b) DDCM<0.5 and DX<0.5; c) DDCM<0.5 and DX>0.5;

and d) DDCM>0.5.

The outputs of the algorithm are

EXT

t

EXT

t

EXTEXT

t

EXT

t

EXT

XDCM

XXXXXXXk

DDD

545.0210

,

where the extended state vector, defining the output matrix Xk, are calculated in the switching instances

according Fig. 39.

3.4.3. Steady-state Losses calculation

Steady-state losses calculations are used to estimate efficiency and to provide losses breakdown of an

analyzed system. The calculations are implemented in five functions presented in 3.2.5. The functions are

divided in to the CCM-DCM mode calculating functions and the Burst mode functions.

CCM-DCM mode calculating functions

CCM-DCM mode calculating functions algorithm is presented in Fig. 40. First step is to obtain the steady-

state operating point defined with the input parameters of the function using GetSteadyState_OpenLoop

function. Upon obtaining the output D and Xk, the CAD tool recreates in time domain all the currents of interest

for losses estimation, such as the inductor current iL for Single-Phase Buck or iL1 for Two-Phase and Coupled

Two phase Buck, the input and output capacitors current iCin and iCout and the MOSFETs currents iPMOS and iNMOS

1X 0X XX X1 X0 XX

iL1

t10 0.5t2 t4 t5 1

iL2

DX

DDCM

10 1X 0X 01 X1 X0

iL1

t10 0.5t2 t4 t5 1

iL2

DDCM

DX

10 00 0X 01 00 X0

iL1

t10 0.5t2 t4 t5 1

iL2

DDCM

DX

11 10 1X 11 01 X1

iL1

t10 0.5t2 t4 t5 1

iL2

DDCM

DX

a) b) c) d)



page 45 of 72

or Single-Phase Buck or iPMOS1 and iNMOS1 for Two-Phase and Coupled Two phase Buck. Furthermore, the

minimal and maximal values of the inductor current, I0 and I1, are obtained which are used for dynamic losses

estimations.

Figure 40. CCM-DCM mode calculating functions algorithm.

Using harmonic function and based on obtained waveforms, effective values of the currents (IL, ICin, ICout,

IPMOS, INMOS) are calculated as well the DC value of the inductor current ILDC for DC inductor loss and N

harmonics of the inductor current ILn for AC inductor losses. Based on the calculated values, passive losses for

Single-Phase Buck are calculated using

2

2

2

2

2

1

2

2

2)(

CoutparCoutparCout

CoutCoutESRCout

CinparCinparCin

CinCinESRCin

LLparLpar

Nharm

n

LnLACLAC

LDCLDCLDC

IRP

IESRP

IRP

IESRP

IRP

InfRP

IRP

,

where RLDC is DC inductor resistance calculated with (1), RLAC is AC resistances corresponding for each

harmonic and defined with (2), ESRCin and ESRCout are equivalent series resistance of the input and output

capacitors, defined with (8) and RLpar, RCin par and RCout par are parasitic resistances of the inductor and the input

and output capacitor, defined in the GUI of the CAD tool. The passive inductor losses for the Two-Phase and

Coupled Two phase Buck are doubled since there are two inductors, while the calculations are done using only

the inductor current of the first phase, while the capacitors losses are the same.

Following the passive losses calculations, the CAD tool estimates semiconductor losses using semiconductor

models presented in 3.3.3. Conduction losses are obtained using on-resistances RPMOS and RNMOS and effective

values of the MOSFETs currents, thus calculated with

2

2

NMOSNMOSNMOScond

PMOSPMOSPMOScond

IRP

IRP.

The resistances are calculated using functions calc_Ron_N and calc_Ron_N, which are presented in chapter

3.2.5. As noted there, the functions are dependent on gate to source voltage VGS, the width of the MOSFET w

and the mean value of the MOSFET current during the on state, which is equal to the mean current of the

inductor and, thus, to the load current.

Dynamic losses of semiconductors are dependent on the minimal and maximal value of the inductor current

since the system is changing its states with those current levels. The assumption is made that the currents are

Calculate Steady-state: D, Xk

START

END

Restore in time domain state variables:

iL (iL1), I0, I1, iCin, iCout, iPMOS (iPMOS1), iNMOS(iNMOS1)

Calculate DC and N harmonics of iL (iL1):

ILDC (IL1DC),ILn (IL1n)

Calculate effective values:

IL (IL1), ICin, ICout, IPMOS (IPMOS1), INMOS(INMOS1)

Calculate Passive Losses:

PLDC, PLAC, PLpar, PCin ESR, PCin par, PCout ESR, PCout par

Calculate Semiconductor Losses:

PPMOScond, PPMOSturn-on, PPMOSturn-off, PPMOSgate,

PNMOScond, PNMOSrev-rec, PNMOSturn-off, PNMOSgate,

PDeadTime:PtoN, PDeadTime:NtoP



page 46 of 72

constant during the switching. Further, the dynamic losses are also dependent on the mode of operation, or in

other words, on the waveform of the inductor current. There are three possible waveforms of the current and

they are presented in Fig. 41.

Figure 41. Single-Phase and Two-Phase Buck – Inductor current iL (iL1): a) CCM operation at heavy load; b) CCM operation at light load;

c) DCM operation at light load.

The first option is that the system is operating in CCM mode under the heavy load, as depicted in Fig. 41a.

Under these conditions, both minimal and maximal value of the inductor current, I0 and I1, are positive thus

creating turn-on and turn-off losses of the PMOS, PPMOSturn-on and PPMOSturn-off, reverse-recovery loss of the

NMOS body diode PNMOSrev-rec, dead-time conduction losses of the NMOS body diode during the both transients,

PDeadTime:PtoN and PDeadTime:NtoP and driver losses of both PMOS and NMOS, PPMOSgate and PNMOSgate. The equations

used for the losses calculations are

SWNtoPDTNDNtoPDeadTime

SWPtoNDTNDPtoNDeadTime

SWNRRrecNMOSrev

SWGSnNGSnGNNMOSgate

SWGSpPGSpGPPMOSgate

SWPoffPturnoffPMOSturn

SWPonPturnonPMOSturn

ftVIP

ftVIP

fIwEP

fVIwVQP

fVIwVQP

fIwEP

fIwEP

00:

11:

0

1

0

1

0

),(

),,(

),,(

),(

),(

,

where fSW is the switching frequency, wP and wN are the widths of the PMOS and NMOS, tDT PtoN and tDT NtoP are

corresponding dead-times defined in the GUI, while VND1 and VNDO are voltage drops of the NMOS body diode

during the conduction of I1 and I0, respectively. The voltage drops are calculated using modeling function

calc_bodyD_Vd, which is dependent on the width of the NMOS wN, as well of the conducting current I. NMOS

turn-on and turn-off losses are zero since the MOSFET is turned-on with zero voltage switching ()ZVS and

turned-off with positive inductor current, which is forcing the NMOS body-diode to conduct.

Similar behavior is obtained during DCM operating mode, shown in Fig. 41c, with the difference that

minimal inductor current I0 is equal to zero.

The last option of the inductor current waveform is for the case of CCM operation under light-load operating

condition, presented in Fig. 41b. The critical part is that minimal inductor current I0 is negative, which is

influencing NMOS to PMOS transition, provoking hard switch-off of the NMOS, since the body-diode is not

conducting. Further. ZVS switch-on of the PMOS and conduction losses of the PMOS body-diode. In addition,

the reverse-recovery losses of both PMOS and NMOS body-diodes are zero, since they are switch-off when the

corresponding current, iPMOS or iNMOS, changes its sign. The issue with the current semiconductor models is that

they are valid only for positive currents, which will be improved for the next versions of the CAD tool. In order

to maintain continuity of the model, the reverse-recovery loss of the NMOS and turn-on loss of the PMOS are

calculated with zero current, the gate charge of the PMOS, assuming symmetry, is calculated with absolute

value of I0, while PMOS body-diode voltage drop is assumed to be the same like it would be for the NMOS

diode and the NMOS turn-off losses are the same as they would be for PMOS. At the end, the system of

equations is

),(

),,(

),,(

)0,(

),(

),(

)0,(

00

00:

11:

1

0

0

1

IwVV

ftVIP

ftVIP

fVIwVQP

fVIwVQP

fwEP

fIwEP

fIwEP

fwEP

PDNPD

SWNtoPDTPDNtoPDeadTime

SWPtoNDTNDPtoNDeadTime

SWGSnNGSnGNNMOSgate

SWGSpPGSpGPPMOSgate

SWNRRrecNMOSrev

SWNoffPturnoffNMOSturn

SWPoffPturnoffPMOSturn

SWPonPturnonPMOSturn

.

The losses estimations of the Two-Phase and Coupled Two phase Buck are doubled since there are two

phases, while the necessary values for the models are obtained only from the first-phase inductor current iL1,

assuming the symmetry for the second current.

iL

(iL1)

iL

(iL1)

iL

(iL1)

I1

I0 I0

I1 I1

DCCMDCCM DDCM

DX

a) b) c)



page 47 of 72

Burst mode calculating functions

Burst mode operation is a light-load operation mode where the system is switching on the border between

CCM and DCM mode for N cycles while the output voltage is increasing from the minimal voltage value VMIN

up to the maximal value VMAX of the output voltage burst range, defined by the user, as presented in Fig. 42.

Then the system is turned-off until the output voltage is reduced to the minimal value VMIN. Burst mode is

implemented for Single-Phase and Two-Phase Buck converter, since there is a possibility that the system enters

in DCM operating mode at the end of the cycle.

Burst mode allows reduction of the losses under light-load conditions since the system is not switching for a

certain period of time thus reducing both dynamic losses and conduction losses, as well, due to the reduction of

the RMS current of the system comparing to the CCM operation. The benefit of this implementation in contrast

to Frequency Modulation in DCM is that, since the system is operating in the CCM-DCM border, the inductor

current can be used to achieve ZVS on the high-side switch reducing the losses. Furthermore, since the system

enters only once during the cycle in high-impedance mode (state “X”), the oscillations of the high-impedance

node occurs only once compared to FM-DCM where the oscillation occurs every switching cycle, thus

increasing the losses.

Figure 42. Single-Phase Buck – Burst Mode: the inductor current (blue) and the ouput voltage (red).

Figure 43. Burst mode calculating functions algorithm.

Burst mode calculating algorithm is presented in Fig. 43. The first step of the algorithm is to calculate CCM

operation point, thus obtaining the duty-cycle D, for constant on-time implementation, or inductor current peak

to peak value, for PCMC implementation. Further, energy variables, which are used to estimate the non-

conduction losses, are set to zero and initial state vector is defined so that the inductor current is zero, the output

voltage is VMIN and that capacitor current is negative value of the output current. Next the system enters in the

while loop where it remains until the output voltage reaches maximal value VMAX of the output voltage burst

range. In the loop, the tool simulates the system for one switching cycle, saves the currents of the system,

accumulates the dissipated energies and tests the output voltage for the loop termination condition. The

accumulation of the dissipated energies are done using

iL

I1

vOUT

VMAX

VMIN

TSW 2TSW NTSW Ttotal

END

Calculate effective values:

IL (IL1), ICin, ICout, IPMOS (IPMOS1), INMOS(INMOS1)

Calculate Semiconductor Losses:

PPMOScond, PPMOSturn-on, PPMOSturn-off, PPMOSgate,

PNMOScond, PNMOSrev-rec, PNMOSturn-off, PNMOSgate,

PDeadTime:PtoN, PDeadTime:NtoP

Find Ttotal and simulate:


Calculate Passive Losses:

PLDC, PLAC, PLpar, PCin ESR, PCin par, PCout ESR, PCout par

CONTINUING

Calculate CCM Steady-state: D, Xk

Set initial energies: ELDC, ELAC, EPMOSturn-on,

EPMOSturn-off, EPMOSgate, ENMOSrev-rec, ENMOSturn-off,

ENMOSgate,, EDeadTime:PtoN, EDeadTime:NtoP =0

Set initial state vector: iL=0, vOUT=VMIN, iC=-IOUT

START

Simulate one switching cycle:


Accumlate energies: ELDC, ELAC, EPMOSturn-on,

EPMOSturn-off, EPMOSgate, ENMOSrev-rec, ENMOSturn-off,

ENMOSgate,, EDeadTime:PtoN, EDeadTime:NtoP

while vOUT<VMAX

BREAK



page 48 of 72

NtoPDTNDNtoPDeadTimeNtoPDeadTime

PtoNDTNDPtoNDeadTimePtoNDeadTime

GSnNGSnGNNMOSgateNMOSgate

GSpPGSpGPPMOSgatePMOSgate

NRRrecNMOSrevrecNMOSrev

PoffPturnoffPMOSturnoffPMOSturn

PonPturnonPMOSturnonPMOSturn

SW

Nharm

n

LnLACLACLAC

SWLDCLDCLDCLDC

NMOSNMOSNMOScond

PMOSPMOSPMOScond

tVIEE

tVIEE

VIwVQEE

VIwVQEE

IwEEE

IwEEE

IwEEE

TI

nfREE

TIREE

IRP

IRP

00::

11::

1

0

0

1

0

1

2

2

2

2

),,(

),,(

),(

),(

),(

2)(

.

Upon detecting that the output voltage is bigger than the maximal value VMAX, the tool simulates system in

state “X” (or state “XX” for Two-Phase Buck) until the output voltage is returned to its initial value VMIN, thus

obtaining the period of burst cycle Ttotal. After, effective values if the currents are calculated and the losses are

obtained using

totalNtoPDeadTimeNtoPDeadTime

totalPtoNDeadTimePtoNDeadTime

totalNMOSgateNMOSgate

totalPMOSgatePMOSgate

totalrecNMOSrevrecNMOSrev

totaloffPMOSturnoffPMOSturn

totalonPMOSturnonPMOSturn

NMOSNMOSNMOScond

PMOSPMOSPMOScond

CoutparCoutparCout

CoutCoutESRCout

CinparCinparCin

CinCinESRCin

LLparLpar

totalLACLAC

totalLDCLDC

TEP

TEP

TEP

TEP

TEP

TEP

TEP

IRP

IRP

IRP

IESRP

IRP

IESRP

IRP

TEP

TEP

/

/

/

/

/

/

//

/

::

::

2

2

2

2

2

2

2

.

Burst mode calculation for the Two-Phase is implemented in similar manner with the difference that both

phases are used equally, while the losses are calculated for only one phase and at the end doubled to obtain total

losses of the system.

3.4.4. Single-variable multi-point search algorithm

Single-variable multi-point search algorithm (SVMP) is generic algorithm used to find an input variable

value x for which a cost function f(x) has its maximal value. The function f(x) is known but its first derivative is

not, thus analytical methods are not applicable so numerical solving approach is used. The algorithm is used in

optimizing function to search the optimal values of the components of the converter system.

The graphical interpretation of the SVMP algorithm is presented in Fig. 44a, while its implementation is

presented in Fig. 44b. The algorithm starts by setting the control flag DOit to true and minimal and maximal

input value, xMIN and xMAX. The algorithm enters in a while-loop and it executes set of instructions until the

DOit-flag is not set to false. In the loop, the algorithm sets six-point vector with equidistant values used to

estimate the cost function. Upon the calculations, performed in for loop, the maximal value of the cost function

YOPT, shown in Fig. 44a as violet component, is found as well as its index in the vector jOPT. Then new minimal

and maximal values, xMIN and xMAX, for the input variable are selected. The new minimal value xMIN is the input

vector component with the index jOPT-1 with constrain that the index cannot be smaller than 1, which may be

calculated the case if the optimal component is the first. On the other hand, the new maximal value xMAX is the

input vector component with the index jOPT+1 with constrain that the index cannot be bigger than 6, which may

be calculated the case if the optimal component is the last. Doing so, the search area is reduced to two fifths of

the initial one.

Next step in the algorithm is to calculate the difference of the maximal and minimal input values Δx and to

compare it to the input precision Xprec. If the Δx is smaller than the input precision, the algorithm sets DOit flag

to false and finishes the execution. The outputs of the algorithm are the lastly obtained optimal output value

YOPT and the input component which corresponds to the optimal index x(jOPT). In the case that the condition for

terminating the execution of the algorithm has not been met, the sequence of commands repeats. Since for each

iteration the search area is reduced to two fifths of the initial one, while the optimal value is kept inside, the

algorithm is creating two arrays xMIN[i] and xMAX[i] which are converging one to another like in the case of

Single-variable single-point search algorithm. In addition, since it is unknown does the cost function has several

maximums, searching in six equidistant points is improving the coverage of the input area, thus local maximums

can be recognized and ignored. In addition, since the search area is reduced to two fifths of the initial one,



page 49 of 72

convergence of the algorithm is improved compared to the implementation where the input vector contains the

equidistant components the difference between them equal to the input precision.

Figure 44. Single-variable multy-point search algorithm: a) graphical interpretation (calculated values (green), optimal values (violet), new

minimal value (blue) and new maximal value (red)) and b) implementation diagram.

3.4.5. Optimization function algorithm

The optimization functions are one of the two top-level functions of the PowerSwipeOptimization_v2

function and it is used to perform optimization of the selected topology under constrains of the design imposed

by the GUI. The algorithm is implemented in four optimization functions presented in 3.2.2.

Figure 45. Optimization function algorithm.

a) b)

xMIN xMAX

y=f(x[i,j])

i=1

Y1Y2

Y3 Y4 Y5

Y6

xMIN xMAX

i=2

Y1

Y2

Y3Y4 Y5

Y6

xMIN xMAX

i=N

Y1

Y2

Y3 Y5 Y6

Y4

Δx1

Δx2

ΔxN

true

false

true

DOit=true

xMAX

xMIN

while (DOit)

dx=(xMAX-xMIN)/5

x[1:6]=xMIN : dx : xMAX

START

END

Y[j]=f(x[j])

for j=1:6

[YOPT, jOPT]=max(Y)

xMIN=x(max(jOPT -1, 1))

xMAX=x(min(jOPT +1, 6))

(xMAX -xMIN)<Xprec

DOit=false

xOPT=x(jOPT )

YOPT=Y(jOPT )

false

true

START

END

COPT, LOPT,

wpOPT, wnOPT

eff(ITYP,CCM)

eff(ITYP,DCM)

eff(ITYP,BURST)

eff(IMAX,CCM)

eff(IMAX,DCM)

eff(IMAX,BURST)

eff(IMIN,CCM)

eff(IMIN,DCM)

eff(IMIN,BURST)

dwp=(wpMAX-wpMIN)/5wp[1:6]=wpMIN:dwp:wpMAX

while (DOitC)

dC=(CMAX-CMIN)/5C[1:6]=CMIN:dC:CMAX

DOitC, CMAX, CMIN

for jC=1:6

DOitL, LMAX, LMIN

while (DOitL)

dL=(LMAX-LMIN)/5L[1:6]=LMIN:dL:LMAX

for jL=1:6

DOitwp, wpMAX, wpMIN

while (DOitwp)

for jwp=1:6

DOitwn, wpMAX, wpMIN

while (DOitwn)

dwn=(wnMAX-wnMIN)/5wn[1:6]=wnMIN:dwp:wnMAX

for jwn=1:6

[effwnOPT, jwnOPT]=max(effwn)wnMIN=wn(max(jwnOPT-1, 1))wnMAX=wn(min(jwnOPT+1, 6))

(wnMAX -wnMIN)<wprec

wnOPT=wn(jwnOPT)effwnOPT, DOitwn

false

truetruetrue

true

effwp(jwp)=effwnOPT

wnwp(jwp)=wnOPT

[effwpOPT, jwnOPT]=max(effwp)wpMIN=wn(max(jwpOPT-1, 1))wpMAX=wn(min(jwpOPT+1, 6))

true

(wpMAX -wpMIN)<wprecfalse

wpOPT=wp(jwpOPT)wnOPT=wnwp(jwpOPT)

effwpOPT, DOitwp

false

effL(jL)=effwpOPT

wpL(jL)=wpOPT

wnL(jL)=wnOPT

[effLOPT, jLOPT]=max(effL)LMIN=L(max(jLOPT-1, 1))LMAX=L(min(jLOPT+1, 6))

true

(LMAX -LMIN)<Lprec

false

LOPT=L(jLOPT)wpOPT=wpL(jLOPT)wnOPT=wnL(jLOPT)effLOPT, DOitwp

false

effC(jC)=effLOPT

LC(jC)=LOPT

wpC(jC)=wpOPT

wnC(jC)=wnOPT

false

[effCOPT, jCOPT]=max(effC)CMIN=L(max(jCOPT-1, 1))CMAX=L(min(jCOPT+1, 6))

true

(CMAX -CMIN)<Cprec

false

COPT=C(jCOPT)LOPT=LC(jCOPT)

wpOPT=wpC(jCOPT)wnOPT=wnC(jCOPT)

effOPT, DOitC

false

sol

System(C(jC),L(jL),wp(jwp),wn(jwn))effwn=efficiency(System)



page 50 of 72

The optimization function algorithm is presented in Fig. 45 and it consists of four nested single-variable

multi-point (SVMP) search algorithms where the input variables in the algorithms are the values of the

components while the outputs are optimized values and the maximal achieved efficiency. According the Fig. 45,

for each SVMP search algorithm the next level SVMP search algorithm represents its cost function down to the

last level SVMP search algorithm where the cost function is the efficiency of the system at typical load current

ITYP. Before entering in the optimization function algorithm, the CAD tool loads all parameters and constrains of

the system from GUI then it stats to execute the algorithm.

Upon entering, the first step is to set DOitC flag to true and to calculate initial minimal and maximal values

of the output capacitor whose SVMP search is the highest level. The initial maximal value CMAX is obtained as

maximal capacitance which fits in 35% of the available area, since the assumption is made that, in order to

facilitate fabrication, both input and output capacitors are the same, thus consuming 70% of the available area,

while the rest 30% is left for through silicon vias (TSV). The minimal value CMIN is based on the dynamic

constrains, since for all the topologies, the closed loop output impedance is mainly determined by the closed-

loop gain and by the output capacitor. Additional limit is imposed that the capacitance cannot be smaller than

50 nF. The next step in execution is that the tool enters in the first while loop where it remains, according to the

previous chapter, until the difference of maximal and minimal capacitor value, CMAX and CMIN, is smaller than

the capacitor value precision Cprec. The output capacitor value vector gets defined upon entering the while loop

and the tool then enters in the first for loop where, for each capacitor value from the vector, using the second

level SVMP search, the tool gets optimal efficiency effLOPT, the inductance of the inductor LOPT and the widths

of the MOSFETs wpOPT and wnOPT. The obtained values are saved in corresponding vectors. Then maximal

value of efficiency effCOPT is then found and its index jCOPT. Following, new minimal and maximal output

capacitor values, CMIN and CMAX, are assigned and their difference is tested for the termination of the SVMP

search algorithm. In the case that the precision is not achieved the cycle is repeated reducing the capacitor

search area to two fifths of the initial. In the case that the termination condition is achieved, the tool exits the

while loop by setting set DOitC flag to false and the optimal component values are saved in COPT, LOPT, wpOPT

and wnOPT. Then the system gets defined and efficiencies and losses are calculated for minimal, typical and

maximal load current under CCM and/or DCM and BURST operating conditions. The last step is to define

output sol which is defined in APPENDIX II.

As mentioned before, the SVMP search for optimal output capacitor is using the second level SVMP search

algorithm to obtain the efficiencies and optimal designs for each capacitor value C(jC) from the output capacitor

value vector. The second level SVMP search algorithm is used to find an optimal value of the inductance for a

selected capacitor value C(jC). Similarly as in the previous case, the first step is to define initial minimal and

maximal inductor values for a given C(jC). The initial maximal value LMAX is defined in GUI, while the initial

minimal inductor value LMIN is calculated to satisfy stability constrains as well as maximal inductor current

ripple and maximal output voltage ripple. Then the tool enters in second level while loop where the inductor

value vector is defined and used in following for loop to obtain optimal widths of the MOSFETs for each

inductor value L(jL). The tool repeats the cycle until the inductor precision is bigger than the difference of the

minimal and maximal inductor value, when the optimal design and efficiency are delivered to the upper level

SVMP search algorithm.

The cost function of the second level SVMP search is the third level SVMP search algorithm where optimal

width of PMOS is searched for a given output capacitor C(jC) and inductor L(jL). Initial minimal and maximal

widths are defined by GUI. The third level SVMP search is using, once again, the fourth and the last level

SVMP search algorithm as a cost function. The last level SVMP search is optimizing the width of a NMOS for a

given C(jC), L(jL) and wp(jwp). Initial minimal and maximal widths are also defined by GUI. As the lowest level

SVMP search algorithm, the cost function consist of creating the switching model of the topology, presented in

3.3.4, and then estimating the efficiency of the system at typical load using the method presented in 3.4.3.

3.4.6. Analysis function algorithm

The analysis functions are one of the two top-level functions of the PowerSwipeOptimization_v2 function

and it is used to perform analysis of the selected topology design defined in GUI and perform the static and

dynamic tests, as well to design regulator and calculate minimal capacitors which are satisfying the static and

dynamic constrains of the design imposed by the GUI. The algorithm is implemented in four optimization

functions presented in 3.2.3.

The analysis function algorithm is presented in Fig. 46 and its execution is defined by the status flags which

are defined in PowerSwipeOptimization_v2 function and depended on the selected tests form control part of the

GUI, presented in 3.1.4. Before starting the execution of the algorithm, the tool loads all the design variables

from GUI which are used in creating the models, such as the output and input capacitor capacitance, the

inductance and semiconductor parameters.



page 51 of 72

Figure 46. Analysis function algorithm.

The first step in algorithm execution is to define the open-loop switching model System which is used for

static behavior analysis and to create open-loop linear model. Upon the creation of the model, the tool tests are

the static behavior flags (Static_typ, Static_max and Static_min) set and for the flags that are true, the tool

performs time domain simulation and the losses calculation, thus presenting the currents and voltages of interest

during the steady-state operation in time domain and the breakdown of the losses for that operating point.

Depending on selected mode of operation, the tool performs simulations only for CCM mode of operation, if

CCM mode is selected, or for all three, CCM, DCM and BURST mode of operation in the case that DCM mode

is selected. Additional condition for DCM and BURST mode simulations are that the inductor current is

negative at some instance of time during the CCM operation. The final analysis that can be performed, in the

case that it is selected, is the sweep of the efficiency in function of the load current IOUT. If the Static_sweep flag

is true, the output current vector is defined with 101 equidistant points from the minimal load current IMIN up to

the maximal load current IMAX. For each point of the vector the efficiency of the system is calculated for CCM

and/or DCM and BURST mode and it is plotted for comparison.

Following the static behavior analysis, the tool performs the dynamic behavior analysis. The first step is to

create the open-loop linear model and to calculate what are the gain and the phase of the system at desired

closed-loop bandwidth frequency BW. The closed-loop bandwidth frequency BW is selected to be one fifth of

the switching frequency fSW for Single-Phase VMC Buck or to be one seventh of the switching frequency fSW for

PCMC systems. In the case of PCMC systems lower bandwidth frequency has been selected since inductor

current loop also exists and its bandwidth is set to be at half of the switching frequency fSW. In addition, due to

true

false

true

false

true

false

true

false

true

false

VIN(j)=VIN - 0.5ΔVIN ± ΔVIN(j) step(t(j) - 3TSW)

true

false

true

false

true

false

START

Static_typ

efficiency(System, ITYP, CCM)

efficiency(System, ITYP, DCM)

efficiency(System, ITYP, BURST)

Static_max

System(C, L, wp, wn)

Static_min

efficiency(System, IMIN, CCM)

efficiency(System, IMIN, DCM)

efficiency(System, IMIN, BURST)

Static_sweep

for IOUT = IMIN:(IMAX-IMIN)/100:IMAX

efficiency(System, IOUT , CCM)

efficiency(System, IOUT , DCM)

efficiency(System, IOUT , BURST)

efficiency(System, IMAX, CCM)

efficiency(System, IMAX, DCM)

efficiency(System, IMAX, BURST)

BREAK 1

MinCap

iCin, iCout @ IMAX

t(2i) = 0 : (SR(i) + 20TSW)

IOUT(i)=±ΔIOUT(i) step(t(i) - 3TSW)

t(2j) = 0 : (SR(j) + 20TSW)

VIN(j)=± ΔVIN(j) step(t(j) - 3TSW)

Simulate(CLSM, t(j), VIN(j))

SVSP search: CINmin

Input: CIN

CINmin = 50nF, CINmax = Cmax

Output: VIN P-P

Reference: VIN P-Pmax

f(x): vIN(t) = Sim(CIN, iCin(t))

VIN P-P = max(vIN(t)) - min(vIN(t))

SVSP search: COUTmin

Input: COUT

COUTmin = 50nF, COUTmax = Cmax

Output: VOUT P-Pstat, VOUTdyn

Reference: VOUT P-Pstat max,VOUTdyn max

f(x): System(COUT, L, wp, wn)

OLLM=OpLoopLinModel(System)[G, Ph]=OLLM(jBW)

R=regulator(type, BW,G, Ph)CLLM=ClLoopLinModel(System,R)

vOUTstat (t) = Sim(COUT, iCout(t))VOUT P-Pstat = max(vOUTstat (t)) -

min(vOUTstat (t))

vOUTdyn(i) (t)= Sim(CLLM, IOUT(i))vOUTdyn(j) (t) = Sim(CLLM,VIN(j))

VOUTdyn =max( |ΔvOUTdyn(i)|, |ΔvOUTdyn(j)|)

END

CONTINUING 2CONTINUING 1

OLLM=OpLoopLinModel(System)

[Gain, Phase]=OLLM(jBW)

R=regulator(type, BW,Gain, Phase)

CLSM=ClLoopSwModel(System,R)

Dynamic_reg

f = 1KHZ:100MHz

CLLM=ClLoopLinModel(System,R)

L(s)=R(s)·GCTRtoOUT(s)

[GainOL, PhaseOL]=OLLM(jf)

[GainCL, PhaseCL]=CLLM(jf)

[GainR, PhaseR]=R(jf)

[GainL, PhaseL]=L(jf)

Dynamic_load

for j = 1:NLoadSteps

t(j) = 0 : (SR(j) + 20TSW)IOUT(j)=ΔIOUT(j) step(t(j) - 3TSW)

Simulate(CLSM, t(j), IOUT(j))

Dynamic_vin

for j = 1:NVinSteps

t(j) = 0 : (SR(j) + 20TSW)

VIN(j)=VIN - 0.5ΔVIN +

ΔVIN(j) step(t(j) - 3TSW)

Simulate(CLSM, t(j), VIN(j))

VIN(j)=VIN - 0.5ΔVIN + ΔVIN(j) step(t(j) - 3TSW)

BREAK 2

U



page 52 of 72

the lacking of precise model of Coupled Two-Phase PCMC Buck, the needed gain and phase of the open-loop

switching system are obtained simulating the system in the time domain with a perturbation introduced in

inductor current reference. The perturbation has small amplitude in order not to produce too much nonlinear

effects and the frequency of the perturbation is equal to bandwidth frequency. Upon obtaining the open-loop

gain and the phase of the system, the regulator is design and later closed-loop switching model CLSM. Then the

tool tests Dynamic_reg flag and, in the case that it is true, the closed-loop linear model CLLM is created.

Amplitude and phase characteristics of open-loop and closed-loop linear models as well of regulator and closed

loop gain are presented in frequency range from 1 kHz up to 100 MHz.

Following the regulator design and presentation of the frequency characteristics, the Dynamic_load and

Dynamic_vin flags are tested and if they are true the tool performs N load steps and M input voltage step tests on

the closed-loop switching model CLSM. The numbers of load and input voltage step tests are defined in GUI by

the length of the load-step amplitude and input voltage step vectors, respectively. First, in the case of the load

step tests, for jth

load step test, the time vector t[j] is defined following the definition of the output current

waveform IOUT[j]. The load current is defined with equation

tjSetTimeTD

jSetTimeTDtTD

TDt

jI

TDtjSetTime

jI

A

tjI

SW

SWSW

SW

OUT

SWOUT

OUT

][3

][33

3

][

3][

][

0

)]([ ,

where ΔIOUT[j] is the jth

load-step amplitude and SetTime[j] is the jth

load-step settling time. For defined time

vector and load current vector the model is tested and the currents and voltages are presented in time domain.

The simulations of the input voltage step tests are performed in similar manner. First, for jth

input voltage

step test, the time vector t[j] gets defined, following the input voltage waveform vIN[j] and then the model gets

simulated. The input voltage waveform is defined with equation

tjSetTimeTD

jSetTimeTDtTD

TDt

jVV

jSetTime

TDtjVjVV

jVV

tjv

SW

SWSW

SW

ININ

SWINININ

ININ

IN

][3

][33

3

2

][

][

3][

2

][

2

][

)]([ ,

where ΔVIN[j] is the jth

input voltage step amplitude and SetTime[j] is the jth

input voltage step settling time. For

defined time vector and input voltage step current vector the model is tested and the currents and voltages are

presented in time domain.

The final part of the analysis function algorithm is calculation of minimal input and output capacitor CINmin

and COUTmin. The calculations are performed in the case that MiCap status flag is true. If that is the case, the first

step is to define in the time domain the steady-state input and output capacitor currents, iCin and iCout, under the

maximal load current IMAX. In this operating condition the input capacitor current is producing maximal ripple

causing maximal input voltage ripple. The output capacitor current has triangular waveform from CCM

operation, thus provoking maximal output voltage ripple. Further, 2N load steps and 2M input voltage steps are

defined which are used for estimation of output voltage deviation under dynamic tests using closed-loop linear

model CLLM. The number of the tests is doubled compared to the time domain tests, presented above, since the

system is tested on both positive and negative steps. The current load steps are defined using (79), while the

input voltage steps are defined with (80) with the difference that initial input voltage is equal zero.

Upon defining all the waveforms, the tool enters in the first single-variable single-point (SVSP) search

algorithm to find minimal input capacitor. The input in the algorithm is the input capacitor CIN, while initial

minimal and maximal values, CINmin and CINmax, are 50 nF, which is system level constrain, and Cmax, which is a

maximal capacitor which can fit in 35% of available area. The output value of the algorithm is static peak to

peak ripple of the input capacitor voltage VIN P-P, while the target value is maximal static input capacitor voltage

peak to peak ripple VIN P-Pmax. The tool is simulating in time domain the response of the capacitor with a current

value CIN on the injected current iCin. If the voltage ripple is smaller than the maximal, the current value CIN

becomes maximal value CINmax for the next iteration, or if it is bigger it becomes minimal value CINmin. The

algorithm is repeated until the difference between maximal and minimal capacitor value becomes less than 2 nF

or the difference between the current input voltage ripple and the maximal is less than 0.1mV.



page 53 of 72

After obtaining the input capacitor, the tool enters in the second (SVSP) search algorithm to find minimal

output capacitor. The input in the algorithm is the output capacitor COUT, while initial minimal and maximal

values, COUTmin and COUTmax, are 50 nF, which is system level constrain, and Cmax, which is a maximal capacitor

which can fit in 35% of available area. The output values of the algorithm are static peak to peak ripple of the

output capacitor voltage VOUT P-Pstatic and maximal deviation of the output voltage under the dynamic tests

vOUTdyn. The target values are maximal static output capacitor voltage peak to peak ripple VOUT P-Pmax and

maximal output voltage dynamic deviation vOUTdyn max. The tool is simulating in time domain the response of the

capacitor with a current value COUT on the injected current iCout and calculates current static peak to peak ripple

VOUT P-Pstatic. Further, the open-loop switching model is created, following the creation of the current open loop

linear model OLLM. The OLLM is used to calculate the gain and the phase of the system at the bandwidth

frequency BW. Then the regulator gets design and the closed loop linear model CLLM. Finally, the closed loop

linear model is tested in time domain on load steps and input voltage steps. The maximal deviation of all the

measured deviations is selected as the current output voltage maximal deviation vOUTdyn which is used to create a

cost function together with VOUT P-Pstatic. If current static peak to peak ripple VOUT P-Pstatic is smaller than the

maximal VOUT P-Pmax and if the current output voltage maximal deviation vOUTdyn is samller than the maximal

output voltage dynamic deviation vOUTdyn max, the current value COUT becomes maximal value COUTmax for the next

iteration. In the case that one of the two conditions is not satisfied, the current value COUT becomes minimal

value COUTmin. The algorithm is repeated until one of the three following conditions is not met:

1. The absolute error between the current static peak to peak ripple VOUT P-Pstatic and maximal VOUT P-Pmax

is smaller than 1μV, while the current output voltage maximal deviation vOUTdyn is smaller than the

maximal output voltage dynamic deviation vOUTdyn max

2. The absolute error between current output voltage maximal deviation vOUTdyn and maximal output

voltage dynamic deviation vOUTdyn max is smaller than 1μV, while the current static peak to peak ripple

VOUT P-Pstatic is smaller than the maximal static peak to peak ripple VOUT P-Pmax

3. The difference between maximal and minimal capacitor, COUTmax and COUTmin, value becomes less

than 2 nF while both current static peak to peak ripple VOUT P-Pstatic and current output voltage maximal

deviation vOUTdyn are smaller than than the maximal static peak to peak ripple VOUT P-Pmax and the

maximal output voltage dynamic deviation vOUTdyn max, respectively.

Upon finishing the searches for minimal capacitors, the tool presents the values in the Status field of the GUI

and the tool exits the algorithm.



page 54 of 72

3.5. Results of the Optimization

This chapter presents the results of the optimization of Low Voltage DC-DC Converter (LV-DCDC) of

Power Swipe project system. All three converter topologies implemented in the CAD tool are optimized under

constrains imposed by Power Swipe project specification for two operating frequencies (10MHz and 20 MHz).

the results of the optimization are presented in Table VII.

TABLE VII. RESULTS OF THE OPTIMIZATION

Frequency 10 MHz 20 MHz

Topology

Single

Buck VMC

or PCMC

Two-Phase

Buck

PCMC

Coupled

Two-Phase

Buck

PCMC

Single

Buck VMC

or PCMC

Two-Phase

Buck

PCMC

Coupled

Two-Phase

Buck

PCMC

COUT [nF] 961.63 442.16 939.73 725.83 460.73 673

ESR [mΩ] 3.65 7.92 3.73 4.83 7.59 5.21

area [mm2] 4.81 2.21 4.7 3.63 2.3 3.37

N12n 75 34 73 56 35 52

N3n9 0 1 1 2 3 2

N1n6 1 2 1 1 1 0

VOUT P-P [mV] 61.95 3.81 6.39 5.41 2.66 5.22

RCoutPAR [mΩ] 10 10 10 10 10 10

LCoutPAR [pH] 100 100 100 100 100 100

CIN [nF] 961.63 442.16 939.73 725.83 460.73 673

ESR [mΩ] 3.65 7.92 3.73 4.83 7.59 5.21

area [mm2] 4.81 2.21 4.7 3.63 2.3 3.37

N12n 75 34 73 56 35 52

N3n9 0 1 1 2 3 2

N1n6 1 2 1 1 1 0

VIN P-P [mV] 22.36 6.91 5.12 16.92 6.26 5.02

RCinPAR [mΩ] 10 10 10 10 10 10

LCinPAR [pH] 1000 1000 10000 1000 1000 1000

LOUT [nH] 219.62 341.19 146.4 143.73 212.87 102.08

LM [nH] - - 700

700

RLDC [mΩ] 219.62 682.38 292.8 143.73 425.74 204.16

IL P-P [mA] 447.2 283.86 250.87 336.1 224.93 172.5

RLPAR [mΩ] 10 10 10 10 10 10

LLPAR [pH] 1000 1000 1000 1000 1000 1000

wP [μm] 12000 7996.56 7756.94 8007.37 5994.93 4039.73

RP [mΩ] 290.8 635.67 661.94 634.82 857.48 1305.05

wN [μm] 12000 7985.91 6010.07 9999.18 5994.93 4013.11

RN [mΩ] 80.17 174.25 232.99 138.54 233.6 353.81

tDT:P2N [ps] 1000 1000 1000 1000 1000 1000

tDT:N2P [ps] 1000 1000 1000 1000 1000 1000

VGSP [V] 5 5 5 5 5 5

IGP [mA] 80 80 80 80 80 80

VGSN [V] 5 5 5 5 5 5



page 55 of 72

IGN [mA] 80 80 80 80 80 80

ηCCMtyp [%] 83.22 79.41 85.28 81.56 79.93 83.36

Losses CCMtyp [mW] 67.74 87.09 58 75.98 84.35 67.07

ηCCMmax [%] 80.65 76.65 83.19 77.8 77.7 79.73

Losses CCMmax [mW] 143.94 182.74 121.22 171.2 172.19 152.56

ηCCMmin [%] 63.81 56.92 65.47 65.39 56.38 66.69

Losses CCMmin [mW] 34.04 45.41 31.65 31.75 46.43 29.97

ηDCMmin [%] 71.13 69.56 - 70.23 63.41 -

Losses DCMmin [mW] 24.35 26.25 - 25.44 34.62 -

ηBURSTmin [%] 81.83 80.66 - 80.27 80.91 -

Losses BURSTmin [mW] 13.32 14.39 - 14.75 14.16 -

Table VII provides complete design information such as, regarding the capacitors design, input and output

capacitor values (CIN and COUT), parasitic (ESR, RC*PAR and LC*PAR), implementation (area, N12n, N3n9 and

N1n6) and maximal voltage ripple (V* P-P). Further, the information regarding the inductor or leakage inductor

are presented, such as inductance (LOUT), DC resistance (RLDC), parasitics (RLPAR and LLPAR) and maximal current

ripple (IL P-P). In the case of the Coupled Two-Phase Buck converter, the magnetizing inductance (LM) is

provided as well. The semiconductor design information consists of the widths (wP and wN), the on-resistances

(RP and RN), the gate to source voltages (VGSP and VGSN), the maximal gate currents (IGP and IGN) and dead-times

(tDT:P2N and tDT:N2P). The last part of the table provides efficiencies and the losses of the three systems for both

operating frequencies. As it can be seen, the highest efficiency can be achieved by using Coupled Two-Phase

Buck converter but this estimation needs to be taken with precaution since the model of the coupled inductors

has not been verified and the performance of the converter is highly dependent on the magnetizing inductance,

which can provoke higher losses if the inductance is not high enough. The system with lower magnetizing

inductance has higher misbalance of the inductor currents thus degrading the system to Two-Phase Buck

converter which has, according the results, the lowest efficiency for both operating frequencies. The reason for

poorer performance of Two-Phase Buck is that the resistance of the inductors remains high producing big losses,

both DC as well the AC. In addition, the high inductor current ripple, responsible for high AC inductor losses,

also produces high conduction and switching losses of MOSFETs which are now doubled due to the existence

of the two phases. The Single-Phase Buck converter presents modest performance with efficiency of 83.22%

and 81.56% at 10 MHz and 20 MHz switching frequency. Due to the smaller components used in the 20 MHz

design, it is currently selected as the optimal. The design has been verified in Cadence software and comparison

between the CAD tool estimation and Cadence simulation is given in Table VIII.

TABLE VIII. COMPARISON BETWEEN THE CAD TOOL ESTIMATION AND CADENCE SIMUALTION OF SINGLE-PHASE BUCK AT 20 MHZ

The CAD estimation Cadence simulation

VOUT P-P [mV] 5.71 5.127

IL P-P [mA] 335.86 321

ηCCMtyp [%] 81.57 82.68

Losses CCMtyp [mW] 75.94 71

ηCCMmax [%] 77.72 78.08

Losses CCMmax [mW] 172.03 168.2

ηCCMmin [%] 65.14 70.92

Losses CCMmin [mW] 32.11 24.69

As it can be seen from the Table VIII, the estimation and simulation are relatively in good agreement. The

improved efficiency of the simulation can be explained due to the absence of the frequency dependent inductor

resistance, which is introducing a small constant offset between the simulation and the estimation losses, and

due to the optimized dead times of the system. The light load estimation is not in an agreement with the

simulation since the semiconductors models are not valid for negative currents, which is the simulated/estimated

case. For the design of Single-Phase Buck at 20 MHz, steady-state operation at typical load is presented in Fig.

47 and Fig. 48.



page 56 of 72

Figure 47. Single-Phase Buck at 20 MHz: typical load – steady-state waveforms.

Fig. 47 presents all the voltages and currents of interest of the system. It can be seen that both input and

output voltages are within the static specification bounds, shown with red dashed line. Furthermore, Fig. 48

presents breakdown of the losses of converter system. The losses are relatively equally balanced between the

passives (20%), the PMOS (42.2) and the NMOS (37.8). also, it can be seen that the biggest losses components

are conduction losses of MOSFETs and DC losses of the inductor, consuming in total 48.44% of total losses. On

the other hand, the dynamic losses (23% in PMOS and 23.3% in NMOS) are balanced with conduction losses

(19.2% in PMOS and 14.5% in NMOS). It can be noted that the big impact in the losses have the dead-time

losses which can be reduced by implementation of optimal dead-time controller.

Figure 48. Single-Phase Buck at 20 MHz: typical load – breakdown of the losses.

0 50 100 1500

0.5

1

Duty

0 50 100 1501150

1200

1250

vOUT

[mV]

0 50 100 1500

200

400

600

iL [mA]

0 50 100 150-200

0

200

iCout

[mA]

0 50 100 1500

200

400

600

iPmos

[mA]

0 50 100 1504800

5000

5200

vCin

[mV]

0 50 100 1500

200

400

600

t [ns]

iNmos

[mA]

0 50 100 150-200

0

200

400

t [ns]

iCin

[mA]

Waveforms of Single Phase(CCM) @ IOUTtyp

4%

15%

1%< 1%< 1%< 1%< 1%

19%

2%

11%11%

15%

< 1%

3%

10%

9%2%

Lout hf: (3.66 %)

Lout dc: (14.71 %)

Lout PAR (1.14 %)

Cout ESR (0.06 %)

Cout PAR (0.12 %)

Cin ESR (0.11 %)

Cin PAR (0.23 %)

PMOS conduction (19.20 %)

PMOS turn-on (1.69 %)

PMOS turn-off (10.63 %)

PMOS gate-drive (10.68 %)

NMOS conduction (14.53 %)

NMOS turn-off (0.00 %)

NMOS reverse-recovery (3.27 %)

NMOS gate-drive (9.59 %)

dead-time:pmos2nmos (8.68 %)

dead-time:nmos2pmos (1.71 %)

Efficiency:0.81292

Breakdown Of the Losses in Single Phase(CCM) @ IOUTtyp



page 57 of 72

Figure 49. Single-Phase Buck at 20 MHz: efficiency vs. load curretn (CCM-blue, DCM-green and Burst-red) .

The efficiency dependence on the load current for Single-Phase Buck at 20 MHz is presented in Fig. 49. The

system has been simulated under all operating modes and it can be seen that, for high load conditions, the

system is in CCM operating mode and it has relativity constant efficiency in the range of 160 mA up to 300 mA,

covering the typical load case, and then the efficiency is dropping as the load current increases due to the high

conduction losses. On the other hand, for the light load conditions, burst mode is presenting drastically better

performance compared to both CCM and DCM operation. The difference of the efficiency is obtained since, in

burst mode operation, the system is operating in the CCM/DCM border where the system has sufficiently high

efficiency, and then the system is turned-off, thus minimizing the losses. In contrast due to the constant

switching, CCM and DCM operation modes present low efficiency due to the dominant driving losses.

Minimal capacitors for all three topologies operating at 20 MHz are calculated and presented in Table IX.

Since the dynamic tests are not stressful for the system, as well as the static constrains, minimal capacitances are

around 50 nF which represents the CAD tool internal constrain. Since available area is sufficient for

implementation of the optimal capacitors, their use is preferable in order to ensure higher robustness of the

system control which is dependent on the output filter resonance.

TABLE IX. MINIMAL CAPCAITORS OF SINGLE-PHASE, TWO-PHASE AND COUPLED TWO-PHASE BUCK CONVERTERS

Frequency 20 MHz

Topology Single Buck VMC or

PCMC Two-Phase Buck PCMC

Coupled Two-Phase

Buck PCMC

COUT [nF] 51.2 51.2 51.2

CIN [nF] 50.85 50.85 50.85

50 100 150 200 250 300 350 400 450 500

0.65

0.70

0.75

0.80

0.85

CCM

DCM

Burst

IOUT [mA]

CCMCCM

DCM

Burst



page 58 of 72

4. Conclusions and future work

This report details Architecture Analysis and Evaluation of Power Swipe project system [1]. The main issues

and current state of design and the implementation of the system are presented.

The design of the HVDC-DC converter, presented in the first part of the report, is heavily constrained by the

electrical transients of the battery voltage. Although the standard battery voltage rating is from 6V to 16V, if no

protection is included between the battery and the main power supply, the HVDC-DC has to withstand an input

voltage of VIN = 40V and a negative input voltage of VIN = -14V due to the electrical surges of the battery.

The case of a 1:3 Switched capacitor converter between the battery and the main power supply is studied.

The Switched capacitor could be bypassed in normal operation and work when the input voltage is above 20V

so that the input voltage of the main power supply is VIN / 3.

The addition of an external commercial protection is also studied. Commercial ICs specific are available that

are specific for the electrical transients of car batteries and are automotive qualified.

Second part of the report detailed the Computer Aided Design Tool (CAD) designed for system level

optimization and analysis of a Low Voltage DC-DC Converter (LV-DCDC) of Power Swipe project system.

Three topologies (Single-Phase, Two-Phase and Coupled Two-Phase Buck converters) were selected as the

main candidates of LV-DCDC converter solution after preliminary analysis and they are implemented in the

tool. The CAD tool is implemented in Matlab 7.10.0.499 (R2010a) software and structured in to four main

functions, where two of them are creating and controlling Graphic User Interface (GUI), while the other two are

controlling optimization and analysis of one of the three implemented topologies and loading already optimized

solutions into the GUI.

The Graphic User Interface (GUI), presented in Chapter 3.1, used to define system specification and

constrains for the optimization of the selected topologies and to define the parameters of the topologies for

analysis. The tool, aside optimization, can analyze the converter presenting the waveforms of the voltages and

currents of interest in steady-state operation for typical, minimal and maximal load current as well to perform

breakdown of the converter losses at those points. Further, the tool can design the regulation and it can perform

dynamic tests of the selected topology such as load-steps and input voltage steps. Finally, the tool can estimate

minimal input and output capacitors which are satisfying both static and dynamic system constrains.

All the calculations are performed using presented models of the passives and semiconductors. In addition,

converter switching and linear models are developed for both open-loop as well for closed-loop system. The

models are developed in cooperation with manufactories or based on the simulations provided by them. Aldo

incomplete, these models provide initial insight on the system behavior and the future work will cover

improvement and validation of the models.

Further, the algorithms are presented followed by the optimization results obtained for all three topologies

operating at 10 and 20 MHz. For both switching frequencies, Coupled Two-Phase Buck presents the best

performance, but the obtained results need to be taken with precaution since the model of the coupled inductors

has not been verified and the performance of the converter is highly dependent on the magnetizing inductance.

The optimal solution, due to the efficiency and the size of the components is Single-Phase Buck converter

operating at 20 MHz. The estimated efficiency at typical load current is verified using Cadence software. In

addition, analyzing the breakdown of the losses, major losses components are identified and it is demonstrated

that the distribution of the losses are equally distributed between passives, PMOS and NMOS. The efficiency

dependence on the load current of the optimal design has been presented and it has been shown that in the

middle load current region, the system has relatively constant efficiency covering the typical load condition.

Furthermore, for the light-load operating condition, burst operating mode presents itself as optimal solution.

Finally, minimal capacitors are presented for all three topologies operating at 20 MHz. Since the dynamic tests

are not stressful for the system, as well as the static constrains, minimal capacitances are around 50 nF which

represents the CAD tool internal constrain.

Future work will be focused on the improvement of the models, especially the semiconductor and inductor

models. The semiconductor models will be developed so that coupling effect between high-side and low side

MOSFET will be included, as well optimal dead-time controller. The current range as well the width range will

be extended. Regarding the inductor models, the models will be implemented including the magnetic losses and

better estimation of the conduction losses based on the geometry.



page 59 of 72

5. References

[1] http://www.powerswipe.eu

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Electron., vol. 20, no. 3, pp. 639–649, May 2005.

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Int. Symp. Circuits Syst., Greece, May 2006, pp. 245–248.

[5] F. C. Lee and Q. Li, “High-Frequency Integrated Point-of-Load Converters: Overview”, IEEE Trans. Power Electron., vol. 28, no. 9, pp. 4127–4136, Sep. 2013.

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[13] T. O’Donnell, N. Wang, R. Meere, F. Rhen, S. Roy, D. O’Sullivan, and C. O’Mathuna, “Microfabricated inductors for 20 MHz Dc-

Dc converters,” in Proc. IEEE Appl. Power Electron. Conf. Expo., 2008, pp. 689–693.

[14] F. Roozeboom, A. L. A. M. Kemmeren, J. F. C. Verhoeven, F. C. van den Heuvel, J. Klootwijk, H. Kretschman, T. Fric, E. C. E. van

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integration towards a Si-based system-in-package concept,” Thin Solid Films, vol. 504, pp. 391–396, May 2006.

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36th Power Electron. Spec. Conf., Recife, Brasil, Jun. 16, 2005, pp. 1773–1779.

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[17] J. Hannon, D. O’Sullivan, R. Foley, J. Griffiths, K.G. McCarthy, and M.G. Egan, “Design and optimization of a high current, high

frequency monolithic buck converter,” in Proc. 23rd Annu. IEEE Applied Power Electronics Conf. Expo., Austin, TX, Feb. 24–28, 2008, pp. 1472–1476.

[18] T. Meade, D. O’Sullivan, R. Foley, C. Achimescu, M. Egan, and P. McCloskey, “Parasitic inductance effect on switching losses for a

high frequency Dc-Dc converter,” in Proc. 23rd Annual IEEE Applied Power Electronics Conf. Expo., Austin, TX, Feb. 24–28, 2008, pp. 3–9.

[19] J. Hannon, R. Foley, J. Griffiths, D. O’Sullivan, K. G. McCarthy, and M. G. Egan, “A 20 MHz 200–500 mA monolithic buck

converter for RF applications,” in Proc. 24th Annu. IEEE Applied Power Electron. Conf. Expo., Washington, D.C., Feb. 15–19, 2009, pp. 503–508.

[20] D. Díaz, M. Vasić, O. García, J.A. Oliver, P. Alou, J.A. Cobos, “Hybrid behavioral-analytical loss model for a high frequency and

low load DC-DC buck converter,” in Proc. Energy Conversion Congress and Exposition (ECCE), 2012 IEEE, Sept., 2012, pp. 4288 - 4294.

[21] http://www.infineon.com/austria

[22] http://www.tyndall.ie

[23] http://www.ipdia.com

[24] R. W. Ericson and D. Maksimović, “Fundamentals of Power Electronic”, second edition, University of Colorado, Boulder, Colorado.

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HFPC’96 Conf, 1996, pp. 19–23.

[27] M. Del Viejo, P. Alou, J. Oliver, O. Garcia, and J. Cobos, “v2ic control: A novel control technique with very fast response under load and voltage steps,” in Applied Power Electronics Conference and Exposition (APEC), 2011 Twenty-Sixth Annual IEEE, 2011, pp.

231–237.

[28] R. Redl, B. Erisman, and Z. Zansky, “Optimizing the load transient response of the buck converter,” in Applied Power Electronics Conference and Exposition, 1998. APEC ’98. Conference Proceedings 1998., Thirteenth Annual, vol. 1, 1998, pp. 170–176 vol.1.

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[32] "Maxim Integrated MAX1627 Load-Dump/Reverse Voltage Protection Circuits," [Online]. Available:

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page 61 of 72

APPENDIX I

Global variables of the system:

variable type description

Specification struct system specification

.f double operating frequency in [Hz]

.NumbHarmonics double number of harmonics

.Vin.DC double nominal input voltage in [V]

.Vin.StaticRipple_pp double input voltage static ripple in [%]

.Vin.DynamicRipple_pp double input voltage dynamic ripple in [%]

.Vout.DC double nominal output voltage in [V]

.Vout.StaticRipple_pp double output voltage static ripple in [%]

.Vout.DynamicRipple_pp double output voltage dynamic ripple in [%]

.Iout.typ double typical load current in [A]

.Iout.max double maximal load current in [A]

.Iout.min double minimal load current in [A]

.ni.typ double efficiency of the system at typical current in [%]

.ni.max double efficiency of the system at maximal current in [%]

.ni.min double efficiency of the system at minimal current in [%]

.Step.LoadStep double vector amplitude of load steps in [A]

.Step.LoadSettlTime double vector settling time of load steps in [s]

.Step.VinStep double vector amplitude of Input voltage steps in [V]

.Step.VinSettlTime double vector settling time of Input voltage steps in [s]

.L.Lout double nominal inductance of the output inductor or

leakage inductance in [H]

.L.Lm double magnetizing inductance of coupled inductors in [H]

.L.max double maximal inductance used in optimizations in [H]

.L.Lprec double precision of inductance in [H]

.L.strp_thickness double the thickness of the strips of magnetics in [m]

.L.dILmax double maximal inductor current ripple in [A]

.L.Area.maxA double available for magnetics area: dimension a in [m]

.L.Area.maxB double available for magnetics area: dimension b in [m]

.L.Area.max double available for magnetics area in [m2]

.L.paraz.R double parasitic resistance of inductor in [Ohm]

.L.paraz.L double parasitic inductance of inductor in [H]

.C.Cout double nominal output capacitance in [F]

.C.Cin double nominal input capacitance in [F]

.C.precision double precision of capacitance in [F]

.C.density double density of capacitance in [F/m2]

.C.Area.maxA double available for capacitors area: dimension a in [m]

.C.Area.maxB double available for capacitors area: dimension b in [m]

.C.Area.max double available for capacitors area in [m2]

.C.Cin_paraz.R double parasitic resistance of input capacitor in [Ohm]

.C.Cin_paraz.L double parasitic inductance of input capacitor in [H]

.C.Cout_paraz.R double parasitic resistance of output capacitor in [Ohm]

.C.Cout_paraz.L double parasitic inductance of output capacitor in [H]

.MOSFETS.P.w double PMOS nominal width in [m]

.MOSFETS.P.wmax double PMOS maximal width in [m]

.MOSFETS.P.wmin double PMOS minimal width in [m]

.MOSFETS.P.Vgs double PMOS driving voltage in [V]

.MOSFETS.P.Ig double PMOS gate current in [A]

.MOSFETS.N.w double NMOS nominal width in [m]



page 62 of 72

.MOSFETS.N.wmax double NMOS maximal width in [m]

.MOSFETS.N.wmin double NMOS minimal width in [m]

.MOSFETS.N.Vgs double NMOS driving voltage in [V]

.MOSFETS.N.Ig double NMOS gate current in [A]

.MOSFETS.dead_time_pmos_to_nmos double dead time of the switching transient from PMOS to

NMOS in [s]

.MOSFETS.dead_time_nmos_to_pmos double dead time of the switching transient from NMOS to

PMOS in [s]

system struct state-space model of a converter - does not have all

the fields, depends on the topology

.x char vector state vector of the converter system

.u char vector input vector of the converter system

.y char vector output vector of the converter system

.xy char vector extended state vector of the converter system

composed of both state and input vectors

.A1 double matrix state matrix during the "1" state


.Ax double matrix state matrix during the "x" state

.B1 double matrix input matrix during the "1" state


.Bx double matrix input matrix during the "x" state

.C double matrix output matrix

.D double matrix feedthrough matrix

.Ay1 double matrix extended state matrix during the "1" state


.Ayx double matrix extended state matrix during the "x" state

.Cy double matrix extended output matrix



.A1x double matrix state matrix during the "1x" state



.A0x double matrix state matrix during the "0x" state

.Ax1 double matrix state matrix during the "x1" state

.Ax0 double matrix state matrix during the "x0" state

.Axx double matrix state matrix during the "xx" state



.B1x double matrix input matrix during the "1x" state



.B0x double matrix input matrix during the "0x" state

.Bx1 double matrix input matrix during the "x1" state

.Bx0 double matrix input matrix during the "x0" state

.Bxx double matrix input matrix during the "xx" state



.Ay1x double matrix extended state matrix during the "1x" state



.Ay0x double matrix extended state matrix during the "0x" state

.Ayx1 double matrix extended state matrix during the "x1" state

.Ayx0 double matrix extended state matrix during the "x0" state



page 63 of 72

.Ayxx double matrix extended state matrix during the "xx" state

m cell status report for GUI

mcnt double pointer on a next cell in m

Static_sweep double Analysis status flag for static behavior test: Iout

sweep

Static_typ double Analysis status flag for static behavior test: typical

load

Static_max double Analysis status flag for static behavior test:

maximal load

Static_min double Analysis status flag for static behavior test:

minimal load

Dynamic_reg double Analysis status flag for dynamic behavior test:

regulator

Dynamic_load double Analysis status flag for dynamic behavior test: load

steps

Dynamic_vin double Analysis status flag for dynamic behavior test:

input voltage steps

MinCap double Minimal Capacitor calculations status flag

C12n double Capacitor model parameter: series capacitance of

12 nF basic cell in [F]

Cp12n double Capacitor model parameter: Parallel capacitance of

12 nF basic cell in [F]

C3n9 double Capacitor model parameter: series capacitance of

3.9 nF basic cell in [F]

Cp3n9 double Capacitor model parameter: Parallel capacitance of


C1n6 double Capacitor model parameter: series capacitance of


Cp1n6 double Capacitor model parameter: Parallel capacitance of


esr12n double Capacitor model parameter: series resistance of 12

nF basic cell in [Ohm]

esr3n9 double Capacitor model parameter: series resistance of 3.9


esr1n6 double Capacitor model parameter: series resistance of 1.6


esl12n double Capacitor model parameter: series inductance of 12

nF basic cell in [H]

esl3n9 double Capacitor model parameter: series inductance of

3.9 nF basic cell in [H]

esl1n6 double Capacitor model parameter: series inductance of

1.6 nF basic cell in [H]

fsw double operating frequency in [Hz]

Nharm double number of harmonics

Vin double nominal input voltage in [V]

Vout double nominal output voltage in [V]

Vref double output voltage reference in [V]

Iout double load current in [A]

Cout double equivalent capacitance of the output capacitor in

[F]

C_ESR_out double equivalent series resistance of the output capacitor

in [Ohm]

C_ESL_out double equivalent series inductance of the output capacitor

in [H]

RparCout double parasitic series resistance of the output capacitor in

[Ohm]

LparCout double parasitic series inductance of the output capacitor in

[H]



page 64 of 72

Cin double equivalent capacitance of the input capacitor in [F]

C_ESR_in double equivalent series resistance of the input capacitor in

[Ohm]

C_ESL_in double equivalent series inductance of the input capacitor

in [H]

RparCin double parasitic series resistance of the input capacitor in

[Ohm]

LparCin double parasitic series inductance of the input capacitor in

[H]

Lout double nominal inductance of the of the output inductor in

[H]

L_DCR double series DC resistance of the output inductor in

[Ohm]

L_ACr double vector series AC resistance of the output inductor in

[Ohm]

LparL double equivalent series resistance of the inductor in

[Ohm]

RparL double equivalent series inductance of the inductor in [H]

dead_time_pmos_to_nmos double dead time of the switching transient from PMOS to

NMOS in [s]

dead_time_nmos_to_pmos double dead time of the switching transient from NMOS to

PMOS in [s]

Vgs_p double PMOS driving voltage in [V]

Vgs_n double NMOS driving voltage in [V]

Rdc_pmos double PMOS on resistance in [Ohm]

Rdc_nmos double PMOS on resistance in [Ohm]

Rload double parallel parasitic load resistance in [Ohm]

L double total equivalent inductance, composed of nominal

and parasitic inductor inductance in [H]

R1 double total equivalent resistance of the high side path,

composed of PMOS on resistance, parasitic and DC

resistance of the inductor in [Ohm]

R0 double total equivalent resistance of the low side path,

composed of NMOS on resistance, parasitic and

DC resistance of the inductor in [Ohm]

Rc double total equivalent output capacitor resistance,

composed of C_ESR_out and RparCout in [Ohm]

Lc double total equivalent output capacitor inductance

composed of C_ESL_out andLparCout in [H]

Output of the Optimization functions

variable type description

sol struct optimal design of a Converter

.Cout.C double output capacitor: capacitance in [F]

.Cout.esr double output capacitor: series resistance in [Ohm]

.Cout.esl double output capacitor: series inductance in [H]

.Cout.N12nN3n9N1n6 double

vector

output capacitor: numbers of each basic cell

.Cout.ripplemax double output capacitor: maximal voltage ripple in [V]

.Cin.C double input capacitor: capacitance in [F]

.Cin.esr double input capacitor: series resistance in [Ohm]

.Cin.esl double input capacitor: series inductance in [H]

.Cin.N12nN3n9N1n6 double

vector

input capacitor: numbers of each basic cell



page 65 of 72

.Cin.ripplemax double input capacitor: maximal voltage ripple in [V]

.MOSFETS.P.w double PMOSFET: width of the channel in [m]

.MOSFETS.P.Rdc double PMOSFET: on-resistance of the channel in [Ohm]

.MOSFETS.N.w double NMOSFET: width of the channel in [m]

.MOSFETS.N.Rdc double NMOSFET: on-resistance of the channel in [Ohm]

.Lout.L double inductor: inductance in [H]

.Lout.Lm double inductor: magnetizing inductance in [H] - exists only in

optimization of Coupled Two-phase Buck

.Lout.RDC double inductor: DC resistance in [Ohm]

.Lout.RAC double

vector

inductor: AC resistances for each harmonic in [Ohm]

.Lout.ripplemax double inductor: maximal current ripple in [A]

.system.typ.CCM.ni double typical load: CCM efficiency

.system.typ.CCM.Losses double typical load: CCM Losses in [W]

.system.typ.DCM.ni double typical load: DCM efficiency - does not exist in optimization of

Coupled Two-phase Buck

.system.typ.DCM.Losses double typical load: DCM Losses in [W] - does not exist in optimization of


.system.typ.BURST.ni double typical load: BURST mode efficiency - does not exist in


.system.typ.BURST.Losses double typical load: BURST mode Losses in [W] - does not exist in


.system.max.CCM.ni double maximal load: CCM efficiency

.system.max.CCM.Losses double maximal load: CCM Losses in [W]

.system.max.DCM.ni double maximal load: DCM efficiency - does not exist in optimization of


.system.max.DCM.Losses double maximal load: DCM Losses in [W] - does not exist in optimization

of Coupled Two-phase Buck

.system.max.BURST.ni double maximal load: BURST mode efficiency - does not exist in


.system.max.BURST.Losses double maximal load: BURST mode Losses in [W] - does not exist in


.system.min.CCM.ni double minimal load: CCM efficiency

.system.min.CCM.Losses double minimal load: CCM Losses in [W]

.system.min.DCM.ni double minimal load: DCM efficiency - does not exist in optimization of


.system.min.DCM.Losses double minimal load: DCM Losses in [W] - does not exist in optimization

of Coupled Two-phase Buck

.system.min.BURST.ni double minimal load: BURST mode efficiency - does not exist in


.system.min.BURST.Losses double minimal load: BURST mode Losses in [W] - does not exist in




page 66 of 72

APPENDIX II

Basic Equations

parCC

parCC

parLOUT

parLDCLNMOS

parLDCLPMOS

RESRR

LESLL

LLL

RRRR

RRRR

0

1

Single-Phase Buck Converter: Open loop state-space models

T

CLC iivx

T

OUTIN IVu

T

LOUT ivy

C

CLoad

C

Load

C

LoadLoad

OUT

L

RR

L

R

L

L

R

L

RR

C

A

1

0

100

11

C

CLoad

C

Load

C

LoadLoad

OUT

L

RR

L

R

L

L

R

L

RR

C

A

1

0

100

00

C

CLoad

C

Load

C

OUT

X

L

RR

L

R

L

C

A1

000

100

C

Load

Load

L

RL

R

LB

0

100

1



page 67 of 72

C

Load

Load

L

RL

RB

0

0

00

0

C

Load

X

L

RB

0

00

00

010

0 LoadLoad RRC

00

0 LoadRE

Two-Phase Buck Converter: Open loop state-space models

T

CLLC iiivx 21

T

OUTIN IVu

T

LLOUT iivy 21

C

CLoad

C

Load

C

Load

C

LoadLoadLoad

LoadLoadLoad

OUT

L

RR

L

R

L

R

L

L

R

L

RR

L

RL

R

L

R

L

RR

C

A

1

0

0

1000

1

1

11

C

CLoad

C

Load

C

Load

C

LoadLoadLoad

LoadLoadLoad

OUT

L

RR

L

R

L

R

L

L

R

L

RR

L

RL

R

L

R

L

RR

C

A

1

0

0

1000

0

1

10



page 68 of 72

C

CLoad

C

Load

C

Load

C

LoadLoadLoad

LoadLoadLoad

OUT

X

L

RR

L

R

L

R

L

L

R

L

RR

L

RL

R

L

R

L

RR

C

A

1

0

0

1000

1

1

1

C

CLoad

C

Load

C

Load

C

LoadLoadLoad

LoadLoadLoad

OUT

L

RR

L

R

L

R

L

L

R

L

RR

L

RL

R

L

R

L

RR

C

A

1

0

0

1000

1

0

01

C

CLoad

C

Load

C

Load

C

LoadLoadLoad

LoadLoadLoad

OUT

L

RR

L

R

L

R

L

L

R

L

RR

L

RL

R

L

R

L

RR

C

A

1

0

0

1000

0

0

00

C

CLoad

C

Load

C

Load

C

LoadLoadLoad

OUT

X

L

RR

L

R

L

R

L

L

R

L

R

L

RR

C

A

10000

0

1000

0

0

C

CLoad

C

Load

C

Load

C

LoadLoadLoad

OUT

X

L

RR

L

R

L

R

L

L

R

L

RR

L

R

C

A

1

0

0000

1000

11

C

CLoad

C

Load

C

Load

C

LoadLoadLoad

OUT

X

L

RR

L

R

L

R

L

L

R

L

RR

L

R

C

A

1

0

0000

1000

00



page 69 of 72

C

CLoad

C

Load

C

Load

C

OUT

XX

L

RR

L

R

L

R

L

C

A

10000

0000

1000

C

Load

Load

Load

L

RL

R

L

L

R

L

B

0

1

100

11

C

Load

Load

Load

L

RL

RL

R

L

B

0

0

100

10

C

Load

Load

X

L

R

L

R

LB

0

00

100

1

C

Load

Load

Load

L

RL

R

L

L

R

B

0

1

0

00

01

C

Load

Load

Load

L

RL

RL

R

B

0

0

0

00

00

C

Load

Load

X

L

R

L

R

B

0

00

0

00

0



page 70 of 72

C

Load

Load

X

L

RL

R

LB

0

100

00

1

C

Load

Load

X

L

RL

RB

0

0

00

00

0

C

Load

XX

L

R

B

0

00

00

00

0100

0010

0 LoadLoadLoad RRR

C

00

00

0 LoadR

E

Coupled Two-Phase Buck Converter: Open loop state-space models

T

CLLmC iiivx 2

T

OUTIN IVu

T

LmLLOUT iiivy 21

C

CLoad

C

Load

C

Load

C

LoadLoadm

mLoad

m

OUT

L

RR

L

R

L

R

L

L

R

L

RR

L

LL

LRR

LL

R

C

A

21

220

002

0

1000

1

1

1

11



page 71 of 72

C

CLoad

C

Load

C

Load

C

Loadm

mLoad

m

mLoad

mm

OUT

L

RR

L

R

L

R

L

L

R

L

LL

LRRRR

L

LL

LRR

LL

RR

LL

R

C

A

21

2

)(2

20

022

0

1000

010

1

011

10

C

CLoad

C

Load

C

Load

C

Loadm

mLoad

m

mLoad

mm

OUT

L

RR

L

R

L

R

L

L

R

L

LL

LRRRR

L

LL

LRR

LL

RR

LL

R

C

A

21

2

)(2

20

022

0

1000

101

0

100

01

C

CLoad

C

Load

C

Load

C

LoadLoadm

mLoad

m

OUT

L

RR

L

R

L

R

L

L

R

L

RR

L

LL

LRR

LL

R

C

A

21

220

002

0

1000

0

0

0

00

C

Load

Load

L

RL

R

LB

0

100

00

11

C

Load

Load

m

m

m

L

R

L

R

LLL

L

LL

B

0

)2(

02

100

10



page 72 of 72

C

Load

Load

m

m

m

L

R

L

R

LLL

LL

LL

B

0

)2(

02

100

01

C

Load

Load

L

RL

RB

0

0

00

00

00

0010

0100

0110

20 LoadLoadLoad RRR

C

00

00

00

0 LoadR

E

Documents

Architecture Analysis and Evaluation - CORDIS...“Optimization and Analysis Tool”, September 2013 PowerSWIPE (Grant agreement 318529) page 4 of 72 1. Introduction This report details