AR0123 Connectivity and Multi-Sheet Design

8/13/2019 AR0123 Connectivity and Multi-Sheet Design

1/16

Legacy documentation

refer to the Altium Wiki for current information

Connectivity and Multi-Sheet Design

Summary

Article

AR0123 (v1.8) July 30, 2008

This article discusses the structural and connective considerations involved in multi-

sheet design, then describes the different browsing tools that let you verify net

connectivity across source documents.

Engineers turn to multi-sheet design for various reasons, the primary one being project size; some projects are too large or

complex to fit on a single sheet. Even when the design is not particularly complicated, there can be advantages in organizing

the project across multiple sheets. For example, the design may include various modular elements. Maintaining these modules

as individual documents would allow several engineers to work on a project at the same time. Another reason is that this

method allows you to use small format printing, such as laser printers.

There are two decisions to make for each multi-sheet project - the structural relationship of the sheets and the method

employed for electrical connectivity between circuitry on those sheets. Your choices will vary according to the size and type of

each project and your personal preferences.

Defining Sheet Structure

While the project file links the various source documents into a single project, the document-to-document and net connective

relationships are defined by information in the documents themselves. A multi-sheet design project is arranged as a hierarchical

structure of logical blocks, where each block can be either a schematic sheet or a HDL file (VHDL or Verilog). At the head of this

structure is a single master schematic sheet, more commonly referred to as the projects top sheet.

The sheet structure itself is formed through the use of a special symbol called a sheet symbol1. Each of the source documents

that constitute the design are represented on the top sheet by a sheet symbol. The Filename property of each sheet symbol

references the schematic sub-sheet (or HDL file) that it graphically represents. In turn, a schematic sub-sheet can also contain

further sheet symbols referencing lower schematic sheets or HDL files. In this way you can define a structural hierarchy of

source documents that can be as simple or complex as your needs require.

When your multi-sheet project is compiled, the logical relationship between the modular blocks of the design is realized and a

structural framework is created. This is a tree structure, beginning with the schematic top sheet and branching down to include

all other schematic sub-sheets and HDL files at one level or another.

Figure 1 shows two examples of compiled design hierarchy. On the left, the structural hierarchy for a compiled PCB design

project (*.PrjPcb). On the right, the structural hierarchy for a compiled FPGA design project (*.PrjFpg).

1

Previous versions of Protel incorporated a Schematic Editor which allowed schematic sub-sheets to be represented by components as analternative to sheet symbols. When you open a legacy database in Altium Designer, any such components will automatically convert into sheet

symbols with appropriately labeled sheet entries.

AR0123 (v1.8) July 30, 2008 1


2/16


refer to the Altium Wiki for current informationConnectivity and Multi-Sheet Design

Figure 1. Compiled multi-sheet design projects showing the hierarchical relationship between source documents.

Building a Hierarchical Structure It is important to remember that forhierarchical designs a project can

contain only one top sheet; allother source documents must be

referenced by sheet symbols. No

sheet symbol may reference the

sheet its on, or any sheet higher

up the ladder, as this will create an

irresolvable loop in the structure.

The design capture environment provides a range of features that allow you to build your multi-

document, hierarchical structure quickly and efficiently. The exact features you choose to use

depend on your personal design methodology top-down or bottom-up.

Top-Down Design

The following commands are available that allow you to build the hierarchy of your design in a

top-down fashion:

Create sheet from symbol use this schematic editor command to create a sheet below the nominated sheet symbol.

Matching Ports will be added to the sub-sheet, ready to wire.

Create VHDL fi le fromsymbol use this schematic editor command to create a shell VHDL file, with an entity declared that

includes port definitions to match the sheet entries in the nominated symbol.

Create Verilog file from symbol use this schematic editor command to create a Verilog file, with a module declared that

includes port definitions to match the sheet entries in the nominated symbol.

Push part to sheet use this schematic editor command to push a placed part onto a new schematic sub-sheet, replacing the

original part on the parent sheet with a sheet symbol pointing to the new sub-sheet. Matching ports will be added and wired to

the part on the sub-sheet. Right-click on a component to access this command.

Bottom-Up Design

The following commands are available that allow you to build the hierarchy of your design in a bottom-up fashion:

Create symbol from sheet or HDL use this schematic editor command to create a symbol from the nominated schematic

sheet, VHDL file or Verilog file. Make the sheet that is to include the sheet symbol the active document before launching this

command.

Convert part to sheet symbol use this schematic editor command to convert a chosen part into a sheet symbol. The

symbol's Designator field will initially be set to the part's designator, with the Filename field set to the part's comment text.

Change the filename to point to the required sub-sheet; change the sheet entries in accordance with the ports defined on that

sub-sheet. Right-click on a component to access this command.

Mixed Schematic/HDL Document Hierarchy

When creating the design hierarchy, you can quite easily use a sheet symbol on a parent schematic sheet to reference a

schematic sub-sheet below. This can be extended when capturing the design using a mixture of schematic sheets and HDL

code. The VHDL or Verilog sub-documents are referenced in the same way as schematic sub-sheets, by specifying the sub-

document filename in the sheet symbol that represents it.

When referencing a VHDL sub-document, the connectivity is from the sheet symbol to an entity declaration in the VHDL file. To

reference an entity with a name that is different from the VHDL filename, include the VHDLEnt i t yparameter in the sheet

symbol, whose value is the name of the Entity declared in the VHDL file.

The process is similar when referencing a Verilog sub-document, where the connectivity is from the sheet symbol to a module

declaration in the Verilog file. To reference a module with a name that is different from the Verilog filename, include the

Ver i l ogModul eparameter in the sheet symbol, whose value is the name of the Module declared in the Verilog file.

2 AR0123 (v1.8) July 30, 2008


3/16



Figure 2 illustrates an example of this mixed hierarchy, whereby the same sheet symbol has been used to reference a

schematic sub-sheet in one instance of a design and an entity in a VHDL sub-document in another. In both cases, the sub-

document implements the same circuitry (a BCD Counter).

Figure 2. Document hierarchy is created by placing sheet symbols to represent the document below

Maintaining Hierarchy

Once you have defined the hierarchical structure of your multi-sheet design, you need to be able to maintain it. Altium Designer

provides features that help you do just that.

Synchronizing Ports and Sheet Entries

A sheet symbol is 'synchronized' with its referenced child sheet below if all of its sheet entries match the corresponding ports on

the sub-sheet both by name and by IO Type. Use the Synchronize Ports to Sheet Entries dialog (Figure 3) to maintain the

sheet symbol to matching sub-sheet links (select Synchronize Sheet Entries and Ports from the Design menu).

Figure 3. Ensuring the synchronization of sheet entries and ports

For detailed information on this synchronization process, refer to the Synchronizing Sheet Entries and Portssection of the

Sheet Symbol topic. This topic can be quickly accessed by pressing F1while the cursor is over a placed sheet symbol.

Renaming a Sheet Symbol's Child Sheet

During a design you may need to change the name of a schematic sub-sheet, for example you may have changed the circuitry

on the sheet and require a different name to better reflect the sheet's functionality. Rather than rename the sheet and then

manually change the reference for each sheet symbol that references the sheet, the Rename Child Sheetcommand is

provided (accessible from the Design menu). With this command you can:

Rename the child sheet and update all affected sheet symbols in the current design project

Rename the child sheet and update all affected sheet symbols in the current design workspace (*. DsnWr k)

Create a renamed copy of the child sheet and update the current sheet symbol to point to it.

For detailed information on this renaming process, refer to the Renaming a Sheet Symbols' Child Sheetsection of the SheetSymbol topic. This topic can be accessed by pressing F1while the cursor is over a placed sheet symbol.

AR0123 (v1.8) July 30, 2008 3


4/16



Supporting Multi-Channel DesignSupporting Multi-Channel Design

The environment includes features specifically to support projects with repetitive circuitry as well as the singular one sheet

symbol = one sub-sheet representation, you can also create a structure where the same sub-sheet is referenced many times.

This is known as multi-channel design.

The environment includes features specifically to support projects with repetitive circuitry as well as the singular one sheet

symbol = one sub-sheet representation, you can also create a structure where the same sub-sheet is referenced many times.

This is known as multi-channel design.

There are 2 approaches to multi-channel design; by referencing the same sub-sheet from multiple sheet symbols, or using one

sheet symbol with the Repeatkeyword. When the design is compiled, any repeated sections (or channels) are automaticallyinstantiated the required number of times. The advantage of multi-channel design is that it allows you to maintain a single copy

of the source channel, even after the design has moved to implementation in the FPGA or on the PCB.

There are 2 approaches to multi-channel design; by referencing the same sub-sheet from multiple sheet symbols, or using one

sheet symbol with the Repeatkeyword. When the design is compiled, any repeated sections (or channels) are automaticallyinstantiated the required number of times. The advantage of multi-channel design is that it allows you to maintain a single copy

of the source channel, even after the design has moved to implementation in the FPGA or on the PCB.

The syntax used involves the use of the Repeatkeyword in the sheet symbol's

Designatorfield and takes the form:

The syntax used involves the use of the Repeatkeyword in the sheet symbol's

Designatorfield and takes the form:

Figure 4. Multi-channelinstantiation using the Repeat

keyword

Repeat ( Sheet Symbol Desi gnator , Fi r st I nst ance, Last I nst ance) ,

where Sheet Symbol Desi gnat or is the base name for the sheet symbol and

Fi r st I nst anceand Last I nstancetogether define the number of channels to be

instantiated. It is important to remember that the Fi r st I nst anceparameter needs to

start at a value equal to or greater than 1. Figure 4 illustrates the use of the Repeat

keyword to instantiate 8 input channels for an audio mixer.

where

Repeat ( Sheet Symbol Desi gnator , Fi r st I nst ance, Last I nst ance) ,

Sheet Symbol Desi gnat or is the base name for the sheet symbol and

Fi r st I nst anceand Last I nstancetogether define the number of channels to be

instantiated. It is important to remember that the Fi r st I nst anceparameter needs to

start at a value equal to or greater than 1. Figure 4 illustrates the use of the Repeat

keyword to instantiate 8 input channels for an audio mixer.

When the project is built, the Compiler instantiates the channel the required number of

times as it builds the internal compiled model, using a chosen annotation scheme to

uniquely identify each component in each channel. The channel sub-sheet is not

duplicated. Instead, once compiled, a separate tab appears at the bottom of the sub-sheet

document in the main design window, for each channel on that sheet, an example of

which is shown in Figure 5.

When the project is built, the Compiler instantiates the channel the required number of

times as it builds the internal compiled model, using a chosen annotation scheme to

uniquely identify each component in each channel. The channel sub-sheet is not

duplicated. Instead, once compiled, a separate tab appears at the bottom of the sub-sheet

document in the main design window, for each channel on that sheet, an example of

which is shown in Figure 5.

Figure 5. Example of instantiated channels on a single child schematic sheet

The article Multi-Channel Design Conceptsgives more information on how to capture a design with repeated sections.

Refer to the tutorial, Creating a Multi-channel Designfor step-by-step instructions on building a multi-channel design.

Increasing Sheet Space at the Lower Level

Multiple sub-sheets may be referenced by a single sheet symbol. Separate each filename by a semi-colon, in the Filename

field. With the effective use of off-sheet connectors, placed on the sub-sheets, you can effectively spread a section of your

design over multiple sheets, treated as though they were one giant (flat) sheet. Note however, that use of off-sheet connectors

is only possible for sheets referenced by the same sheet symbol. See Example 5 Off-sheet Connectorslater in this document

for more detailed information.

4 AR0123 (v1.8) July 30, 2008
http://ar0112%20multi-channel%20design%20concepts.pdf/http://tu0112%20creating%20a%20multi-channel%20design.pdf/http://tu0112%20creating%20a%20multi-channel%20design.pdf/http://ar0112%20multi-channel%20design%20concepts.pdf/


5/16



Instrumentation.SchDoc Protection.SchDoc

Figure 6. Example of multiple sub-sheets referenced from a single sheet symbol

Defining Net Connectivity

The only way to pass signals between sheets in a project is with net identifiers. These are objects that will make logical

connections with one another, rather than physical connections (wires). Of course, net identifiers can be used locally within a

single sheet, as shown below.

These pictures show how wires can be replaced by net labels, ports and power ports, respectively. These are known as net

identifiers, and will be discussed in detail in the next section.

The pictures below illustrate a common misconception: that net identifiers of different types (such as net labels and ports) will

connect logically if their names match. In fact, the opposite is true: different kinds of net identifiers may have distinct names, but

still be wired together to form a single net.

These diagrams are all concerned with net identifiers replacing physical connections within a single sheet. What they do not

show is that net identifiers give you the freedom to transfer nets between sheets in a multi-sheet project. How this happens

depends upon the net identifiers used in your design, and the scope setting.

Net Identifiers

The most basic net identifiers are net labels. Their primary function is to alleviate the traffic of wire connections in a sheet.

While there are ways and circumstances in which net labels can be made to correspond between sheets, you should generally

consider them for local (in-sheet) connections.

Ports, like net labels, will always connect locally to matching ports on the same document. Unlike net labels, ports are

specifically designed for inter-sheet connections. This can happen horizontally or vertically. Horizontally is the broadest option,

AR0123 (v1.8) July 30, 2008 5


6/16


7/16



If your schematic project contains ports, but not a single sheet entry, then the automatic detection chooses a scope of ports

global. This means that ports will connect horizontally throughout the project, disregarding the multi-sheet structure and

identifying all matching ports within the same net. Net labels will continue to make local connections only.

Finally, if your schematic project is devoid of both sheet entries and ports, then the automatic detection will elevate net labels to

global status.

Off-sheet connectors, power ports and special hidden pins will always operate in the same way, regardless of the NetIdentification Scope.

Flat vs Hierarchical Connectivity

In terms of document structure, all multi-sheet design projects are organized hierarchically, even if the hierarchy is limited to

only two levels (i.e. a top sheet containing all sheet symbols that reference the sub-sheets on the level below). In terms of

connectivity, a design can follow either a flat or hierarchical structure. The base difference between the two is that hierarchical

designs relay signals between sheets according to the sheet structure you have created, while flat designs take no

consideration of the structural arrangement of sheets.

It is important to note that when designing an FPGA project, the connective model employed must be hierarchical.

Flat Designs Without a Top Sheet

If your design is not hierarchical i.e. the sub schematic sheets are all on the same level, with no sheet symbols referencingfurther sheets below the design is a flat one. In this case, you are not required to have a top sheet, containing only sheet

symbols to reference those sheets below. The requirement for a top sheet dates back to when there was no project file, without

a project file the software had to rely on the sheet symbols on the top sheet to determine which sheets were in the project. To

test such a project without a top sheet, right-click on its filename in the Projects panel and choose Remove from Projectfrom

the context menu.

Flat design projects that already include the top sheet will compile correctly, but Altium Designer gives you the choice to build

your project without a top sheet, should you wish.

Connectivity Examples

The following four illustrations will show how the detected or selected scope will affect the connectivity of net labels and ports in

the same inter-sheet structure. The fifth shows how off-sheet connectors work.

Example 1 Hierarchical

This schematic project will automatically be detected for hierarchical scope, due to the presence of sheet entries within the

sheet symbols on the parent sheet. The net labels C1 and C2 on each sub-sheet will not connect to matching net labels on the

other sub-sheet, but remain within the confines of their local sheets. The ports in this example have different names, but even if

they had matching names, they would not make horizontal connections with one another between sub-sheets when the

hierarchical scope was in effect. Instead, ports will only make trans-sheet connections vertically, up to the parent sheet. For this

to work, the port on the sub-sheet must find a matching sheet entry inside the corresponding sheet symbol. That connection

may then be wired to pins or other net identifiers from the sheet entry on the parent sheet.

AR0123 (v1.8) July 30, 2008 7


8/16



In this example, the sheet entries on the parent sheet are connected to one another (notice that their names do not match; this

is a physical connection, not a logical one). In a more highly-developed structural design, these signals could have been wired

to ports and matched to entries within another sheet symbol on a grand-parent sheet.

Example 2 Ports Global

The presence of ports in this design, along with the absence of any sheet entries, causes the scope to automatically change to

ports global. This essentially flattens the project as far as ports are concerned; they will make logical connections to all ports

with matching names anywhere in the project. Net labels do not share this same ability; they will remain local to individual

sheets.

As this design project is flat, the top-sheet could be removed from the project and the design would still compile correctly.

Remember, Altium Designer uses the project file to determine which sheets are in the design project.

Example 3 Net Labels Global

This project is entirely devoid of both sheet entries and ports. This is the only case in which net labels will automatically make

global connections in a multi-sheet design. These net labels will connect with all matching net labels in the project, regardless of

the structure.

Again, as this design project is flat, the top-sheet could be removed from the project and the design would still compile correctly.

8 AR0123 (v1.8) July 30, 2008


9/16



Example 4 Net Labels and Ports Global

This scope is not available through automatic detection, but has been continued in Altium Designer to provide support for legacy

designs. In it, both net labels and ports make global connections with matching net identifiers in a horizontal fashion. The only

way to achieve this kind of connectivity is to browse to the Optionstab of the Options for Projectdialog, and change the Net

Identifier Scopeto Gl obal ( Net l abel s and port s gl obal ) .

As this design project is flat, the top-sheet could again be removed from the project and the design would still compile correctly

(the project file itself holding the information about which source documents form the design).

Example 5 Off-sheet Connectors

In this example, the top sheet references four sub-sheets with only two sheet symbols. This is done by referencing multiple

schematic files in the sheet symbols Filenamefield, separated by a semicolon. Off sheet connectors will then create flat

connections between all sheets grouped within a single sheet symbol even if other sheets in the project are using vertical

connectivity.

The grouping of sheets has no effect on any net identifiers except for off-sheet connectors. It creates a haven within your design

that can accommodate flat connections but this will only occur between matching off-sheet connectors. Notice how these

connections are maintained within groups only. They do not cross into other groups, even if they contain off-sheet connectors

with matching names.

AR0123 (v1.8) July 30, 2008 9


10/16



Many designers may never use off-sheet connectors. They were introduced primarily as a means of importing designs

seamlessly from other design packages. You may, however, encounter situations where they come in handy. For example,

suppose you have a highly modular design, with each sheet representing a logical chunk of your design. The placement of your

sheet symbols will not just create the connectivity you desire, but it will let other engineers quickly understand the overall design.

Now imagine that the circuitry within one of these functional blocks overflows beyond what will fit in a single sheet. To fit it into a

hierarchy, you will need to replace any net labels that should be passed from sheet to sheet with ports, which will transfer them

up to matching sheet entries which must then be wired together. This is a laborious solution, not to mention the fact that youhave cluttered your design with two sheet symbols that have no logical difference, all because your sheet was a little too small.

The correct alternative is to replace the net labels that would normally create the connectivity across this portion of the design

with off-sheet connectors. Grouping multiple sheets will keep the block-diagram flow of your design consistent with the overall

logic of the project.

Using Buses

Many schematics contain buses, which symbolize grouped signals. They are conventionally drawn with a greater thickness than

wires, making them easy to identify. This graphical aspect of buses can be a useful tool in itself, but bused signals can also be

transferred between sheets, according to the general rules of connectivity described previously.

Figure 7. Example of graphical and logical buses used in a design

The example circuitry in Figure 6 above contains four buses: two graphical and two logical. Logical buses are attached to netidentifiers (net labels and/or ports) which use bus syntax. To understand bus syntax, consider one of the logical buses in this

example more closely:

These eight nodes are eligible for inclusion in a bus because they have net labels that share the same prefix, followed by a

numeric suffix. The logical bus is created by a net label with the syntax D[0..7], where D is the

shared prefix, and the numbers 0 and 7 mark the smallest and largest numbers in the suffix. Any

non-negative numbers can be used in this suffix, and the order is only important so long as it

agrees with any other net identifiers on the same bus. For example, we could change the net

label D[0..7] to D[7..0], so long as we also changed the order both in the attached port and in the

sheet entry it matches on the top sheet of this design.

It is recommended that the net labels prefix does not end with a number, for example,

Headphone[1..8] netlabel where the Headphone prefix only has alpha characters. The

Headphone1[1..8] netlabel has a number 1 at the end of the prefiix which expands toHeadphone11..Headphone 18, which can cause net naming conflicts in your design.

10 AR0123 (v1.8) July 30, 2008


11/16



Notice that the logical bus is created by the net label, not the bus primitive. The electrical function of the bus is to connect these

net identifiers. Remember that net identifiers of different types do not automatically connect to one another, even if they share

the same name. This holds true for net identifiers with bus syntax; a net label D[0..7] will not a

the same name. The bus is required to connect them together.

The rest o

utomatically connect to a port with

f the bus that portion which extends towards the individual nets, is important for

e

which are entirely graphical do not touch any net

tivity, because their names do not conform to the

x, and be

graphical reasons only. Bus entries have no connective properties, but provide a clearance

around buses which might be fed by wires on either side (two wires touching a bus at the sam

point would short together).

The two buses in the example schematic

identifiers. In this case, the actual connections will be made between matching net labels.

Deleting such buses would have absolutely no effect upon the connectivity of your sheet

(although it would make the schematic harder for humans to read).

The nets in this example are, in fact, ineligible for logical bus connec

requirements of the bus syntax. Remember that all nets in a single bus must be individually labeled with the same prefi

distinguished from one another by their numeric suffix alone.

AR0123 (v1.8) July 30, 2008 11


12/16



Navigating a Multi-Sheet DesignNavigating a Multi-Sheet Design

The Navigator Panel

When you have finished your schematic project, you dont need to generate the netlist and laboriously cross-check each net by

hand. All connectivity information is displayed upon compilation in the Navigatorpanel which has the added benefit of being

interactive with your design.

The Navigatorpanel is the center-piece for net connectivity in your design. The

top section arranges your project sheets in three ways: as a list of compiled

sheets, as a flattened hierarchy and as a structural tree. After compiling a multi-

sheet project, you should immediately check the tree to see if your intended

structure has been correctly defined through sheet symbols.

The following two sections in the panel list the Instances and Net/Buses in your

project. These also are displayed in tree format, as a sheet symbol may contain

multiple sheet entries, and a component may include multiple parameters,

models and pins. Similarly, a logical bus will branch down to the nets it

packages together.

The contents of the final section of the panel depends upon two things: theobject you are navigating, and the objects you have set for display. The master

list of objects you want to display can be accessed in the options pop-up

associated with the panel's Interactive Navigationbutton, but you can right-

click in the panel and enable or disable them individually through the Show

submenu.

Click on a sheet in the top section, and the bottom section will list its ports. Click

on a component in the next section, and the bottom section will report its pins.

Open the tree for that component, and click on one of its pins, and the bottom

section will show this and all of the other pins and net identifiers on the same

net. This is the same result you get when clicking on any of the bus or net

objects in the third section.

Notice that its not just the bottom section that updates when you click on anobject. Each section of the panel will jump to the corresponding item in its l ist

when a navigated object pertains specifically to it.

The other thing that updates is the workspace. As you click on an object in the

Navigatorpanel filtering will be applied, the visual result of which is controlled

by a number of highlighting options. These options (described below) can be

accessed and set either from the options pop-up associated with the panel's

Interactive Navigationbutton, or from the System Navigationpage of the

Preferencesdialog.

Zooming- when enabled, the filtered objects will be zoomed and centered

(where possible) in the main design window. The zoom level - the extent of

zooming applied when navigating from either the panel or interactively

within the design document - can be controlled using the Zoom Precisionslider bar. A greater zoom level is achieved by moving the slider to the

(The zoom facility has no effect when the t

right.

arget object is a port and resides in a HDL file)

Selecting- when enabled, the filtered objects will be selected in the workspace

Masking- when enabled, the filtered objects will appear fully visible in the main design window, with all other objects

becoming dimmed. Control over the contrast between filtered and masked objects is provided using the Mask Level button

at the bottom right of the workspace

Connective Graph- enabling this option displays the connective relationship between objects (on the active document in

the main design window). The visual connections will be green when navigating by components and red when navigating by

nets. Enable the Include Power Partssub-option if you wish to also graph the connectivity of power objects

Any combination of these options can be enabled. For example, you might want to have all filtered objects zoomed, centered

and selected in the main design window, whilst applying masking to take away the clutter of other design objects.

12 AR0123 (v1.8) July 30, 2008


13/16



Figure 9. Example of connective

graph when navigating a component

Figure 8. Example of connective

graph when navigating a net object

Figure 8 shows an example of the connective graph when navigating to a net object (bus, net, pin, bus line, wire or net

identifier). This line is drawn in red, showing all of the connected net objects that you have set to display. The line is solid,

meaning that the pins are connected physically, rather than logically, which would be shown by a dotted red line.

Figure 9 shows an example of the connective graph when navigating to a component. Component graphs are displayed with

green lines, showing the other components which are immediately connected to the component to which you have navigated.The navigation tools can operate on multiple sheets at once. Navigating to a bus or net will apply the highlighting options to all

sheets where they are found. Of course, this will be hard to notice if your entire screen is filled with a single document. Cross-

sheet highlighting becomes helpful when the project documents are arranged (tiled) on one or more monitors.

For detailed information on the Navigatorpanel, press F1while the cursor is over the (focused) panel.

Other Methods of Navigation

Logical navigation clicking in the Navigatorpanels tree structures is one of many ways to browse the connective model of

your design.

Spatial Navigation

At the top right of the Navigatorpanel is an Interactive Navigationbutton. Clicking this turns your cursor into a crosshair target

in the active schematic document. This gives you a spatial alternative to the logical list presented in the panel itself. Click on anet to highlight all objects in the net, click on a port to jump to the sheet entry it connects to, and so on. The Navigatorpanels

contents will update according to the object you choose. The cursor will remain in this navigation mode until you right-click or

press the Esckey.

Navigating Hierarchy

Use the Up/Down Hierarchy feature, accessed by clicking on the button, to navigate up or down through the design

hierarchy. If you click on a sheet entry you will be presented with the matching port on the sub-sheet, if you click on a sheet

symbol you will be presented with the entire sub-sheet. To navigate up through the hierarchy, click a port to be presented with

the matching sheet entry on the parent sheet.

Hierarchy can also be navigated directly by pressing Ctrland double-clicking over a port, sheet entry or sheet symbol.

Cross-Probing between Schematic and PCBSince designing a PCB from a schematic project is a highly iterative process, the Navigatorpanel also allows cross-probing

between schematic and PCB documents. Open the PCB document, and hold down theAl tkey while navigating objects on the

schematic source the same highlighting options will apply to both the navigated schematic objects and the corresponding PCB

objects.

You will find that cross-probing through the Navigatorpanel is a little bit different than using the cross-probe command in the

Toolsmenu. The latter command is available in both schematic and PCB environments, while the Navigatorpanels tools are

designed to start in the schematic portion of the project. The cross-probe tool does not apply the current highlighting settings to

the document youre probingonly the destination document that responds. Finally, the cross-probe tool offers jump-probing,

done by holding the Ctrlkey when probing an object. This is different from the Navigatorpanels tools, which will apply

highlights to the PCB, but will not make it the active document.

AR0123 (v1.8) July 30, 2008 13


14/16



Connectivity Insight

Connectivity Insight, part of Design Insight, is interactive with the added benefit of displaying connectivity at a highly-visual,

project level. Hover over a Sheet Symbol to see a preview of the child sheet as shown below. This document preview is

available prior to compiling your project.

Compile your project to establish and view the connective relationship between net objects.. After compilation, hover over a net

object to gain insight into the connectivity of that net object across your whole project. Alternatively, use the keyboard shortcut

Alt+Double Clickon any net object to show Connectivity Insight on demand.

Connectivity Insightshows the active document displayed in preview mode, with the net information displayed as a hint. The

selected net is highlighted with all other objects masked. If the net object is connected to nets on other documents, these

documents will be displayed with respect to your project hierarchy, with the selected net highlighted for ease of navigation.

Figure 10. Connectivity Insight in action the active document is displayed with the selected net highlighted

14 AR0123 (v1.8) July 30, 2008


15/16



Connectivity Insight is available for any net object such as a port, sheet entry, bus, power port, component or harness objects.

For Sheet Symbols, it will show the child sheet. For components, it will show all of the pins connected to that component. If the

component is a multi-part component, all of the parts for that component will be displayed.

Navigate to a document by clicking on the document name in the list. The masking is maintained until you click in the document.

In your Design Insight Preferences (DXP Preferences System Design Insight), you can disable and enableAlt+Double

Clickand the Hover style independently, choose whether to display hints, document preview or both and you can even controlthe time delay for popping up hover invoked Connectivity Insight.

Refer to Project Essentialsdocument for more information about Project Insight, a feature of Design Insight.

Refer to The Altium Designer Environment document for more information about Document Insight, a feature of Design

Insight.

AR0123 (v1.8) July 30, 2008 15
http://ap0129%20project%20essentials.pdf/http://gu0112%20welcome%20to%20the%20altium%20designer%20environment.pdf/http://gu0112%20welcome%20to%20the%20altium%20designer%20environment.pdf/http://ap0129%20project%20essentials.pdf/


16/16

Documents

AR0123 Connectivity and Multi-Sheet Design