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© 2014, it - instituto de telecomunicações. Todos os direitos reservados.
Nuno Horta
Integrated Circuits Group
Instituto de Telecomunicações
Instituto Superior Técnico, University of Lisbon, PT
EDA Tools for Analog IC Design Performance Optimization and Reduced Design Time
2
Integrated Circuits Group - IT
HEAD: Nuno Horta
Senior Member at IEEE, ACM and IT
Professor at Electrical and Computers Engineering Dept. in IST
TEAM:
4 PhDs (Nuno Horta, Nuno Lourenço, Ricardo Martins and Jorge Guilherme), 4 PhD
Students, 8 MSc Students
RESEARCH AREAS:
Analog EDA, Analog IC Design, Intelligent Computation
PROJECTS:
More than 20 international and national projects
PUBLICATIONS:
More than 100 publications respectively books, book chapters, journal papers (IEEE
JSSC, IEEE TCAD, IEEE TCAS II, Expert Systems with Applications (Elsevier),
Applied Soft Computing) and international conference papers (IEEE ISCAS, IEEE
VLSI-SOC, DATE, SMACD, ECCTD)
| THALES Workshop - September 28th, IST - Lisbon
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Analog ICs - Application Domains related to THALES
[ExoMars – THALES Alenia Space]
[Satellites – THALES Alenia Space]
[Defence – THALES]
[Transportation – THALES]
Analog ICs are
fundamental to
establish the
interface between the
digital environments
and the real world.
Application
Domains:
• Space Exploration,
• Automotive
Industry,
• Satellite Industry,
• Communication,
• Healthcare, etc.
| THALES Workshop - September 28th, IST - Lisbon
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Analog IC Design Automation
LAYOUT-AWARE SIZING
PARETO FRONT
AUTOMATIC
[Single Stage Amplifier with Gain Enhancement using Voltage Combiner, R. Póvoa et al., 2013]
vip
PM1PM0 PM3PM2
NM10 NM11
NM4
NM6
NM8 NM9
NM7
NM5
vin vip
vin
vonvop
VDD VDD VDD VDD
VDD VDD
VSS VSS
VSS VSS
cmfb
cssa cssb
n1 n2
| THALES Workshop - September 28th, IST - Lisbon
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Analog IC Design Automation: AIDAsoft (www.aidasoft.com)
AIDAsoft
• R&D (Fully developed at IT/IST)
• Awarded EDA tool (SMACD 2015, ISCAS 2014)
• Innovative Layout-Aware Analog IC Sizing Met.
• Full Custom Automatic Layout Generation
• Interface with major CAD Environment and
Simulators (ELDO, HSPICE and Spectre)
| THALES Workshop - September 28th, IST - Lisbon
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Analog and Mixed Signal IC Design
Multi-mode Stereo Class-D Amplifier Architecture
Short-Circuit
detectorInternal ControlReference
Generator
Power
H-Bridge(and replicas)
Power
Drivers
Vgsi4
4
4
4
LP
F
Lo
ad
External
RC network
External
RC networkDrive
co
ntr
ol
QOscFFlvc
Le
ve
l W
ind
ow
co
ntr
ol
Tu
nn
ing
an
d c
on
tro
l
Dig PWM
PCM
4
DAC
Power
H-Bridge(and replicas)
Power
Drivers
Vgsi4
4
4
4
LP
F
Lo
ad
External
RC network
External
RC network
Driv
e c
on
trol
QOscFFlvc
Le
ve
l Win
do
w c
on
trol
Tu
nn
ing
an
d c
on
trol
Dig PWM
PCM
4
DAC
Designed – both schematic and layout
Ongoing design – schematic phase
Starting development
TC phase
Test-chip Prototype
IC Design Examples:
• Pipelined A/D Converter,
• Logaritmic A/D Converter
• Delta-Sigma Converters
• DC/DC Converters
• LNAs, LC-VCO, Class D Amplifiers, etc.
| THALES Workshop - September 28th, IST - Lisbon
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THALES Alenia Space (France)
• System-Level Design for
Pipeline Data Converters
THALES Alenia Space (France)
• Circuit-Level Sizing and
Optimization
• 5 MSc Co-Supervisions
(2014/2015 and 2015/2016)
IT – THALES Alenia Space Cooperation
SCALES Project (2011-2014)
AIDA-C Project (2013-2016)
Vin
ADC DAC
+
-
B bits
Vout
B bits B bits
VinStage 1 Stage 2 Stage M-1 Stage M
2Bn
n
nn
S/H
S/H
B1 B2 BM-1 BM
Digital delay line
Digital correction logic
bits word
N
M
bits output word
| THALES Workshop - September 28th, IST - Lisbon
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Integrated Circuits Group - IT
CONTACT:
Person: Prof. Nuno Horta
Email: [email protected]
Phone: +351 218418093
| THALES Workshop - September 28th, IST - Lisbon
