Apic Mitul

04/08/2023Advanced Programable Interrupt Controller

Advanced Programmable Interrupt Controller

(APIC)

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Presented By Mitul Modi(ME – I - MSA –199)M S University, Baroda2012-13


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OUTLINES Basic Overview

Local APIC

Handling Local Interrupts

APIC Timer

Issuing Inter processor Interrupts (IPIs)

System and APIC bus Arbitration

Flowcharts Handling Interrupts

Message Signal Interrupts


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CONTROL

BY

APIC

Interrupt Systems :B A S I C O V E R V I E W


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Capabilities of APIC


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APIC Architecture :


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APIC (Advanced Programmable Interrupt Controller)

• Local APIC– Internal in CPUs– Receives interrupts from CPU’s interrupt pins, from

internal sources and from an external I/O APIC– Sends and receives IPI (InterProcessor Interrupt)

• I/O APIC– Part of a chipset – Receives external interrupts and relays them to a

local APIC– Possibility of IPI distribution among CPUs

• xAPIC– Newer architecture – using in P4 and Xeons architectures


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Relation Between Local APIC and I/O APIC when Xeon Processor are used in MP

Relation Between Local APIC and I/O APIC when P6 Processor are used in MP

• For the P6 family and Pentium processors, the I/O APIC and local APICs communicate through the 3-wire inter-APIC bus. The local APICs also use the APIC bus to send and receive IPIs. The APIC bus and its messages are invisible to software and are not classed as architectural.• Beginning with the Pentium 4 and Intel Xeon processors, the I/O APIC and local APICs (using the xAPIC architecture) communicate through the system bus. Here the I/O APIC sends interrupt requests to the processors on the system bus through bridge hardware that is part of the Intel chip set. This bridge hardware generates the actual interrupt messages that go to the local APICs. IPIs between local APICs are transmitted directly on the system bus.

Comparison Between System Bus and APIC Bus.


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Block diagram of Local APIC Software interacts with the local APIC by reading and writing its registers. The APIC registers are memory-mapped to a 4-Kbyte region of the processor’s physical address spaceFor correct APIC operation, this address space must be mapped to an area of memory that has been designated as strong uncacheable (UC).Strong Uncacheable (UC)—System

memory locations are not cached. All reads and writes appear on the system bus and are executed in program order without reordering.

1. Introduced in P6 family processors.2. Introduced in the Pentium 4 and

Intel Xeon processors.3. Three-wire APIC bus in P6 family and

Pentium processors.4. Not implemented in Pentium 4 and

Intel Xeon processors.

L O C A L A P I C


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Presence of the Local APICIn p6 Processor Family, the presence or absence of an on-chip local APIC can be detected using the CPUID instruction. When the CPUID instruction is executed with a source operand of 1 in the EAX register, bit 9 of the CPUID feature flags returned in the EDX register indicates the presence (set) or absence (clear) of a local APIC.

Enabling or Disabling the Local APIC(1) Using the APIC global enable/disable flag in the IA32_APIC_BASE MSR

(2) Using the APIC software enable/disable flag in the spurious-interrupt vector register


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Local APIC State:Local APIC State after Power-up or RESET• The following registers are reset to all 0s: the IRR, ISR, TMR, ICR, LDR, and TPR registers; the timer initial count and timer current count registers; and the divide configuration register.• The DFR (Destination Format Register) is reset to all 1s.• The LVT (Local Vector Table) register entries are reset to all 0s except for the mask bits, which are set to 1s.• The local APIC version register is not affected.• The local APIC ID register is set to a unique APIC ID. The Arb ID register is set to the value in the APIC ID register• If the processor is the only processor in the system or it is in an MP system the local APIC will respond normally to INIT and NMI messages,

An INIT RESET of the processor can be initiated in either of two ways:• By asserting the processor’s INIT# pin.• By sending the processor an INIT IPI local APIC INIT RESET is the same as it is after a power-up or hardware RESET, except that the APIC ID and arbitration ID registers are not affected. This state is also referred to at the “wait-for-SIPI” state.

Local APIC State after an INIT RESET


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Local APIC State after it has been software disabled

When the APIC software enable/disable flag in the spurious interrupt vector register has been explicitly cleared (as opposed to being cleared during a power up or RESET), the local APIC is temporarily disabled. • The local APIC will respond normally to INIT, NMI, SMI, and SIPI messages.• Pending interrupts in the IRR and ISR registers are held and require masking or handling by CPU.• The reception or transmission of any IPIs that are in progress when the local APIC is disabled are completed before the local APIC enters the software-disabled state.

Local APIC Version Register

Version:1XH = Local APIC for P4 and Intel Xeon Processor0XH = 82486DX external APIC


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H A N D L I N G L O C A L I N T E R R U P T S :

Local Vector Table:

• Five 32 bits APIC Registers.1. LVT Timer Register2. LVT Thermal Monitor

Register3. LVT Performance

Counter Register4. LVT LINTX Registers5. LVT Error Register


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Error Handling:

Error Status Register (ESR)


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APIC Timer:

LVT Timer Register


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I S S U I N G I N T E R P RO C E S S O R I N T E R RU P TS ( I P I s ) The following sections describe the local APIC facilities that are

provided for issuing inter processor interrupts (IPIs) from software. The primary local APIC facility for issuing IPIs is the interrupt command register (ICR). The ICR can be used for the following functions:

• To send an interrupt to another processor.• To direct the processor to interrupt itself (perform a self interrupt).• To deliver special IPIs, such as the start-up IPI (SIPI) message, to other processors.

Basically to determine IPI destination Destination Mode, Destination field, Destination Shorthand, Delivery Mode of ICR, LDR (Local Destination Register and DFR (Destination Format Register) are used that depends upon following destination mode.1. Physical Destination Mode2. Logical Destination Mode3. Broadcast / self Delivery

Mode4. Lowest Priority Delivery

Mode

Interrupt Command Register (ICR)


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S Y S T E M A N D A P I C B U S A R B I T R A T I O NWhen several local APICs and the I/O APIC are sending IPI and interrupt messages on the system bus (or APIC bus), the order in which the messages are sent and handled which is determined through bus arbitration.

For the Pentium 4 and Intel Xeon processors, the local and I/O APICs use the arbitration mechanism defined for the system bus to determine the order in which IPIs are handled. This mechanism is non-architectural and cannot be controlled by software.

For the P6 family and Pentium processors, the local and I/O APICs use an APIC-based arbitration mechanism to determine the order in which IPIs are handled. Here, each local APIC is given an arbitration priority of from 0 to 15, which the I/O APIC uses during arbitration to determine which local APIC should be given access to the APIC bus. The local APIC with the highest arbitration priority always wins bus access. Upon completion of an arbitration round, the winning local APIC lowers its arbitration priority to 0 and the losing local APICs each raise theirs by 1.


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F L O W C H A R T S H A N D L I N G I N T E R R U P T SInterrupt Handling with the Pentium 4 and Intel Xeon Processors

(1) It determines if it is the specified destination or not. If it is the specified destination, it accepts the message; if it is not, it discards the message.

(2) If the local APIC determines that it is the designated destination for the interrupt and if the interrupt request is an NMI, SMI, INIT, ExtINT, or SIPI, the interrupt is sent directly to the processor core for handling.

(3) If the local APIC determines that it is the designated destination for the interrupt but the interrupt request is not one of the interrupts given in step 2, the local APIC sets the appropriate bit in the IRR.

(4) When interrupts are pending in the IRR and ISR register, the local APIC dispatches them to the processor one at a time, based on their priority and the current task and processor priorities in the TPR and PPR.(5) When a fixed interrupt has been dispatched to the processor core for handling, the completion of the handler routine is indicated with an instruction in the instruction handler code that writes to the end-of-interrupt (EOI) register in the local APIC

Procedure:


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Interrupt Handling with the P6 Family and Pentium Processors


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Task and Processor Priorities

Task Priority Register (TPR)

Processor Priority Register (PPR)


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Interrupt Acceptance for Fixed Interrupts

The IRR contains the active interrupt requests that have been accepted, but not yet dispatched to the processor for servicing. When the local APIC accepts an interrupt, it sets the bit in the IRR that corresponds the vector of the accepted interrupt. When the processor core is ready to handle the next interrupt, the local APIC clears the highest priority IRR bit that is set and sets the corresponding ISR bit. The vector for the highest priority bit set in the ISR is then dispatched to the processor core for servicing. then repeats the process of clearing the highest priority bit in the IRR and setting the corresponding bit in the ISR. The processor core then begins executing the service routing for the highest priority bit set in the ISR.

The trigger mode register (TMR) indicates the trigger mode of the interrupt. Upon acceptance of an interrupt into the IRR, the corresponding TMR bit is cleared for edge triggered interrupts and set for level-triggered interrupts

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Message Address Register Format

Message Data Register Format

M E S S A G E S I G N A L L E D I N T E R R U P T S


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R E F E R E N C E S :

1. IA-32 Intel® Architecture Software Developer’s Manual Volume 3: System Programming Guide

2. Presentation On “Microprocessor system architectures – IA32 advanced features and rests” By Jakub Yaghob.

3. Pentium® Processor Family Developer’s Manual Volume 1: Pentium® Processors

4. Minimal Intel Architecture Boot Loader Bare Bones Functionality Required for Booting an Intel Architecture Platform January 2010

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