AP0156 Interacting With the Desktop NanoBoard NB2DSK01

Interacting with the

Desktop NanoBoard NB2DSK01

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Altium's Desktop NanoBoard NB2DSK01 is a unique, reconfigurable hardware platform that harnesses the power of today's high-capacity, low-cost programmable devices to allow rapid and interactive implementation and debugging of your digital designs.

When the Desktop NanoBoard NB2DSK01 is powered on, the TFT LCD panel will present a graphical user interface, the Home screen of which is shown in Figure 1. This GUI is driven by the firmware running on the board's Spartan-3 FPGA device (NanoTalk Controller). Through its touch screen, the panel becomes a portal to the firmware, allowing direct interaction with various NB2DSK01 resources.

Programmable Clock FrequencyCurrent Time

(Output from Real Time Clock)NanoBoard-to-PC Connection

(Parallel Port or USB2.0)

Icons giving accessto sub-screens

Detected peripheral boards(Board.Revision) attached tomotherboard connectors:‘PERIPHERAL BOARD A’‘PERIPHERAL BOARD B’‘PERIPHERAL BOARD C’

Detected NanoBoard(Board.Revision) and currently

loaded version of firmware

Detected daughter board(Board.Revision) attached tomotherboard

Icon for handing TFT LCDpanel control fromfirmware GUI to daughterboard FPGA design

Icon for manualactivation of screensaver

Figure 1. TFT LCD panel GUI – allowing direct interaction with the NB2DSK01.

Driving the GUI

Navigation and selection on the TFT LCD panel is simply a case of touch-and-go. This facility is provided courtesy of the panel's touch screen layer. Use your finger, or the supplied stylus, to touch icons and descend into sub-screens of the GUI, which collectively provide access to a myriad of features.

Summary This application note describes how the TFT LCD panel on the Desktop NanoBoard NB2DSK01 can be used to directly interact with the firmware, running on the board's Spartan-3 FPGA (NanoTalk Controller).

AP0156 Interacting with the Desktop NanoBoard NB2DSK01

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In both cases, ensure that you keep the three generic user switches pressed until the reset screen appears. Otherwise you will simply be performing a reset of the NanoTalk Controller.

The screen saver can also be activated manually, and immediately, by clicking on the available icon on the Home screen of the GUI. Manual activation does not depend on the Enable Screen Saver setting.

If no images can be found – in either Flash memory or an SD card – a simple screen saver will be used, with the Altium logo cycling through different locations on the screen.

The GUI itself is very intuitive – a few taps on the screen and you will quickly become familiarized with the controls and options available. The following list offers a few pointers when using the GUI – some obvious, some more subtle, but all aimed at making your experience with the GUI a more productive one. For more detail on specific features offered by the GUI, see the section Interactive features.

• The panel's touch screen should already be calibrated correctly upon first use. However, recalibration can be performed at any time. From the Home screen of the GUI, touch the icon, followed by the icon. Calibration involves touching at four prompted locations – top-left, top-right, bottom-right and bottom-left.

• If a screen presents radio-button style options, simply touch the radio button for the option that you wish to make use of. If a screen presents check box style options, simply touch on the check box area to toggle the state of that option.

• If a screen allows you to change a setting, there will typically be two icons at the bottom of the screen with which to commit the change or cancel and return back to the parent GUI screen .

• The icon at the bottom-right of a screen may change depending on the context of the screen and the action permitted. For example, if you have selected an example design on the Examples screen, or an FPGA programming file on the Browse screen, the icon will appear as , meaning the design/file will be downloaded to the daughter board FPGA if touched.

• Settings modified through the GUI can be reset to their default values. This can be achieved in one of two ways: - Press and hold generic user switches SW1, SW3 and SW5 (located below the TFT LCD

panel) and keep the Home button (designated SW9 and located to the top-right of the panel) pressed for more than 5 seconds.

- Press and hold generic user switches SW1, SW3 and SW5 and cycle the NB2DSK01's power.

In both cases, a screen will appear on the TFT LCD panel asking for confirmation to proceed with the reset. Press generic user switch SW4 to load the defaults (Yes) or SW2 to decline (No) and keep your current settings.

• Certain sub-screens or options of the GUI will be disabled if they can not be used or accessed at that time. The Examples screen, for example, will only become enabled if an SD card with applicable content is inserted into the motherboard's SD card reader. Another example is the GUI to daughter board icon, , which will be disabled unless an FPGA design is running on the daughter board FPGA, and which utilizes the TFT LCD panel.

• The image at the top-left of the screen reflects the current JTAG connection between the NB2DSK01 and the PC. denotes a parallel port connection, while denotes a USB2.0 connection. The image will flicker momentarily, and periodically, in accordance with the chosen polling interval, defined on the FPGA – Devices View page of the Preferences dialog (DXP » Preferences).

• The version of firmware currently installed and running on the NanoTalk Controller is reflected at the bottom of the GUI's Home screen. If there is a later version of firmware available, you will need to follow the procedure for updating to the new firmware. For detailed information on how to do this, refer to the document AP0155 Updating the Firmware on the Desktop NanoBoard NB2DSK01.

GUI options

To access options for the GUI, from the Home screen of the GUI touch on the icon, followed by the icon on the sub-screen that appears. The following options are available: • Enable Screen Saver – use this option to enable the automatic screen saver.

Screen saving will be applied after the TFT panel's touch screen has not been touched for a period of 10 minutes. The automatic screen saver functionality simply displays Bitmap or JPEG images in a loop, with each image displayed for 10 seconds. Images are sourced from two places – within the ScreenSaver folder stored in the NB2DSK01's common-bus Flash memory, and within a ScreenSaver folder resident on an SD card currently inserted into the motherboard's SD card reader. All images found within the Flash location will be used first, followed by those found on the SD card.

To return back to the GUI while the screen saver is running, simply touch the panel.

• Enable Sounds – enable this option to have action-based sounds played during the course of using the GUI, for example when you touch on the accept/confirm icon . Use the NB2DSK01's volume control to adjust the sound level as required.


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• Enable RGB LEDs – use this option to control the ON/OFF state of the RGB LEDs on the attached Desktop Stereo Speaker Assembly NB2DSK-SPK01.

• Fade Screens – Use this option to enable a 'fade' effect when transitioning between screens of the GUI.

• Show intro at startup – With this option enabled, introductory screens will be presented on the panel whenever the NB2DSK01 is powered on, or after a reset of the NanoTalk Controller. These screens are in fact JPEG images, stored within the Welcome folder in the NB2DSK01's common-bus Flash memory.

This option is also presented while the introductory screens are being viewed, so that you can opt to disable these screens directly. There is also an option to skip the intro screens.

A shared panel...

The TFT LCD panel on the NB2DSK01 is used by the firmware, to present the interactive GUI, but it can also be used by a design running on the daughter board FPGA. When you program the FPGA with a design that utilizes the panel, it will automatically assume control (provided the DAU_TFT_MUX line is tied High in the design).

To pass ownership of the panel back to the firmware running on the NanoTalk Controller, you simply need to press the NB2DSK01's 'Home' button (designated SW9 and located to the top-right of the panel). This button actually serves multiple purposes: • By pressing and releasing quickly, the firmware is given the driving seat for the panel – presenting the Home screen of the

GUI.

• If pressed and held for more than 5 seconds, the NanoTalk Controller is reset. • If pressed and held for more than 5 seconds while also holding generic user switches SW1, SW3 and SW5, a screen is

accessed from which to reset GUI options to default settings. (Note: The generic switches must be kept pressed until the reset screen actually appears).

If you need to give control of the panel back to the daughter board FPGA again, simply touch the icon on the Home screen of the GUI. Whatever was displayed on the panel prior to handing control to the firmware will reappear on the panel.


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Interactive features

The previous section gave an overview of the firmware-driven GUI on the TFT LCD panel and how ownership of the panel is passed from the firmware running on the NanoTalk Controller to the design running on the daughter board FPGA, and vice-versa. The following sections take a closer look at some of the other key screens and functions provided by the GUI.

Bootstrapping the daughter board FPGA

The Desktop NanoBoard NB2DSK01 provides the ability to bootstrap the physical FPGA device, on the currently inserted daughter board, at power-up.

To access boot controls (Figure 2), from the Home screen of the GUI touch the icon, followed by the icon.

The GUI allows you to choose whether or not you wish to enable use of the boot feature and, if so, from where the programming file(s) for the design will be sourced for the boot process – either from an SD memory card inserted into the NB2DSK01 motherboard's SD card reader, or from dedicated on-board SPI Flash memory.

Booting from an SD card To boot from an SD memory card on power-up, simply use the GUI to select the option First example found on SD-card, and ensure the SD memory card carrying the design is inserted into the motherboard's SD card reader (designated J8 on the board).

Note: The required FPGA programming file and HEX file (for the code if applicable) must reside on the card, and be pointed to by an associated EXAMPLE file (*.example), also on the card, and in the same location. For more information on EXAMPLE files, see the section Examples screen, later in this document.

Once the NB2DSK01's power is cycled, the first EXAMPLE file found will be used (EXAMPLE files are sorted alphabetically). This will also depend on the file structure in-place on the card. The FPGA programming file referenced in the EXAMPLE file will be downloaded to the daughter board FPGA. Any HEX file referenced will be downloaded to the M25P80 SPI Flash memory device that is solely used for embedded storage purposes (designated U20 on the motherboard).

Booting from SPI Flash memory To boot using a design stored in serial Flash memory, simply use the GUI to select the Serial Flash option and ensure that the FPGA programming file for the design is loaded into the M25P80 SPI Flash memory device that is used for boot purposes (designated U21 on the motherboard). Once the NB2DSK01's power is cycled, the FPGA programming file stored in the SPI Flash memory will be downloaded to the daughter board FPGA.

The procedure for loading an FPGA programming file into the Flash memory can be carried out at any time – with or without an FPGA project open and irrespective of whether a design is currently programmed into the target FPGA device (on the daughter board).

Controls for downloading to, and erasing, the Flash memory, can be found in the Flash RAM Controller For FPGA Boot dialog. Access to and use of this dialog, is detailed in the following sections.

Accessing Flash memory controls The Flash RAM Controller For FPGA Boot dialog is accessed directly from the instrument panel for the NB2DSK01's NanoTalk Controller. From the Devices view (View » Devices View), simply double-click on the icon for the NanoBoard (in the NanoBoard Controllers chain) whose FPGA Boot Flash memory you wish to load. The Instrument Rack – NanoBoard Controllers panel will appear. Click on the FPGA Boot Flash button to access the dialog (Figure 3).

Figure 2. Controls related to bootstrapping of the FPGA device.


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Figure 3. Accessing controls for the FPGA Boot Flash memory.

The Device ID region of the dialog reflects the communications link between the NanoTalk Controller and the Flash memory device. If communications are successful, upon accessing the dialog a value of $13 will be entered into the far right field and the confirmatory message "Device Found: M25P80 (8M-Bit Serial Flash RAM)" will be displayed. If this is not the case, try to manually interrogate the communications link by pressing the Read Electronic Signature button.

Erasing the Flash memory Before loading the required programming file into the Flash memory device, the memory must first be cleared. To erase the entire 8Mbit of Flash memory, press the Erase Entire Device button, in the Erase region of the Flash RAM Controller For FPGA Boot dialog. The erasing process will take approximately five to eight seconds, after which a confirmation dialog will appear (Figure 4).

Controls are also available for erasing a particular sector of memory. Each M25P80 device is organized into 16 sectors. Each sector contains 256 pages, and each page is 256 bytes wide. Therefore each sector is 65536 bytes or 512Kbits.

Simply use the available drop-down to select the sector you wish to erase (or enter the sector number directly) and then click the Erase Sector button. Erasure time is typically less than a second, after which time you will receive a dialog to confirm completion of the erase (Figure 5).

To verify that the device has been successfully erased, press the Blank Check button. The verification process will take approximately sixty seconds, after which time you will receive another confirmation dialog (Figure 6).

Figure 4. Confirming full erasure.

Figure 5. Sector erasure. Figure 6. Verification of memory erasure.


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Downloading to Flash memory Once the Flash memory has been erased, the programming file can be downloaded. From the Download region of the Flash RAM Controller For FPGA Boot dialog, press the ... button to the right of the File Name field. The Choose FPGA Programming File For Download dialog will appear. Use this dialog to browse to, and open, the required file. The programming file used depends on the target device: • *.bit file for a Xilinx device

• *.rbf file for an Altera device

• *.rbt (ASCII) or *.bit (binary) file for a Lattice device

• *.stp file for an Actel device.

Note: When using Xilinx FPGA devices, the programming file used will be different for JTAG programming and Slave-Serial programming. The SPI Flash memory on the NB2DSK01 uses the latter when loading the FPGA device on the daughter board. Therefore, when choosing the programming file, the _cclk.bit version of the file should be used.

For a design that has been compiled, synthesized and built using Altium Designer, the programming file will be located in the {OutputPath}\ConfigurationName sub-folder defined for the project. The {OutputPath} is project-specific and is defined on the Options tab of the Options for FPGA Project dialog (Project » Project Options). ConfigurationName is the configuration containing a constraint file that targets the physical FPGA device on the daughter board, into which the design will be programmed. For example NB2DSK01_08_DB30_06, which targets the Xilinx Spartan-3 device on the DB30. After choosing the file and clicking Open, you will be returned to the Flash RAM Controller For FPGA Boot dialog. The chosen file (including path) will be displayed in the File Name field (Figure 7). To download this file to the Flash memory device, simply click the Save File To Flash button. If you want to download to a specific area of memory, enter the required address in the Memory Address field. The download process will proceed, with progress shown in Altium Designer's Status bar. At the end of the download an information dialog will appear, confirming the end of the process (Figure 8).

Figure 8. Confirmation of file download to the Flash memory device.

Figure 7. FPGA programming file chosen and ready for download.


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Verifying the download After you have downloaded the FPGA programming file to the Flash memory device, a check should be made to ensure the integrity of the file. To do this, simply click on the Verify against File button, in the Download region of the Flash RAM Controller For FPGA Boot dialog.

The contents of the Flash memory are read back and compared against the original programming file. Progress is again reflected in Altium Designer's Status bar. An information dialog will appear at the end of the process, providing details of the verification results (Figure 9).

If the download process is shown to have failed, the dialog will report an error count. A large number of errors typically indicates that the Flash memory device was not successfully erased prior to downloading the programming file. In this case, try erasing the device again – using the Erase Entire Device button – and then using the Blank Check button to verify that the device's memory has indeed been successfully erased. The programming file can then be downloaded again.

Downloading example designs stored on an SD card

When an SD memory card is inserted into the NB2DSK01 motherboard's SD card reader, the icon becomes enabled on the Home screen of the GUI. Touch this icon to access the Examples sub-screen. This screen of the GUI lists all EXAMPLE files (*.example) found on the SD card. The upper region of the screen provides a short description of each example. Touch an entry to populate the lower region of the screen with a more detailed description.

Examples appearing in the list can be downloaded directly to the FPGA device on the daughter board. Simply select an example and then touch the icon that appears at the bottom-right corner of the screen.

The EXAMPLE file itself is simply a list of constraint records. Two additional (non-constraint) records are used to store the text for the short and long descriptions that get displayed on TFT LCD panel, for example:

Record=ShortDescription | Text="Ethernet Analyser"

Record=LongDescription | Text="The Ethernet Analyser example provides

capture and filter functionality of packets seen on the PB03 Ethernet

connection"

A set of constraint records are used to declare the hardware configuration – the boards required within the NanoBoard system for the design to run. Board revision must be included when specifying the constraint for the daughter board or a peripheral board (e.g. PB03.06 for revision 6 of the peripheral board PB03). Revision of the NanoBoard is not necessary – as it is assumed that the design is to run on a daughter board plugged into the NB2DSK01, and so the revision of the motherboard is not checked.

For example, to run the Ethernet Analyser design on a Xilinx Spartan-3 device, which also involves use of peripheral board PB03, the following constraint entries would be made:

Record=Constraint | TargetKind=Board | TargetId=NB | Id="NB2DSK01"

Record=Constraint | TargetKind=Board | TargetId=DAUGHTERBOARD | Id="DB30.06"

Record=Constraint | TargetKind=Board | TargetId=PERIPHERALBOARD_B | Id="PB03.06"

A single constraint is used to define the clock speed to be used for the design, for example: Record=Constraint | TargetKind=Clock | TargetId=CLK_BRD | FPGA_CLOCK_FREQUENCY=49.5 Mhz

Finally, constraint records are used to declare which files to use when programming the daughter board FPGA device with the design. This will include the FPGA programming file and typically a program code file (*.hex) – the latter loaded into the motherboard's M25P80 SPI Flash memory device that is solely used for embedded storage purposes (designated U20 on the board). The following entries point to files to be used for a design targeting the Xilinx Spartan-3 on the DB30:

Record=Constraint | TargetKind=FPGA_FILE | Filename="dsf_ethernet_analyser_cclk.bit"

Record=Constraint | TargetKind=SERIAL_FLASH_FILE | Filename="ethernet_analyser_system_XROM.hex"

Figure 9. Successful verification of downloaded file.

Figure 10. Example designs.


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If using a folder structure on the SD card, the download files are expected to reside in the same folder as the EXAMPLE file itself.

You must perform a reset of the NanoTalk Controller in order to refresh the displayed list of contents for both SD card and Flash memory.

Note: Before the list of examples is populated, a check is made between the required hardware system configuration (specifically the daughter board and peripheral board(s) defined in each EXAMPLE file) and the actual hardware system configuration (daughter board and peripheral board(s) detected using the 1-Wire ID devices resident on each board). If a design example cannot run on the current hardware system, it will not appear in the list.

Browsing Flash memory and SD card content

The GUI provides a screen for browsing the file content of both the NB2DSK01's common-bus Flash memory and also an SD card currently inserted into the motherboard's SD card reader. To access this screen, simply touch the icon on the GUI's Home screen.

The screen will present the two storage locations in drive-style fashion: A: NB2FLASH

B: SD Card

Touch on one of the entries – if files are stored in a folder structure, each folder will be listed. Simply touch on a folder and then touch the icon at the bottom-right of the screen, to expand the folder and browse its contents.

FPGA programming files can be downloaded directly to the daughter board FPGA from this screen. Simply select the required programming file and then touch the icon that appears at the bottom-right corner of the screen. Note: Program code files (*.hex) can not currently be downloaded from the Browse screen. To download a design fully, an EXAMPLE file should be made, stored on the SD card, and the download performed from the Examples screen

If there are any image files (*.bmp or *.jpg), these can be opened directly within the TFT LCD panel. Once opened, simply touch the screen again to return to the GUI. Similarly, if there are any audio files (*.wav), you can open these for listening, directly from the panel. Doing so will open the GUI's Audio Player, the screen for which is illustrated in Figure 12.

Initially, controls are available to start playback and choose which of the speakers on the attached Desktop Stereo Speaker Assembly NB2DSK-SPK01 are enabled – Left channel, Right channel, or both. Simply touch on a speaker icon to toggle its state between enabled and disabled .

During playback, pause and stop controls become available and a progress bar is used to represent playback time (Figure 13). Use the NB2DSK01's volume control to crank-up the sound as required!

A word about storage... Both the NB2DSK01 common-bus Flash memory and the inserted SD card appear as additional drives within Windows Explorer, allowing you to quickly add file content to either storage location, or copy or move content between them.

The common-bus Flash memory offers just under 30MB of storage space. Content written to this memory will remain until deleted – it does not expire upon power down of the Desktop NanoBoard.

The following should be considered when using these two file storage facilities:

• EXAMPLE files can be stored in both locations, but the Examples screen of the GUI will only list those examples found on the SD card.

• If you wish to use the GUI's screen saver facility, the image files (.bmp and/or .jpg) must be stored within a folder named ScreenSaver in either storage location.

Figure 12. Playback music (wav) files using the GUI's Audio Player.

Figure 13. Screen appearance during playback.

Figure 11. Browsing file content.


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• Only those default introductory screens resident in the Flash memory's Welcome folder (welc1.jpg to welc6.jpg) are expected and displayed by the GUI when the option to show intro screens is enabled. Any additional Bitmap or JPEG files added to this folder will not be displayed as part of the intro-cycle.

Bypassing JTAG devices

With the NanoBoard-NB1, if a user board connected to the NanoBoard did not make use of, or support, the Soft JTAG chain, the TDI_SOFT and TDO_SOFT pins had to be connected at the header, in order for the chain not to be broken. With the Desktop NanoBoard NB2DSK01, there is no manual looping of such signals. You can selectively control which boards are included or excluded from the Soft JTAG chain, literally with a tap of the GUI screen. To access JTAG chain-related controls (Figure 14), from the Home screen of the GUI

touch the icon, followed by the icon.

You can choose to include/exclude any of the following boards – or more specifically, their associated header/connector:

• User Header A

• User Header B

• Peripheral Board A

• Peripheral Board B

• Peripheral Board C

By default, all boards will be included in the chain.

Changing system clock frequency

The NB2DSK01 motherboard provides an on-board system clock generator in the form of the SPI-compatible ICS307-02 device. The frequency of the programmable clock output from this device can be changed directly through the GUI. To access clock frequency-related controls (Figure 15), from the Home screen of the GUI

touch the icon, followed by the icon.

Simply touch the frequency required – the supported frequencies in the range 6 to 200MHz are listed – and then touch the icon to commit your selection.

The requested clock frequency is written, over the SPI bus, to the ICS307-02 device. It is also stored in the motherboard's common-bus Flash memory. The new frequency is read back from the Flash memory and reflected at the top-center of the panel display.

As the frequency is stored in Flash memory, it is persistent across design and hardware sessions. Cycling the NB2DSK01's power for example will result in the last set clock frequency, stored in the Flash memory, to be used at startup – regardless of whether that frequency was set by the firmware (through the GUI) or by Altium Designer.

The user-programmable clock has a default frequency of 50MHz. Note: Only the predefined frequencies for the programmable clock, based on the 20MHz fixed reference clock frequency, are available for selection. Should you wish a different frequency between 6 and 200MHz, this can be achieved via the Instrument Rack – NanoBoard Controllers panel, from within Altium Designer. Access this panel by double-clicking on the icon for the NB2DSK01, in the NanoBoard chain of the Devices view (View » Devices View).

Figure 14. Controls related to inclusion of boards into the Soft JTAG chain.

Figure 15. Controls to change the frequency of the motherboard's programmable system clock.


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Real Time Clock (RTC)

The GUI contains a screen for viewing/modifying the current date and time. This information is sourced from the NB2DSK01 motherboard's DS1391U-33 device – an SPI-compatible real-time clock (RTC).

To access clock controls (Figure 16), from the Home screen of the GUI touch the

icon, followed by the icon. Time is always displayed using the 24-hour format (e.g. 14:22). The date is always displayed in the format yyyy - mm - dd (e.g. 2007 - 12 - 04).

Simply touch the relevant field to expose controls for incrementing/decrementing the value of that field. Commit any changes by touching the icon.

Once the DS1391U-33 device is setup with the correct time and date, it will always reflect the correct time and date, even after a reset to default values, providing power to the device is not lost (i.e. NB2DSK01 motherboard powered off and the 3V Lithium battery is depleted).

Test Routines

A variety of test routines can be performed from the TFT LCD panel, specifically testing the integrity of key elements of the NB2DSK01 motherboard, including the host LEDs and the generic user switches.

Test routines (Figure 17) are accessed by pressing the icon on the Home screen of the GUI.

Simply select the test you wish to perform and follow the instructions on the panel. Navigation and selection is performed using the generic user switches, located directly below the panel. Note: When the daughter board FPGA has been programmed with a design, access to the Test Routines screen will be unavailable, with the icon put into a disabled state – .

Figure 16. Display and modification of time and date.

Figure 17. Accessing routines to test functionality of key motherboard resources.


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Revision History

Date Version No. Revision

17-Dec-2007 1.0 Initial release

15-May-2008 2.0 Updated for Altium Designer Summer 08

30-Aug-2011 - Updated template.

Software, hardware, documentation and related materials:

Copyright © 2011 Altium Limited.

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Documents

AP0156 Interacting With the Desktop NanoBoard NB2DSK01