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“Design for parallel and low power” Authors: Fabien Colas-Bigey1, [email protected] Albert Cohen2, [email protected] Chantal Couvreur3, [email protected] Luciano Lavagno4, [email protected] Eugenio Villar5, [email protected] Daniel Calvo6, [email protected] and Andrei Terechko6, [email protected] Affiliations: 1Thales Communications and Security, 2Ecole Normale Supérieure, 3Interuniversitair Micro-Electronica Centrum, 4Politecnico di Torino, 5University of Cantabria, 6Tedesys, 7Vector Fabrics Abstract The PHARAON project targets the development of two different sets of techniques and tools, both aiming at best exploiting the low-power capabilities of modern multi-core processors, tackling both the programming and runtime power management challenges mentioned above. The first set will directly impact the design of the application. The objective is to assist the designer in finding the most adequate software architecture taking into account hardware constraints. To do so, tools will be capable to evaluate the parallel structure of an application and propose improvements. A tool will also be capable to handle communications between different processors and generate the multi-processor embedded code. The second set of techniques and tools will impact the runtime behavior of the application. The objective is to adapt the performance of the platform, (frequency & voltage for example) in order to consume only the required energy. A reconfiguration system and a low power scheduler will be integrated with other run-time components on top of the platform. To demonstrate the efficiency of the developed techniques and tools, three demonstrators will be produced: 2 radio protocols with real-time reconfiguration and multi-stream capabilities, advanced 3D stereoscopic applications with real-time and high definition constraints.!
Parallel and Heterogeneous Architectures for Real-time ApplicatiONs
http://researchprojects.xwiki.com/xwiki/bin/view/PHARAON
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Objectives & Impact Demonstrators
[email protected] “New paradigms for embedded systems, monitoring and control towards complex system engineering”Project number 288307 / 36 Months
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Parallelisation toolchain andPerformances analysis
High Level System Description(UML Marte + C Code)
Addition of low power strategiesint main(void){int len = 128;FFT(buf,len);
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int main(void){
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int main(void){int len = 128;FFT(buf,len);
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int main(void){int len = 128;FFT(buf,len);
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Code Generator
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