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AnalyzingTimingA,eryousetthe4mingconstraintssuchasclocks,inputdelays,andoutputdelays,itisagoodideatousethecheck_4mingcommandtocheckfor4mingsetupproblemsand4mingcondi4onssuchasincorrectlyspecifiedgeneratedclocksandcombina4onalfeedbackloops.Thecommandchecksthe4minga?ributesofthecurrentdesignandissueswarningmessagesaboutanyunusualcondi4onsfound.
Thedefaultreportshowsthestartpoint,endpoint,pathgroup(clockdomain),pathtype(minimumdelay,maximumdelay,max_rise,min_fall,andsoon),theincrementalandcumula4ve4medelayvaluesalongthedataandclockpaths,thedatarequired4meatthepathendpoint,andthe4mingslackforthepath.
AnalyzingTimingUsingtheGUI,youcangeneratecolor-codeddiagramsshowingtheloca4onsofworst-case4mingcondi4onssuchaspathslack,cellslack,netcapacitance,clocklatency/transi4on,andcrosstalk.
AnalyzingPowerThereport_powercommandcalculatesandreportspowerforadesign.Thecommandusestheuser-annotatedswitchingac4vitytocalculatethenetswitchingpower,cellinternalpower,andcellleakagepower,anditdisplaysthecalculatedvaluesinapowerreport.
Repor4ngQualityofResultsYoucangenerateareportonthequalityofresults(QoR)forthedesigninitscurrentstatebyusingthecreate_qor_snapshotcommand(orbychoosingTiming>CreateQoRSnapshotintheGUI).Thiscommandmeasuresandreportsthequalityofthedesignintermsof4ming,designrules,area,power,conges4on,clocktreesynthesis,rou4ng,andsoon.
CellDensityMapTogenerateacelldensitymap,thetooldividesthelayoutintoagridofsquaresmeasuringfivestandard-cellheightsoneachside.Itfindstheareau4liza4onineachgridsquareandthencolor-codeseachsquareaccordingtotheu4liza4onvalue.Italsodisplaysahistogramshowingthenumberofgridsquaresineachoftheu4liza4onvaluebins.
Conges4onMapsAconges4onmapcanhelpyouvisualizethequalityofplacementwithrespecttotheavoidanceofrou4ngconges4on.
HierarchyVisualModeThehierarchyvisualmodeisadisplayofthedesignwithcellshighlightedandcolor-codedaccordingtoblockmembershiporlevelsofhierarchy
Clock-TreeVisualModeTheclocktreevisualmodehighlightstheflylinesandcellsofaclocktreeusingadifferentcolorforeachbufferlevelofthetree.Forexample,Figureshowstheconnec4onsinlevels0,1,and2ofthesys_clkclocktree,withthelevel0inyellow,level1inmagenta,andlevel2inblue.Thisdisplaycanhelpyouvisualizetheextentandapproximateroutelengthsoftheclocktree.
NetConnec4onsThenetconnec4onsinareavisualmodeletsyouvisualizethenetsenclosedinorcrossingaspecifiedrectangularareaofthedesignandexaminetheproper4esofthosenets.
NetConnec4onsThenetconnec4onsinareadisplaycapabilityletsyoudeterminethenettopologyinapar4cularregionandobservetheproper4esofthenetsinthatarea.Thisfeatureworkswithbothroutedandunrouteddesigns.Youcananalyzethenetsthatcrossaspecificareaandusetheinforma4ontochangethefloorplanoraddconstraintssuchasblockages.Forexample,excessivelocalnetsmightimplythatu4liza4onchangesareneeded,orexcessiveglobalorpass-throughnetsmightimplythatfloorplanorplacementconstraintchangesareneeded.
ClockTreeSynthesisDesignPrerequisites• Thedesignisplacedandop4mized.Usethecheck_legality-verbosecommandtoverifythattheplacementislegal.Runningclocktreesynthesisonadesignthatdoesnothavealegalplacementmightresultinlongrun4mesandreducedQoR.Thees4matedQoRforthedesignshouldmeetyourrequirementsbeforeyoustartclocktreesynthesis.Thisincludesacceptableresultsfor
• Conges4onIfconges4onissuesarenotresolvedbeforeclocktreesynthesis,theaddi4onofclocktreescanincrease
conges4on.Ifthedesigniscongested,you canrerunplace_optwiththe-conges4onand-efforthighop4ons,buttherun4mecanbelong.
• Timing• Maximumcapacitance• Maximumtransi4on4me
Toensurethattheclocktreecanberouted,verifythattheplacementissuchthattheclocksinksarenotinnarrowchannelsandthattherearenolargeblockagesbetweentheclockrootanditssinks.Ifthesecondi4onsoccur,fixtheplacementbeforerunningclocktreesynthesis.•Thepowerandgroundnetsareprerouted.•High-fanoutnets,suchasscanenables,aresynthesizedwithbuffers.
ClockTreeSynthesisLibraryPrerequisites•Anycellinthelogiclibrarythatyouwanttouseasaclocktreereference(abufferorinvertercellthatcanbeusedtobuildaclocktree)orforsizingofgatesontheclocknetworkmustbeusablebyclocktreesynthesisandop4miza4on.Bydefault,clocktreesynthesisandop4miza4oncannotusebuffersandinvertersthathavethedont_usea?ributetobuildtheclocktree.• Thephysicallibraryshouldinclude• Allclocktreereferences(thebufferandinvertercellsthatcanbeusedtobuildtheclocktrees)• Rou4nginforma4on,whichincludeslayerinforma4onandnon-defaultrou4ngrules• TLUPlusmodelsmustexist.
Extrac4onrequiresthesemodelstoes4matethenetresistanceandcapacitance.
AnalyzingTheClockTreeBeforerunningclocktreesynthesis,analyzeeachclocktreeinyourdesigntodetermineitscharacteris4csanditsrela4onshiptootherclocktreesinthedesign.Foreachclocktree,determine•Whattheclockrootis•Whatthedesiredclocksinksandclocktreeexcep4onsare•Whethertheclocktreecontainspreexis4ngcells,suchasclock-ga4ngcells•Whethertheclocktreeconverges,eitherwithitself(aconvergentclockpath)orwithanotherclocktree(anoverlappingclockpath)•Whethertheclocktreehas4mingrela4onshipswithotherclocktreesinthedesign,suchasinterclockskewrequirements•Whatthelogicaldesignruleconstraints(maximumfanout,maximumtransi4on4me,andmaximumcapacitance)are•Whattherou4ngconstraints(rou4ngrulesandmetallayers)are
Usethisinforma4onwhenyoudefinetheclocktreesandtovalidatethatthetoolhasthecorrectclocktreedefini4ons.
DefiningTheClockTreeThetoolusestheclocksourcesdefinedbythecreate_clockcommandastheclockrootsandderivesthedefaultsetofclocksinksbytracingthroughallcellsinthetransi4vefanoutoftheclockroots.Youcandesignateeitheraninputportorinternalhierarchicalpinasaclocksource.
DefiningTheClockRootA?ributeIftheclockrootisaninputport(withoutanI/Opadcell),youmustaccuratelyspecifythedrivingcelloftheinputport.Aweakdrivingcelldoesnotaffectlogicsynthesis,becauselogicsynthesisusesidealclocks.However,duringclocktreesynthesis,aweakdrivingcellcancausethetooltoinsertextrabuffersasthetooltriestomeettheclocktreedesignruleconstraints,suchasmaximumtransi4on4meandmaximumcapacitance.Ifyoudonotspecifyadrivingcell(ordrivestrength),thetoolassumesthattheporthasinfinitedrivestrength.IftheclockrootisaninputportwithanI/Opadcell,youmustaccuratelyspecifytheinputtransi4on4meoftheinputport.
Implemen4ngClockMeshesClockmeshesarehomogeneousshortedgridsofmetalthataredrivenbymanyclockdrivers.Thepurposeofaclockmeshistoreduceclockskewinbothnominaldesignsanddesignsacrossvaria4onssuchason-chipvaria4on,chip-to-chipvaria4on,andlocalpowerfluctua4ons.Aclockmeshreducesskewvaria4onmainlybyshor4ngtheoutputsofmanyclockdrivers.Figureshowsthestructureofaclockmesh.Thenetworkofdriversfromtheclockporttothemeshdriverinputsiscalledthepremeshtree.Thenetworkofshortedclockdriveroutputsiscalledthemesh.
Implemen4ngClockMeshesUsingclockmeshesprovidesthefollowingbenefits:•Smallskewvaria4on,especiallyforhigh-performancedesigns•Consistentdesignperformanceacrossvaria4ons•PredicableresultsthroughoutboththedesignstageandECOstagelater•Stabilityresul4ngfrommeshgridsbeingclosetoreceiversUsingclockmesheshasthefollowingdisadvantages:•Morerou4ngresourcesarerequiredtocreateclockmeshes•Higherpowerconsump4onduringtransi4onsontheparalleldriversdrivingthemesh
H-TreesAnH-treeisafractalstructurebuiltbydrawinganHshape,thenrecursivelydrawingHshapesoneachofthever4ces,asshowninFigure.Withenoughrecursions,theH-treecandistributeaclockfromthecentertowithinanarbitrarilyshortdistanceofeverypointonthechipwhilemaintainingexactlyequalwirelengths.Buffersareaddedasnecessarytoserveasrepeaters.Iftheclockloadswereuniformlydistributedaroundthechip,theH-treewouldhavezerosystema4cskew.Moreover,thetreestendtouselesswireandthushavelowercapacitancethangrids.
SpinesThespinesdrivelength-matchedserpen4newirestoeachsmallgroupofclockedelements.Iftheloadsareuniform,thespineavoidsthesystema4cskewofthegridbymatchingthelengthoftheclockwires.