1

Analysis of MEMS electrostatic energy harvesterselectrically configured as voltage multipliers

Binh Duc Truong, Cuong Phu Le and Einar Halvorsen, Member, IEEE

Abstract—This paper presents the analysis of an efficient alter-native interface circuit for MEMS electrostatic energy harvesters.It is entirely composed by diodes and capacitors. Based onmodeling and simulation, the anti-phase gap-closing structure isinvestigated. We find that when configured as a voltage multiplier,it can operate at very low acceleration amplitudes. In addition,the allowed maximum voltage between electrodes is barely limitedby the pull-in effect. The parasitic capacitance of the harvesterand non-ideal characteristics of electronic components are takeninto account. A lumped-model of the harvesting system has beenimplemented in a circuit simulator. Simulation results show thatan output voltage of 22 V is obtained with 0.15 g input acceler-ation. The minimum necessary ratio between the maximum andminimum capacitances of the generators which allows operationof the circuit, can be lower than 2. This overcomes a crucialobstacle in low-power energy harvesting devices. A comparisonbetween the voltage multiplier against other current topologiesis highlighted. An advantage of the former over the latter isto generate much higher saturation voltage, while the minimumrequired initial bias and the minimum capacitance ratio in bothcases are in the similar levels.

Index Terms—MEMS, electrostatic energy harvester, voltagemultiplier, low-power system, diode-capacitor network

I. INTRODUCTION

V IBRATION-BASED energy harvesting canprovide reliable alternative power sources for

emerging miniaturized-electrical devices such as implantmedical/wireless sensors [1], [2]. As a key element connectingthe harvester and storage component or electrical load, powerelectronic interface circuitry has gained significant interestin recent years. Abundant research on circuit topology withfunctions of voltage regulation, optimal power extractionand damping control for energy harvesting systems has beenconducted and presented [3]–[7]. In this paper, we focus onthe power electronics for micro capacitive energy harvester.

Several topologies of power electronic interface circuitfor MEMS electrostatic energy harvesters are reported. Forinstance, Yen et al. proposed a simplified circuit in whicha charge pump was used with a fly-back circuit to storeand transfer extracted energy [8]. The major drawback ofthis architecture is that the storage capacitor acts as parasiticcapacitance to the energy converter, reducing the net powerharvested. The power consumption of the control unit of theswitch is also a challenging concern as it must be supportedby the generator, even in ASIC implementations [9], [10].

B. D. Truong, C. P. Le and E. Halvorsen are with the Depart-ment of Microsystems, University College of Southeast Norway, e-mail:Binh.Truong@usn.no.

Manuscript received Moth Day, Yeah; revised Moth Day, Year.

In addition, the use of bulky inductor is not applicable tominiaturization of the harvesting system.

Besides the switched-inductor topologies, diode-capacitorvoltage multipliers are widely used for converting an AC inputvoltage into a DC output voltage. Based on Bennet’s doublerof electricity, de Queiroz et al. proposed an inductor-less andswitch-less doubler circuit [11], [12]. The major advantage ofthis topology is a simple and robust implementation. However,the circuit requires a ratio Cmax/Cmin between maximum andminimum capacitances of the variable capacitors to be greaterthan 2. This is a critical challenge in practice since MEMSharvesters tend to exhibit small variable capacitances, limitedby standard fabrication processes and device size.

An advanced topology for vibration electrostatic energyharvesters was recently proposed by Lefeuvre et al. [13], [14].An argument based on theoretical analysis using a rectangularQ-V cycle suggests that this voltage multiplier can operatewith a minimum necessary capacitance ratio lower than 2.However, one may have concerns regarding the accuracy ofthis assumption for the complex dynamic behavior of thecircuit. Also, both simulations and experiments were for amacro-scale rotating variable-capacitor with Cmin = 45 pFand Cmax = 155 pF which clearly has Cmax/Cmin muchlarger than 2.

This paper presents a new adaption of a voltage multipliercircuit to MEMS energy harvesting. This capacitor-diode net-work is based on the Greinacher’s voltage doubler which is thebasic stage of a multiplier circuit first proposed by Greinacherin 1920 [15]. Since the micro energy harvesting systemtypically provides low output voltage that is not acceptable toswitching converters, the multiplier topology is also a potentialsolution to initially boost such voltage to start-up the activeelements of converter circuit [16]–[18]. A complete lumpedmodel including both mechanical and electrical domains isinvestigated. Parasitic capacitance of the generators and diodelosses are taken into account. System dynamics are analyzedusing a SPICE simulator. The performance of the introducedmultiplier configuration is then compared to several circuits ofthe same family [13], [19].

II. ENERGY HARVESTER MODEL

Figure 1 shows the 2D geometry of the electrostatic energyharvester, which is used as a vehicle to explore the operationof a voltage multiplier configuration. The device includestwo fixed electrodes attached to the frame and two variableelectrodes on the proof mass suspended by four non-linearsprings. The maximum displacement Xmax is limited by me-chanical end-stops. Though an in-plane anti-phase gap-closing

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17

2

Vib

rati

on

dir

ecti

onNon-linear spring

Fixed electrode

Anchor

En

d-s

top

En

d-s

top

Fixed electrode

CI(x)

CII(x)

Proof

mass

g2

g1

Fig. 1. Anti-phase gap-closing vibration energy harvester.

asymmetric transducer is early used in sensing applications[20], [21], it is the first time introduced as an energy generatorthrough this paper. An advantage of such structure is the capa-bility to obtain large range of capacitance variation with smalldisplacement, which allows the device to operate efficiently atrelatively low input excitations. Meanwhile, the pull-in voltageis kept to an remarkably high value due to the anti-phasebehavior of the two transducers. These characteristics makethe structure interesting to investigate.

The capacitances CI and CII as functions of the proof massdisplacement are

CI/II

(x)= Cp + C1/2

(x), (1)

C1

(x)= C0

1(1 + x

g1

)(1− x

g2

) , (2)

C2

(x)= C0

1(1− x

g1

)(1 + x

g2

) (3)

where C0 is the nominal capacitance of transducers, Cp

presents for the parasitic capacitance. The gaps between mov-able electrode and fixed electrodes g1 and g2 must be satisfiedthe condition Xmax < g1 < g1 + 2Xmax < g2 so that theanti-phase characteristics is fulfilled ∂CI

∂x∂CII

∂x < 0.The nonlinear squeeze-film damping is proved to be es-

sential to capture the device behavior [22], [23]. Meanwhile,the hardening restoring force could be useful to increasethe device stability during operation. Along with the powerconversion circuitry, the effect of the mechanical end-stopson the performance of a harvesting system is significant andcannot be ignored [24]. Therefore, all of them needs to betaken into account in device modeling. The dynamic of thespring-mass-damper system is then given by

mx+B(x)x+ Fm

(x)+ Fe

(x)+ Fs

(x)= F (4)

where m is the inertial mass and F = mA cos(ωt)

is theexternal force. Including the squeeze-film damping of thegap-closing capacitor structure [25] and an additional lineardamping, the total damping force of the harvesters is B

(x)x,

where

B(x) = bl +bn(

1 + xg1

)3 +bn(

1− xg2

)3+

bn(1− x

g1

)3 +bn(

1 + xg2

)3 . (5)

mB(x) Fm(x)

22

i

1 i p

e

1 1

2i

dqdx C x C

F x

C2(x)

C1(x)

Cp

CpD1

D2

D3

D4

D5

Cb1

Cb2

Cs V0

t=0

+

–

Fs(x)

cos( )mA t

+ –

+ –

+

–

+

–

x

Fig. 2. Lumped-model of electrostatic energy harvester configured as avoltage multiplier.

Fm is the mechanical restoring force, which we consider onthe Duffing-spring polynomial form

Fm

(x)= k1x+ k3x

3. (6)

The electrostatic force is represented by

Fe

(x)=

1

2q21

d

dx

1

C1

(x)+ Cp

+1

2q22

d

dx

1

C2

(x)+ Cp

(7)

where q1 and q2 are the charges on the two transducers. Astray capacitance Cp in parallel with the variable capacitanceis also included in the model. Fs is the impact force betweenthe movable mass and the rigid end-stops at the ultimatedisplacement |x| > Xmax, which can be simplified as [26]

Fs

(x)= ksδ + bsδ (8)

where ks is the impact stiffness, bs is the damping coefficientaccounting for the impact loss and δ = |x| − Xmax is thedeformation displacement between the proof mass and the end-stops during impact.

Based on the above equations, the equivalent circuit forthe anti-phase gap-closing electrostatic energy harvesters isshown in Figure 2. Along with that is the proposed interfacecircuit, which includes two, namely, biasing capacitor Cb1

and Cb2 and five low-leakage diodes D1, D2, D3, D4 andD5 (abbreviation, D1−5). The output of the interface circuitis connected to a storage capacitor Cs where the generatedenergy is stored. Cs is initially precharged to a voltage of V0.All model parameters are listed in Table I and are chosen closeto the parameters of the MEMS electrostatic energy harvestersin [27].

III. OPERATION AND DYNAMICS OF THE TWO-STAGEVOLTAGE MULTIPLIER

In order to investigate the potential benefit of the circuit,the MEMS transducers are designed so that the capacitancevariation ratio is

η =Cmax + Cp

Cmin + Cp= 1.55. (9)

3

TABLE IMODEL PARAMETERS

Parameters ValuesProof mass, m 30.4 mgLinear stiffness, k1 675.1 Nm−1

Hardening nonlinear stiffness, k3 2.7e7 Nm−3

Slide-film air damping, bl 2.5e-5 Nsm−1

Squeeze-film air damping, bn 2.7e-5 Nsm−1

Nominal capacitance, C0 36.26 pFParasitic capacitance, Cp 8.5 pFLower gap between movable and fixed electrodes, g1 16 µmUpper gap between movable and fixed electrodes, g2 40 µmMaximum displacement, Xmax 6.5 µmImpact stiffness, ks 3.36e6 Nm−1

Impact damping, bs 0.44 Nsm−1

Bias capacitance, Cb1/b2 0.5 nFStorage capacitance, Cs 10 nF

−40 −30 −20 −10 0 10 20 30 4025

30

35

40

45

50

55

60

Displacement [µm]

Capacitan

ce[pF]

C1(x)

C2(x)

−Xmax

Cmin

Cmax

Xmax

Fig. 3. The capacitance variation in anti-phase gap-closing transducers.

It is also the minimum ratio that is required for the harvesterto work as a voltage multiplier. Note that the critical ratio foroperation of the Bennet’s doubler is ηcr = 2, or even largerwhen the electrical losses are included. The variable capacitorshere vary between Cmin = 30.79 pF and Cmax = 52.53 pF.The capacitance variation of the two transducers are shown inFigure 3.

A dynamic model of the low-leakage diode BAS716 [28]is used for simulations in LT-SPICE, taking into accountnon-ideal properties such as built-in junction voltage, leakagecurrent and p-n junction capacitance. The SPICE model ismuch more complicated and realistic than constant-voltage-drop model or piecewise linear model. The capacitance valueof the storage capacitor is first arbitrarily chosen large enoughCs = 10 nF to minimize the ripple voltage at the DCoutput, while the biasing capacitance is kept much smallerCb1 = Cb2 = Cb = 0.5 nF to minimize start-up time.

Figure 4 shows waveforms of the voltages across capacitorsand currents through diodes together with the proof massdisplacement in the same time interval. The voltages acrossCb1/b2 and Cs increase slowly as functions of period oftime, while that of variable capacitors have AC characteris-tics depending on the amplitude and frequency of the inputacceleration. Use of the non-ideal diode model results in

2289 2289.5 2290 2290.5 2291 2291.5 2292

-6

-4

-2

0

2

4

6

t/T [s]

Displa

cem

ent[7

m]

2289 2289.5 2290 2290.5 2291 2291.5 2292

10

15

20

25

t/T [s]

Voltage

[V]

VC1(x)

VC2(x)

VCb1

2289 2289.5 2290 2290.5 2291 2291.5 2292

0

0.1

0.2

0.3

0.4

0.5

t/T [s]

Curr

ent[n

A]

ID1

ID2

2289 2289.5 2290 2290.5 2291 2291.5 2292

5

10

15

20

25

30

t/T [s]

Voltage

[V]

VC1(x)

VCb1

VCb2

Vout

2289 2289.5 2290 2290.5 2291 2291.5 2292

0

0.1

0.2

0.3

0.4

0.5

t/T [s]

Curr

ent[n

A]

ID3

ID4

ID5

0t 1t 2t 3t 4t

Fig. 4. Simulated waveforms of the proof mass displacement, voltages acrosscapacitors and currents through diodes. The input acceleration amplitude is

A = 0.5 g. The driving frequency is kept at the constant value f0 =√

k1m

=750 Hz and the initial bias voltage is V0 = 12 V.

4

0 2 4 6 8 10 120

5

10

15

20

25

30

35

Time [s]

Outputvoltage

[V]

A=0.15 g: VCb1

A=0.25 g: VCb1

A=0.15 g: Vout

A=0.25 g: Vout

Fig. 5. The time evolution of the voltage across Cb1 and Cs denoted asVC1

and Vout respectively, for different input acceleration A = 0.15 g andA = 0.25 g.

strongly complex behavior of the diode currents. To analyzethe complicated operation of the circuit, a sequence of fourstages can be identified during a cycle.

In the first stage, from t0 to t1, C1(x)(C2(x)

)start

increasing (decreasing) from the minimum (maximum) value.Conditions VC2 + VCb1

> VC1 > VC2 , VC1 > VCb1+ VCb2

and Vout + VCb2> VC1

> Vout are satisfied. All the diodesare blocked and the charges of C1 and C2 can be treated asconstants.

The second stage is from t1 to t2. At the beginning, VC1

continues decreasing while VC2is increasing. When VC2

>VC1

, D1 is conducting and C1 is charged by C2. Also, VCb1+

VCb2> VC1

leads to conduction of the diode D3 and thecurrent flows from Cb1, Cb2 to C1. This stage ends when C1

reaches the minimum value Cmin and VC1 starts to rise.In the next stage from t2 to t3, all diodes D1−5 are reverse-

biased, for the same reasons as above. However, C1 now isdecreasing from the maximum value Cmax and the voltageacross it increases again. The opposite happens to C2.

In the final stage from t3 to t4, VC1first continues increasing

while VC2decreases. This situation prevails until VC1

becomeslarger than VC2

+ VCb1and the diode D2 begin to conduct

transferring charge from C1 and C2 to Cb1. Then, the voltageacross C1 changes only very slightly. In addition, whenVC1 > Vout + VCb2

, the current flows from C1 and Cb2 to Cs

while D4 is conducting. When C1 reaches Cmax, all conditionsmentioned in the first stage occur and a new cycle starts. Notethat the condition Vout > VC1

is rarely satisfied. The currentthat transfers the charge from Cs to C1 through the diode D5

is small and negligible. However, D5 still plays a vital rolefor pre-charging C1 at the very beginning of operation. Inprinciple, D5 can be disconnected through a switch in seriesafter the first several cycles. This technique could result inhigher saturation voltage [29], but is not our objective in thispaper. Therefore, we choose to keep D5 as part of the voltagemultiplier, so that the attractive simplicity of the circuit is notcompromised.

Figure 5 shows the time evolution of the output voltage with

0.9 0.95 1 1.05 1.1 1.150

5

10

15

20

25

30

35

40

45

50

f/f0

Saturation

voltage

[V]

A=0.15 gA=0.20 gA=0.25 gA=0.30 gA=0.50 gA=0.75 gA=1.00 gA=1.25 gA=1.50 g

Fig. 6. Variation of the saturation voltage with different acceleration ampli-tudes and frequencies.

drive frequency f = f0 = 12π

√k1m = 750 Hz, acceleration

amplitudes A = 0.15 g and A = 0.25 g and initial pre-chargevoltage V0 = 8 V. The energy stored in Cs initially increases.The steady state is obtained after several cycles of operationand the accumulated voltage Vout is saturated at a certainlevel due to the effect of the electromechanical coupling [30].Higher voltages result in stronger electrostatic forces causinga decrease of the proof mass displacement, and therefore η.Higher input acceleration leads to a larger value of saturationvoltage Vsat. For instance, A = 0.25 g gives Vsat = 29.36 Vwhile that of A = 0.15 g is Vsat = 22.32 V.

If the variable capacitor C1 is replaced by a sinusoidal inputvoltage source v(t) = Vin cos(ωt) and all losses in diodesare neglected, the value of Vout is supposed to be two timeshigher VCb1

and therefore Vout = 4Vin. However, the relationbecomes much more complicated when the input source isthe actual voltage generated by MEMS energy harvester, i.e.VC1 , since this voltage is now dependent on the mechanicalvibration and may have time-varying amplitude. For example,the ratio of Vout/VCb1

are 1.61 and 1.58 for A = 0.25 g andA = 0.15 g respectively. Simulation results also show thatA = 0.12 g is the minimum required acceleration for efficientoperation of the circuit, at the resonant frequency f = f0.

Figure 6 shows variation of the output voltage at steadystate obtained from simulations for each pair of accelerationamplitude and frequency (A, f ). At a particular acceleration,when the vibration frequencies are within a certain rangearound the mechanical resonance, the system harvests energyand the voltage increases towards saturation. For frequenciesoutside this range, the necessary condition η ≥ 1.55 is notsatisfied due to small proof mass displacement. All the storedenergy from precharge of the capacitor will then be dissipatedresulting in zero output voltage after a certain time. It is clearthat larger excitation strengths create a wider band of usefuldrive frequencies.

In order to understand the characteristics observed in Figure6, we first consider dynamics of the proof mass at steady state.A comparison of normalized signal waveform x/Xmax for

5

9 9.002 9.004 9.006 9.008 9.01 9.012

−1

−0.5

0

0.5

1

Time [s]

x/X

max

A=0.15 gA=0.35 g

End-stop

End-stop

Fig. 7. Comparison of the proof mass displacement at steady state for differentacceleration amplitudes.

0 0.5 1 1.5 20.8

0.85

0.9

0.95

1

1.05

1.1

Acceleration amplitude A [g]

f r=

f eff/f

0

Fig. 8. Dependence of the ratio between the effective resonant frequency andthe resonant frequency on input acceleration.

different acceleration amplitudes is shown in Figure 7 whereA = 0.15 g and A = 0.35 g are taken as examples. Furthersimulation results show that, in the range of A = 0.15 g−0.30g, the displacement barely reaches the maximum value Xmax

and hence Fs = 0. For higher excitation levels, the electrostaticforce drives the proof mass toward (closer to) one side ofthe end-stop and the impact force between them periodicallyoccurs.

We now examine an effective stiffness Keff of the anti-phasegap-closing device at steady state, which is given by

Keff = <e

∫ T

0FME

(t)e−jωtdt∫ T

0x(t)e−jωtdt

, (10)

where FME = Fm+Fe+Fs. The signals of x(t), Fm

(t), Fe

(t)

and Fs

(t)

are extracted from simulations. The ratio betweenthe effective resonant frequency feff =

√Keff/m/2π and the

mechanical resonant frequency is then

fr =feff

f0=

√Keff

k. (11)

Figure 8 shows the changes of fr versus acceleration am-plitude. In case of A ∈ [0.15 g, 0.30 g], the resonant peakof the transducer is shifted downwards along with the riseof bias voltage due to the softening effect of the nonlinearelectrostatic force. Therefore, lower input frequencies resultin higher voltages. When A > 0.30 g, the impact forcedominates the electrostatic force and performs the hardeningnonlinearity. The resonant peak thus increases in accordancewith acceleration amplitudes and the output responses tend toincrease with higher frequencies.

0 5 10 15 20 25 30 35 400

10

20

30

40

50

60

Time [s]

Vout[V

]

Cb = 0.07 nF

Cb = 0.70 nF

Cb = 7.00 nF

Fig. 9. The time evolution of the output voltage Vout across Cs for differentvalues of Cb.

10−1

100

101

101

102

Cb [nF]

Start−

up[s]

10−1

100

101

20

30

40

50

60

Vsat[V

]

Fig. 10. Start-up time for different values of Cb.

Our previous work showed that the saturation voltage ofthe Bennet’s doubler circuit does not depend on the initial biasV0, and can be optimized by increasing the mechanical qualityfactor and adjusting stiffness [30]. These statements are stillvalid with the voltage multiplier configuration. In this paper,we continue exploring other aspects of the circuit such as effectof the biasing capacitor on start-up time (i.e., the time durationfrom the beginning to when the output voltage is saturated)and dependence of the ripple voltage on the storage capacitor.It is clearly that minimum start-up time and minimum ripplevoltage would be desirable.

For simplification, all fixed capacitances are chosen equalCb1 = Cb2 = Cb. Figure 9 depicts the effect of Cb on theevolution of output voltage over time. The biasing capacitanceCb almost does not affect the saturation voltage Vsat, but hasstrong influence to the required time duration until Vsat isachieved. Therefore, the start-up time can be minimized withrespect to Cb so that the circuit can produce the same expectedamount of the DC voltage faster. The start-up time used todistinguish between the transient and steady states is deter-mined once the output voltage reaches 98% of the saturation

6

10−2

10−1

0

0.5

1

1.5

Cs [nF]

Ripple

[V]

10−2

10−1

30

35

40

45

50

Vsat[V

]

Fig. 11. The output DC voltage and the corresponding ripple with differentvalues of Cs.

voltage. Simulation results obtained for a wide range of Cb areshown in Figure 10. The saturation voltage can be consideredunchanged, while the shortest start-up time tmin ≈ 7.5 s isfound around Cb = 0.4 nF. Larger capacitances result inlonger changing time for each multiplier-stage and thus slowdown the start-up, but too small ones even increase the timesharply due to the undesired dynamic loading condition. Fromanother perspective, Cb has a significant impact on the cycle-to-cycle multiplication factor z of the output voltage. Theargument is similar to the one that was used to explain theinfluence of the storage capacitor on z for the Bennet’s doublercircuit [11], [30].

Simulation results for the voltage ripple and the corre-sponding saturation voltage versus the storage capacitancesare shown in Figure 11. The ripple is determined as (Vmax −Vmin)/2, where Vmax and Vmin are the highest and lowestpeaks of the output voltage at steady state. Meanwhile, thesaturation voltage is Vsat ≈ (Vmax + Vmin)/2. The ripple isfound to be about 35 mV when Cs = 0.5 nF and increase withdecrease of Cs. Vsat is slightly reduced when Cs < 50 pF isused. Since our objective is to obtain a DC output voltage,it is desirable to choose as large a value of the capacitanceCs as possible in order to minimize the ripple. However, theanalysis presented in Figure 10 also holds for Cs, meaning thatlarger capacitances result in longer start-up time. Therefore, agood trade-off is needed here to keep both the ripple and start-up time at reasonable levels that are dependent on particularrequirements of the output specifications.

At the input acceleration A = 0.12 g and the drive fre-quency f = f0, simulations obtained for the low-losses diodeBAS716 show that V0 = 6 V is the minimum required initialbias for efficient operation of the circuit, so-called criticalvoltage Vcr. In previous work we proved that the use of aMOSFET connected in a diode-configuration as an alternativeto the p+n diode could significantly reduce Vcr. Moreover,the diode-connected MOSFET is also a convenient option forintegrated circuits. With the same MOSFET parameters givenin [30], the value of Vcr can be further lowered to 1.9 V.

IV. GENERALIZED N-STAGE VOLTAGE MULTIPLIER

C2(x)

C1(x)

CpCp D1

D2D3

D4

Cb1

Cb2

Cs V0

t=0Cb[2(N-1)]

Cb3

D2N

D2N-1

D2N+1

Fig. 12. Multi-stage voltage doubler circuit - Configuration (I).

The introduced circuit can be generalized to an N-stagevoltage doubler as depicted in Figure 12, where N is aninteger and N ≥ 3. Each intermediate stage j ∈ [2, N − 1]includes two biasing capacitors Cb[2(j−1)], Cb[2(j−1)+1] andtwo rectifier diodes D2j−1, D2j. The fly-back diode D2N+1 isconnected between the storage capacitor Cs of the final stageand the variable capacitor C1. D2N+1 plays exactly the samerole as D5 does in Figure 2.

C2(x)

C1(x)

Cp

Cp D1

D3

Cb1

Cb2

Cb[2(N-1)]

Cb(2N-3)

D2N-1

C2(x)

C1(x)

Cp

Cp

D2

D4

Cb1

Cb2

Cs

Cb[2(N-1)]

Cb3

D2N

Stage II

Stage IV

Fig. 13. Operation of multi-stage voltage doubler circuit: stage II and IV.

Despite of complex dynamics of the voltage multiplierconfiguration, we can also simplify and divide its operationover one cycle into four sequence stages that are similar tothe Section III. Since all diodes Di (i ∈ [1, 2N + 1]) areblocked in the first and the third stages, we consider twomain topologies regarding directions of the parallel currentsacross diodes and capacitors. Both are represented in Figure13. Though diode D2N+1 is required for initially chargingC1, its conduction is insignificant during operation of theharvesting system, and therefore is disregarded. In the firsttopology, only D2j−1 (j ∈ [1, N ]) are conducting. Chargesare pumped from capacitor C1 and Cb[2(k−1)−1] into C2 andCb[2(k−1)] (k ∈ [2, N ]) respectively. This stage stops when

7

Q

VO Vs (VC1)max

QL=CmaxV

QR=C

minV

Saturation

Fig. 14. Succession of charge-voltage cycles of C1

the proof mass displacement reaches the maximum valuex = Xmax. The second topology corresponds to discharge ofC2 and Cb[2(k−1)] into Cb[2(k−1)−1] and Cs due to conductionof diodes D2j. Until x = −Xmax, all Di are blocked again anda new cycle starts. Observing that the currents flow in parallelbranches in the conducting regime and the doubler stages areconnected in series, such a voltage multiplier configuration canbe classified as a parallel-series charge-pump or parallel-seriesswitched/diode-capacitor network.

Based on the dynamic simulation, the operation of capacitorC1(x) can be approximated by a Q-V cycle depicted in Figure14. In the left and the right sides, the Q-V diagram is boundedby the lines corresponding to maximum and minimum valuesof the variable capacitance: QL = CmaxV and QR = CminV .The area of each parallelogram is roughly equal to the har-vested energy per cycle [31], and is modified over cyclesin a complicated manner. It is very small at the beginningand gradually increases in the conversion regime. When theoutput voltage across the storage capacitor Cs approaches thesaturation voltage Vout ≈ Vsat, the shape of the Q-V cyclebecomes thinner. At n −→ ∞, it degenerates to the line,meaning that the mechanical energy is no longer captured.Here, n is the number of cycles. The similarity was observedfrom the Q-V cycle represented for the charge-pump circuitwith resistive fly-back [32], [33].

0 0.5 1 1.5 215

20

25

30

35

40

45

50

55

60

65

A [g]

Vsat[V

]

N=2

N=3

N=4

N=5

N=6

N=7

Fig. 15. Output voltage at saturation versus input acceleration with differentvalue of the number of stages N .

Figure 15 shows the saturation voltage of the circuit versus

0 0.5 1 1.5 20

5

10

15

20

25

30

35

A [g]

Lr

N=2

N=3

Under effectof impact

Under effectof impact

Fig. 16. Dependence of the ratio between average power lost in both electricaldamping and impact force and mechanical damping on input accelerationamplitude

0 1 2 3 4 5 6 7 8

1

1.5

2

2.5

Number of stages N

ηmin

Fig. 17. Minimum value of the capacitance ratio ηmin versus number ofstages N .

the input accelerations for various number of stages N .Considering the two-stage voltage doubler N = 2, there isa rapid increase of the saturation voltage corresponding toincrease of A ∈ [0.15 g, 0.30 g]. However, higher accelerationamplitudes result in very slight rise of Vsat. Similar behaviorsare also observed for N ≥ 3. To understand the reason for thisphenomenon, we consider the relation between the work doneagainst both electrostatic and impact forces and the energy lostin mechanical damping per cycle, which is characterized bythe ratio

Lr =

∫ T0[Fe

(t)+ Fs

(t)] x(t)dt∫ T

0B(t) x(t)2 dt

(12)

where the electrostatic force Fe

(t), the impact force Fs

(t), the

time-dependent damping B(t)

and the proof mass velocityx(t)

are extracted from simulations at steady state. Thevariation of Lr versus acceleration amplitude for N = 2 andN = 3 are depicted in Figure 16 as examples. Sufficiently highaccelerations (i.e., A > 0.3 g with N = 2 and A > 1.0 g withN = 3) result in collisions between the proof mass and theend-stops even at steady state. The coincidence between thefigure 15 and 16 shows that the energy losses due to impactsmake the saturation voltage increase very little with A.

In addition, there is a range of input excitation that N-stagemultiplier circuit with N ≥ 3 performs worse than the caseof N = 2. For instance, the 3-stage voltage multiplier onlygives more benefit on the saturation voltage than the 2-stageconfiguration when A is equal or greater than a certain valuecalled critical acceleration, in detail A ≥ Acr = 0.94 g. Itis also observed that Acr decreases with increase of N , e.g.Acr ≈ 0.84 g with N = 7. All those behaviors are due toeffect of the strong nonlinear electrostatic force.

8

One important criteria to evaluate and highlight the per-formance of the voltage multiplier is its capability to workwith micro-scale energy harvesters or low power systems. Theminimum value of the capacitance ratio ηmin for differentN is given in Figure 17, with input acceleration A = 0.5g. In the ideal case, the prerequisite condition for operationof the circuit is that η must be greater than the thresholdη∗ = N+1

N [34]. It is interesting to note that η∗ and ηmin canbe decreased by increasing N . When the electrical losses aretaken into account, ηmin is slightly higher than η∗. Even so, thepresented configuration is a promising solution to overcomethe challenging obstacle of MEMS devices which typicallyhave η < 2 due to the limitation of device size, micro-fabrication process and presence of parasitic capacitance.

Based on the analyses above, it can be concluded that withthe use of the anti-phase gap-closing devices, 2-stage voltagemultiplier is a better option for transducers with higher ratioη operating at low input acceleration amplitudes while 3- ormore-stage ones are prefer in the opposite cases.

V. COMPARISON OF DIFFERENT TOPOLOGIES OF THEVOLTAGE MULTIPLIER

Due to mentioned problems, there are only a few circuitsfor which successful realizations, at least in theory, havebeen reported so far. A topology proposed by Lefeuvre etal. [13] was given that the minimum necessary ratio η forits operation can be lower than 2. The argument is basedon theoretical analysis of the rectangular Q-V cycle alone,there are no concrete evidences in both dynamic simulationsand measurements. Instead, the experimental validations werecarried out using a single rotating variable capacitor drivenby a DC motor, with nearly Cmax = 45 pF and Cmin = 155pF. From the same group, a similar contribution was madein [18], where Cmin = 25 pF and Cmax = 125 pF. It isclearly that the ratio Cmax/Cmin in both cases is much lagerthan 2. In the same manner, the work of Karami et al. [19]presented a series-parallel charge-pump conditioning circuitswhich are generalized from the Bennet’s doubler. However,this contribution is limited to an electrical domain study only.One may concern about the effect of the electromechanicalcoupling on the full dynamics of the energy harvesters.

In this paper, we choose to compare our voltage multiplierconfiguration with the one in [13]. The series-parallel voltagedoubler [19] is explored and discussed afterward, due to somelimitations that are revealed by our simulation results.

Besides the circuit shown in Figure 12, an anti-phasestructure may provide us another configuration where eachtransducer produces a single output voltage, see Figure 18. Theinsignificant anti-phase AC signals referred as ripple voltagesare neglected. The two output voltages can be considered equalV1 = V2, which is the symmetric characteristics of the circuit.Similarly, we can divide the circuit configurations proposed byLefeuvre et al. into two varieties that are depicted in Figure19. Each cell 2, N is an adaptation of the Greinacher voltagedoubler. In configuration (IV) we also get V

′

1 = V′

2 . For afairly comparison, we classify four different configurationsinto two group: (I)/(III) and (II)/(IV), as each group sharesthe same number of electrical outputs.

C2(x)

C1(x)Cp Cs1

t=0

Cp Cs2

V0

t=0

+

–

+

–

V1

V2

Fig. 18. Symmetric multi-stage voltage doubler circuit - Configuration (II).

C2(x)

C1(x)

Cp

Cp Cs

V0

t=0

Cell 1 Cell 2 Cell N

+

–

/

sV

(a) Congifuration (III)

C1(x)

Cb

Cp Cs1

V0

t=0

C2(x)Cp

Cbt=0

Cs2

+

–

+

–

/

1V

/

2V

(b) Congifuration (IV)

Fig. 19. Schematic diagram of the self-biased interface circuits [13].

Figure 20 and 21 shows the evolution of output voltage for

9

0 0.2 0.4 0.6 0.8 10

10

20

30

40

50

t/tend

Outp

utvoltage[V

]

(III)(I)

Fig. 20. Time evolution of output voltage: configuration (I) and (III).

0 0.2 0.4 0.6 0.8 10

10

20

30

40

50

t/tend

Outp

utvoltage[V

]

(II)

(IV)

Fig. 21. Time evolution of output voltage: configuration (II) and (IV).

configuration (I)/(III) and (II)/(IV) respectively, with the inputacceleration A = 1.5 g, drive frequency f = f0, initial biasV0 = 8 V and the number of stage N = 3. It should be notedthat η = 1.55 is not enough for efficient operation of bothconfigurations (II) and (IV) with N = 2. The end-time ofsimulations are t(I)end = 2.8, t

(II)end = 65, t

(III)end = 1.3, t

(IV)end = 4

seconds. A major disadvantage of the configuration (II) overthe others is its long start-up time, which however can beshortened by carefully choosing the biasing/storage capacitorand increasing V0. For example, the start-up time of theconfiguration (II) reduces from 30.6 s with V0 = 8 V andCb = 0.5 nF to 7.4 s with V0 = 9 V and Cb = 0.2 nF.We see that the output voltage of configuration (I) saturates atmuch higher value than that of configuration (III). The samephenomenon is observed when configuration (II) is comparedto configuration (IV).

1 2 3 4 5 6 7 80

10

20

30

40

50

60

70

Vsat[V

]

Number of stages N

A=1.5 g

A=2.0 g

Vs - (I)

V′

s - (III)

Fig. 22. Saturation voltage Vsat versus number of stages N : comparisonbetween configuration (I) and (III).

1 2 3 4 5 6 7 80

10

20

30

40

50

60

70

Vsat[V

]

Number of stages N

A=1.5 g

A=2.0 g

V1/2 - (II)

V ′

1/2 - (IV)

Fig. 23. Saturation voltage Vsat versus number of stages N : comparisonbetween configuration (II) and (IV).

These above simulations are extended for various stagenumber N with different input acceleration amplitudes. Thesaturation voltage results are presented in Figure 22 and 23.In both cases, the introduced topology shows the superiorityin comparison with previous work by Lefeuvre et al. Not onlythat, the remarkable gap of saturation voltage between the twotopologies also raises with increase of N . The number of stagehas a strong influence on the saturation voltage of the circuits.For configurations (III) and (IV), Vsat decreases as N increasesdue to parasitic effect of the constituent capacitor of each stageand power losses in diodes. Though the configuration (I) canovercome this challenge, the voltage gain is less than linear asmore stages are introduced. The behavior of the configuration(II) is a bit more complicated, however, the voltage changesare small in general.

The difference in performance between the configurations(I) and (III) can be explained by their physical mechanisms.For configurations (I), each stage is a modified voltage doubler,it also acts as an intermediate charge reservoir. An amount ofenergy stored in stage j−th is transferred into stage (j+1)−thin the next operation cycle, which keeps going until it reachesand then is stored in Cs. Meanwhile, only a small amountof charge is transferred from Cs into C1, making the voltageacross C1 to be built up very slowly. Considering configuration(III), in contrary, the harvested energy is pumped from C1

to Cs through the intermediate capacitor C2 alone. However,both C1 and C2 are charged by a built-in voltage multipliercircuit that may include up to N cells. This process causesthe voltages across the two variable capacitors to increase toofast, leading to rapid rise of the electrostatic force and decreaseof the proof mass displacement as a consequence. Hence, theoutput voltage saturates at a lower level. That is also the reasonwhy configuration (I) tend to have longer start-up time thanconfiguration (III). Similar behaviors can be correspondinglyinferred for the other configurations (II) and (IV).

The minimum required values of η and V0 for four con-figurations are compared in pairs in Table II. Since thedifferences between them are not so significant, advantages

10

TABLE IICOMPARISON OF MINIMUM REQUIRED η AND V0 BETWEEN FOUR

CONFIGURATIONS WITH N = 2

Configuration (I) (III) (II) (IV)ηmin 1.55 1.44 1.68 1.62(V0)min 6.0 4.5 10.0 10.0

of the proposed topologies are not overshadowed.

C1(x)

CpD1

D2

Cb

V0

t=0

D3

D5

Cs

C2(x)

Cp

D4 D6

Fig. 24. Series-parallel charge-pump circuit with N = 2, by Karami et al.[19].

10−2

10−1

100

101

0

5

10

15

20

Time [s]

Outputvoltage

[V]

V0 = 7 V

V0 = 10 V

V0 = 5 V

V0 = 6 V

V0 = 4 V

V0 = 3 V

V0 = 9 V

V0 = 8 V

Fig. 25. Evolution of the output voltage for different values of the initial biasV0 ranging from 3 to 10 V.

The topology reported by Karami et al. is shown in Figure24 for N = 2, adapted from [19]. The same switch-capacitorconfiguration can be found in [35]. Simulation results showthat the circuit cannot operate with η = 1.55. Instead, theminimum required ratio of the capacitance variation is muchhigher than that, ηmin = 2.1. Unlike other voltage multipliercircuits, the saturation voltage here strongly depends on theinitial bias, but the voltage gain Vsat/V0 is very small, e.g.,Vsat ≈ 22 V when V0 = 20 V. Moreover, Vsat/V0 > 1 only ifV0 > 6 V.

The saturation voltage could be significantly improved whenthe device with high ratio of η = 2.61 is used. The correspond-ing maximum displacement is now Xmax = 11 µm. The timeevolution of the output voltage across the storage capacitor Cs

is presented in Figure 25 with various values of the initial biasV0. Since higher V0 results in higher Vsat, the investigationof the minimum pre-charge voltage is irrelevant in this case.Such a phenomenon has not been revealed in [19] since onlyelectrical domain was investigated. These results confirm the

essential role of the electromechanical coupling on the circuitperformance, which cannot be ignored in studying the systemdynamics.

VI. CONCLUSION

This paper presents a new configuration of a voltage mul-tiplier for MEMS electrostatic energy harvesters. The anti-phase gap-closing transducers were modeled and utilized inthe study. Without switches and inductive elements, the circuitproved to be suitable for ultra-low power implementation.Effect of the component imperfections such as parasitic ca-pacitance of the transducer and diode non-idealities on thesystem performance are taken into account. The influence ofbiasing capacitances on start-up time and the dependence ofthe ripple voltage on the storage capacitor were explored. Theanalyses shown that the saturation voltage depends on both thenonlinearities of the electrostatic force and the impact forceat high acceleration amplitudes. In comparing to previouslyreported circuits that are also based on the voltage doubler, thealternative topology presented in this paper can operate witha ratio of capacitance η lower than 2. The minimum value ofη can be reduced by increasing the number of doubler stagesN . The introduced configuration has shown the superiority onthe saturation voltage compared to earlier work published inthe literature.

With the assessment that the electrostatic force of the in-plane overlap-varying harvester is proportional to the proofmass displacement (i.e., which is very different from the anti-phase gap-closing devices), performance of such a transducerstructure when configured as N-stage voltage multiplier isinteresting for further investigation.

ACKNOWLEDGMENT

Financial support from the Research Council of Norwaythrough Grant no. 229716/E20 is gratefully acknowledged.

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PLACEPHOTOHERE

Binh Duc Truong received the B.E. degree inMechatronics from the Ho Chi Minh City Universityof Technology, Vietnam, in 2012 and the M.Sc.degree in Micro- and Nano System Technologyfrom the Buskerud and Vestfold University College,Norway, in 2015. He is currently pursuing the Ph.D.degree with Department of Microsystems, UniversityCollege of Southeast Norway, focusing on MEMSelectrostatic energy harvesters and wireless powertransfer systems.

PLACEPHOTOHERE

Cuong Phu Le Cuong Phu Le received the B.S.degree in telecommunications engineering from theUniversity of Technology, Ho Chi Minh City, Viet-nam, in 2005, the M.S. degree in microsystem tech-nology from Vestfold University College in Horten,Norway in 2009 and the Ph.D. degree in microsys-tems technology from University of Oslo, Norwayin 2013. He is currently a research scientist inDepartment of Microsystems, University College ofSoutheast Norway in Horten. His current researchinterests include microsystem design, modelling and

MEMS vibration energy harvesting.

PLACEPHOTOHERE

Einar Halvorsen (M’03) received the Siv.Ing. de-gree in physical electronics from the NorwegianInstitute of Technology (NTH), Trondheim, Norway,in 1991, and the Dr.Ing. degree in physics from theNorwegian University of Science and Technology(NTNU, formerly NTH), Trondheim, Norway, in1996. He has worked both in academia and the mi-croelectronics industry. Since 2004, he has been withUniversity College of Southeast Norway in Horten,Norway, where he is a professor of micro- andnanotechnology. His current main research interest

is in theory, design, and modelling of microelectromechanical devices.