Analysis of Instruction-level Vulnerability to Dynamic Voltage and

Temperature Variations

‡Computer Science and Engineering, UC San Diego

http://variability.org http://mesl.ucsd.edu

Abbas Rahimi‡, Luca Benini†, Rajesh Gupta‡

†Dipartimento di Elettronica, Informatica e Sistemistica, Università di Bologna

http:// micrel.deis.unibo.it

Outline

• Dynamic variations• Dynamic variability among pipeline stages• Methodology and quantifying instruction-

level vulnerability (ILV)• Classification of instructions• Adaptive clock scaling utilizing ILV• Conclusion

2

Motivation: Increasing Dynamic Variations

3

• Increasing dynamic environmental variations in ambient condition such as temperature fluctuations and supply voltage droops.

• Dynamic Variations contain high-frequency and low-frequency components which occur locally as well as globally across the die.

4

1ns

4ns3ns

5ns

Voltage

Temperature

Aging

Process

HW SW

Instruction

What will be happened for instructions when we have

dynamic voltage and temperature variations?

Instruction is a bridge to software side

Quantifying effects of operating conditions

• We analyze the effect of a full range of operating conditions on the performance and power of the LEON-3 processor compliant with the SPARC V8 architecture.

5

• Specifically, we used a temperature range of -40°C−125°C, and a voltage range of 0.72V−1.1V.

• Dynamic variations cause the critical path delay to increase by a factor of 6.1X. Consequently, a large conservative guard-band into the operating frequency is needed to ensure the error-free operation in presence of the dynamic variations.

Critical path (ns)

6

Variability among pipeline stages

0

2

4

6

8

10

12

14

16

Fetch Decode Reg. acc. Execute Memory Write back

Num

ber o

f fai

led

path

s

x 10000 0.72V 0.88V 1.10V

0

1

2

3

4

5

6

7

8

Fetch Decode Reg. acc. Execute Memory Write back

Num

ber o

f fai

led

path

s

x 10000 -40 � C 0� C 125 � C

The execute and memory parts are very sensitive to voltage and temperature variations, and also exhibit a large number of critical paths in comparison to the rest of processor. Similarly, we anticipate that the instructions that significantly exercise the execute and memory stages are likely to be more vulnerable to voltage and temperature variations Instruction-level Vulnerability (ILV)

VDD= 1.1V

T= 125°C

7

Methodology for ISA-level Vulnerability

Post-Synthesis Simulation for 32-bit RISC Leon3

Processor

Voltage variation

Temperature variation

SPARC V8 instructions with random operands

Probability of failure( PoF) for every instruction

@ different (Voltage, Temperature, Frequency)

ILV to dynamic variations

Quantifying ILV

• To quantify the ILV to voltage and temperature variations, we define the probability of failure (PoF) for each instructioni – where Ni is the total number of clock cycles in Monte Carlo simulation

which takes to execute instructioni with random operands

– Violationj indicates whether there is a violated stage at clock cyclej or not (If any of the analyzed stages has one or more violated flip-flop at clock cyclej, we consider that stage as a violated stage at cyclej)

8

N

1

1PoF ViolationN

If any stage violates at cycleViolation

otherwise

ii j

i j

jj

1

0

9

Classification of instructions, cont.Probability of failure of ISA at 0.88V, while varying temperature

1st

2nd

3rd

• Instructions are partitioned into three main classes: 1st Logical & arithmetic; 2nd Memory; 3rd Multiply & divide.

• The 1st class shows an abrupt behavior when the clock cycle is slightly varied, mainly because the path distribution of the exercised part by this class is such that most of the paths have the same length, then we have a all-or-nothing effect, which implies that either all instructions within this class fail or all make it.

Classification of instructions

10

Probability of failure of ISA at 0.72V, while varying temperature

All instruction classes act similarly across the wide range of operating conditions: as the cycle time increases gradually, the PoF becomes 0, firstly for the 1st class, then for the 2nd class, and finally for the 3rd class:

PoF (3rd Class) ≥ PoF (2nd Class) ≥ PoF (1st Class)

Adaptive clock scaling utilizing ILV

11

• We define an adaptive clock cycle for each class of instructions to mitigate the conservative guard-banding, not only within a fix process corner, but also across corners.

• The ILV a valuable mechanism to alleviate the guard-banding: I. within a fixed corner, by acquiring the knowledge about which class of

instructions is running, the processor can adapt the guard-banding accordingly.

II. across every corner, processor adjusts its guard-banding by using a low-overhead variability observer .

• Therefore, adaptive clock scaling can decide on the clock speed of the processor at a very fine grain: • just looking at the fetched instructions and keeping track of their entry

into the stages of the pipeline • and at the same time monitoring the current corner with a low-

overhead monitoring hardware.

Effectiveness of Adaptive clock scaling

12

• This figure shows how a procedure consists of various classes of instructions can benefit by this technique under different operating conditions: the performance improvement when processor runs a procedure only consists of specific classes, in comparison to the traditional worst-case design.

0

1

2

3

4

5

6

Spe

edup

(Voltage=%, Temperature=%) variations in comparison to the worst-case corner

1st and 2nd class (logical & memory instructions)

1st, 2nd, and 3rd class (logical, memory & multiply-divide instructions)

Conclusion

• The concept of instruction-level vulnerability to dynamic voltage and temperature variations is defined.

• Based on that, all exercised instruction in the integer pipeline of LEON-3 are partitioned into three classes for the full range of operating condition: – (i) the logical and arithmetic instructions – (ii) the memory instructions – (iii) the multiply and divide instructions.

• Leveraging this classification in conjunction with less intrusive variability observers, not only provides us a great opportunity to enhance processor performance by 1.1X-5.5X, in TSMC 65nm technology.

13

14

Thank you!

http://mesl.ucsd.edu http:// micrel.deis.unibo.it

http://variability.org