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Bashir Al-Hashimi. Reuben Wilcock. [email protected]. [email protected]. Analogue Filter IP Cores for Design Reuse. Outline. Introduction and Motivations Analogue Filter IP Core Design Example Results Concluding remarks. Introduction. System on Chips (SoC) employ IP cores - PowerPoint PPT Presentation
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Electronic Systems Design Group
Department of Electronicsand Computer Science
University of Southampton, UK
Analogue Filter IP Cores for Design
Reuse
Bashir [email protected]@ecs.soton.ac.uk
Reuben Wilcock
Reuben Wilcock ASP 2002
University of Southampton, UK
Slide 2
Outline
• Introduction and Motivations
• Analogue Filter IP Core Design
• Example Results
• Concluding remarks
Reuben Wilcock ASP 2002
University of Southampton, UK
Slide 3
Introduction
• System on Chips (SoC) employ IP cores
• Analogue IP core design is demanding– Difficult to trade as high level description– Correct operation depends on many factors
Important to redesign for particular specifications and process to ensure
functionality
Reuben Wilcock ASP 2002
University of Southampton, UK
Slide 4
Analogue Filter IP Core Design
• What are the considerations?
Circuit design technique
Filter Methodology
Automation
Reuben Wilcock ASP 2002
University of Southampton, UK
Slide 5
Solution ?
Circuit Design Technique
• Requirements– Simple, easily designed blocks – No high quality passive components– Compatible with present and future processes– High performance
• Solution: Switched Current– Designs based on current mirrors
– No linear passive components
– Current mode allows low Vdd
– High performance cells availableCgs1 Cgs2
M2M1
Iin Iout
S1
Reuben Wilcock ASP 2002
University of Southampton, UK
Slide 6
Solution ?
Filter Methodology
• Requirements– Suitable for Switched Current– Regular structures and simple design procedure– Based on LC ladder to inherit low sensitivity– Bilinear transform so Nyquist limit can be approached
• Solution: Wave Filters– Ideal for Switched Current
– Easily designed blocks
– Based on LC ladders
– Bilinear transformA22=0
2220R00
R10
R20 =
10
00 R01
R11
R21 =
11
2101 R02
R12
R22
12
02
z-1 z-1
B22A00
B00
-z-1
Vi
Ri L1
C1 C2 Ro
+v-
Reuben Wilcock ASP 2002
University of Southampton, UK
Slide 7
Automation
• Requirements:– Increase productivity– Transistor level
simulations– Optimisation
Step 1
Design referenceLC filter
Interactiveiteration
LC values fromtables
Idealsimulations
Step 2
Derive wave filter& coefficients
Automaticoptimisation[Yufera ‘94]
Samplingfrequency ratio
Idealsimulations
Step 3
Design memorycell [Hughes ‘00]
Interactiveoptimisation
Fs, Bias (Power)Mod, Vgt
BSimsimulations
Step 4
Put filter togetherand verify
Revisit 1-3 asnecessary
Results fromsteps 1-3
Filter response(BSim)
Solution ?
• Solution: SKILL tool– Automate hand-
calculations
– Integrated in Cadence
– Manual/Automatic optimisation loops
Step 5
Layout(using pCells)
Reuben Wilcock ASP 2002
University of Southampton, UK
Slide 8
Step 1: Passive Filter Design
• De-normalise values• Frequency response
• Choose filter type/function/order• Normalised component values
Reuben Wilcock ASP 2002
University of Southampton, UK
Slide 9
Step 2: Wave Filter Design
• Optimise [Yufera ’94]
• Frequency response from behavioural models
• Decide cutoff/sample ratio• Coefficients are calculated
Reuben Wilcock ASP 2002
University of Southampton, UK
Slide 10
Step 3: Memory Cell Design
• S2I memory cell [Hughes ’00]• Trade off design parameters• First cut design calculated• DC, transient simulations• Optimise for gm, Cgs, Ctot,
Switch Ron and settling
Reuben Wilcock ASP 2002
University of Southampton, UK
Slide 11
Step 4: Complete Filter Design
• Save all design variables, dimensions and coefficients to a single file
• Schematic representing entire transistor level design is opened
• Spectre RF used to give an AC response in minutes
• Revisit steps 1 – 3 as necessary
Reuben Wilcock ASP 2002
University of Southampton, UK
Slide 12
Schematic Hierarchy
• Parameter passing with pPar(“”)
• Hierarchy from top to transistor level
Reuben Wilcock ASP 2002
University of Southampton, UK
Slide 13
Conclusions
• Switched Current has good potential for IP cores
• Wave is suitable as a filter methodology
• Automation tools should be integrated into powerful CAD packages
• Our tool allows a designer to rapidly develop Switched Current analogue filter cores.
• Future work will involve – Extending the filter library
– Including Class AB cell as alternative to S2I
– May include layout (step 5)
Reuben Wilcock ASP 2002
University of Southampton, UK
Slide 14
Contact
Reuben Wilcock
Electronic Systems Design
Department of Electronics and Computer Science
University of Southampton
United Kingdom