Analog System Review and Status Wes Grammer NRAO September 24-26, 2012EOVSA Prototype Review1

EOVSA Prototype Review 1

Analog System Review and Status

Wes GrammerNRAO

September 24-26, 2012


Outline

• Top-level subsystem description• Module-level design and construction status

– 2-meter Front End assembly– Front End auxiliary electronics cabinet– Downconverter module– LO Distribution modules– Timing Generation and Distribution module– Correlator Clock Generation module

• Rack-level design & cabling• Budget and current schedule



Analog Subsystem Diagram



2-Meter Front End Assembly



2-Meter Front End Block Diagram


T

S W 1O v e rt e m p

TE A s s e m b ly

F A N + F A N - T E C + T E C -

TE C 1L a ird

D A -0 7 5 -2 4 -0 2 -0 0 -0 0

C P 1

2 0 d B C o u p le r

1 8 0 1 2 0K ry t a r

C P 2


1 8 0 1 2 0K ry t a r

S P L 1

2 -wa y S p lit t e rW e in s c h e lW A 1 5 1 5

1

2

I N

D 1

3 0 d B E N RN o is e wa v eN W 1 8 G -3 0 -C S

R F +2 4 V

V RF In1-18 GHz

H RF In1-18 GHz

-12V

A 1

3 0 d B g a in , 2 . 5 d B N F

A F S 4 -0 0 1 0 1 8 0 0 -2 5 -1 0 P -1 2 V -4M it e q+1 0 d B m P o _ 1 d B

+24V

W D M 1F . O . D ip le x e rO p t ila b

P A D 1

-3 d B

B W -S 3 -2 W 2 6 3 +M in i-C k t s

+3 . 3 V

0 / 10 dB

A 4

3 1 d B g a in 5 d B N F

C A 1 1 8 -4 5 5 AC ia o W ire le s s+2 0 d B m P o _ 1 d B

H / VFO Out

0 -3 1 d B

A 5


C A 1 1 8 -4 5 5 A DC ia o W ire le s s+2 0 d B m P o _ 1 d B

+24V (TE)+12V (FAN)

F I L T1

1 8 G H z L o wp a s sR e a c t e l8 L 0 -X1 8 G S 2 2

A 2

3 0 d B g a in , 2 . 5 d B N F

A F S 4 -0 0 1 0 1 8 0 0 -2 5 -1 0 P -1 2 V -4M it e q+1 0 d B m P o _ 1 d B

M&C I/O

A 7

D u a l d if f . b u f f e r

Ethernet I/O

TE A s s e m b ly

F A N + F A N - T E C + T E C -

TE C 2L a ird

D A -0 7 5 -2 4 -0 2 -0 0 -0 0

[7]

P A D 2

-3 d B

B W -S 3 -2 W 2 6 3 +M in i-C k t s

F I L T2

1 8 G H z L o wp a s sR e a c t e l8 L 0 -X1 8 G S 2 2

E TH [ 8 . . 1 ]

[7]

F O O U T

DC PowerInputs A&B

O P T_ TX1F . O . Tra n s m it t e r

L T-2 0O p t ila b+V

I N

R S 2 3 2

O P T_ TX2F . O . Tra n s m it t e r

L T-2 0O p t ila b+V

I N

R S 2 3 2

[1]

0 / 10 dB

A 3


C A 1 1 8 -4 5 5 AC ia o W ire le s s+2 0 d B m P o _ 1 d B

V P O L _ P O U T

H P O L _ P O U T

[2] [3]

TR I G +

[4]

[5] [6]

+12V "A"

TR I G

[3][2][1] [5]

[4]

[6]

t

R T1TS E N S E

TR I G -

+2 4 V

Power and Signal I/O

U 2

E m b e d d e d M P UR M C 4 0 0 0R a b b it

G N D +3 . 3 V

I O [ 1 . . 2 0 ]

E TH [ 1 . . 8 ]

TR I G

0.1 - 2V out

+12V "B"

F E _ D C / S I G [ 1 0 . . 1 ]

F E _ +1 2 V _ A / B [ 4 . . 1 ]

F E _ C -D C -1 [ 4 . . 1 ]

F E _ C -D C -2 [ 4 . . 1 ]

Trigger

H

VA N T1D u a l L o g -P e r.TE C O M8 0 5 9 2 0 -0 0 2

Front End Module Assembly Enclosure, 2-Meter Antenna

0-31 dB

A 6


C A 1 1 8 -4 5 5 A DC ia o W ire le s s+2 0 d B m P o _ 1 d B

TE Assy.DC Power Inputs

EOVSA Prototype Review 6September 24-26, 2012


Half-side Interior View,2-meter Front End Assembly



20 GHz Laser Transmitter



Optical Mux / Demux



Front End Module Design and Construction Current status

• Most components on hand, except low-loss coax cables, BPF, bulkhead fiber adapter.

• Module mechanical design 50% done; will contract Segars Engineering to complete.

• Apex mounting plate design is TBD (Segars )• Module wiring diagram is TBD• Ethernet cable is under construction (Kjell N.)• Front End interface board circuit design 90% done; PCB

layout, fab and assembly TBD. Parts ordering TBD.• Software interface document, embedded firmware and

control GUI are TBD.



Front End Auxiliary Cabinet



Auxiliary Cabinet Wiring Diagram


+12V-C_RET

TSW_1

120 VAC Input

-12V-A_OUT

+24V-C_OUT

RT_1

+24V-C_RET

-12V-A_RET

NEUT

RT_2

R L 1R E L A Y S P S T

Weidemuller0536260000

1 4

1 3

A 1A 2

LINE A R DC S UP P LY

+ 12V @ 4A

P S 1

TDK-Lambda NNS-3012

+S

+V

-V

-SG

L

NFront End Cable FE_+12V_A/B

Pin_'A'

Pin_'B'

Pin_'C'

C O N N 2

Te rm in a l B lo c k 6 -p inM c M a s t e r-C a rr9 1 3 0 K 4 5

1

2

3

4

5

6

1

2

3

4

5

6

+24V-B_OUT

Pin_'D'

LINE A R DC M ODULE

-12V @ 0.4A

P S 3

Acopian 12EB40

O U T+

O U T-

A C

A C

+24V-B_RET

Pin_'E'

Pin_'F'

LINE A R DC M ODULE

+ 24V @ 0.2A

P S 4

Acopian 24EB20

O U T+

O U T-

A C

A C

S W ITCHE DDC S UP P LY

+ 24V @ 10A

P S 5

Phoenix Contact 2866323

+V

-V

L

N

Pin_'G'

GND

Pin_'H'


+ 12V @ 4A

P S 2

TDK-Lambda NNS-3012

+S

+V

-V

-SG

L

N

+12V-B_OUT

+12V-B_RET C O N N 3

Te rm in a l B lo c k 1 2 -p in9 1 3 0 K 4 8M c M a s t e r-C a rr

1

2

3

4

5

6

1

2

3

4

5

6

7

8

9

1 0

1 1

1 2

7

8

9

1 0

1 1

1 2

Pin_'J'

F 1

2 A , S lo w B lo w

FE_C-DC-1[4..1]

FE_C-DC-2[4..1]

FE_+12V_A/B[4..1]

FE_DC/SIG[10..1]

Pin_'K'

Pin_'C'

Pin_'B'

Pin_'A'

Pin_'D'

Front End Cable FE_DC/SIG

+12V-A_OUT

+12V-A_RET

F 24 A , S lo w B lo w

DC-to-DCCONV E RTE R

+ 12V @ 2A

P S 6

Phoenix Contact 2320018

+V

-V

I N +

I N -

+TRIG

-TRIG

RT_2

RT_1

C O N N 1

Te rm in a l B lo c k 1 2 -p in7 6 1 8 K 6 1 8M c M a s t e r-C a rr

1

2

3

4

5

6

1

2

3

4

5

6

7

8

9

1 0

1 1

1 2

7

8

9

1 0

1 1

1 2

LINELINE

P W M TE CNTLR

+ 24V@ 15A

C TR L 1

Laird TC-XX-PR-59

+TE MS V 3 1

-TE MS V 3 3

+V D CS V 2 1

C O MS V 2 2

N TCTS 1 -1

N TCTS 1 -2

R E TTS -3

TRIG+

NEUT

Differential Trigger Input (from Auxiliary Cabinet)

Pin_'A'

GND

Pin_'C'

Pin_'B'

Pin_'A'

Pin_'D'

Pin_'B'

Pin_'C'

Pin_'D'

Front End Cable FE_C-DC #1

Front End Cable FE_C-DC #2

TRIG-

TSW_2

RT_2

+12V-C_OUT



Auxiliary Cabinet Design and Construction Current status

• Nearly all components on hand; two Lambda supplies on backorder, opt. RX units in transit.

• Wiring of first cabinet is well underway• All 4 power and signal cables completely specified, parts

on hand at OVRO (Kjell to build)• 1PPS fiber patch cords on order; will arrive ~9/28• Outdoor analog fiber drop cables on order; will arrive

~11/1. • Ethernet cable under construction (Kjell N.)• Multifiber cable termination inside cabinet TBD



Downconverter Module



Downconverter Block Diagram (1 of 2)


[14]

[9]

[14]

[9]

[6]

[6]

1st IF20-20.5 GHz

1st IF20-20.5 GHz

LO1 (21.5-38 GHz)

2nd IF0.65-1.15 GHz

A 2

3 0 d B g a in , 3 . 3 d B N F

C A 1 1 8 -4 5 7 DC ia o W ire le s s

+1 0 d B m P o _ 1 d B

2nd IF0.65-1.15 GHz

[6]

[6]

H _ P in

V _ P in

A 1 1

D u a l d if f . a m p

H _ I N

M&C I/O

LO2 (21.15 GHz)

V _ I N

V In-32 dBm

M&C I/O RS-485

H In-32 dBm

V Out-5 dBm[1]

[3]

[2]

[4]

H Out-5 dBm

LO1 In+2 dBm

LO2 In 0 dBm

[7]

[8]

[9]

[10]

[11]

[9]

[5]

[5]

[2][1]

[3]

[4]

[6]

[6]

O P T_ R X2F O R e c e iv e r

L R -3 0O p t ila b

+V

O U T

R S -2 3 2

P A D 9

-3 d B

S A 3 0 1 5 -0 3F a irv ie w

A 1 0

2 8 d B g a in+1 6 d B m P o _ 1 d BC ia o W ire le s sC A 0 1 -2 4 4 4

M 4

D o u b le -B a l. M ix e rM a rk iM 1 R -0 7 2 6 L S

R F

LO

I F

F I L T3

0 . 6 5 -1 . 1 5 G H z B P FQ M ic ro wa v e1 0 1 9 2 8

4 -B it D ig it a l A t t e n u a t o r

A TN 2

0 - 1 5 d B a t t e n .J F W 5 0 P -1 9 3 4

I N O U T

P A D 1 0

-3 d B

S A 3 0 1 5 -0 3F a irv ie w

S P L 1

1 0 -4 0 G H z S p lit t e rP 2 K 9 AA TM

1

2

S

A 5

1 7 d B g a in , 6 d B N F+1 8 d B m P o _ 1 d BM a rk i A -1 8 4 4

U 1


O [ 1 . . 1 4 ]M B _ I

M B _ O

A 31 7 d B g a in , 6 d B N F+1 8 d B m P o _ 1 d BM a rk i A -1 8 4 4

Downconverter Module Assembly Enclosure

P A D 4

-3 d B

B W -S 3 -2 W 2 6 3 +M in i-C k t s

P A D 3

-3 d B

B W -S 3 -2 W 2 6 3 +M in i-C k t s

M 1

D o u b le -B a l. M ix e rM a rk i M 9 -0 9 4 2 L N

R F

LO

I F

A 7

2 8 d B g a in , 1 . 3 d B N F+1 0 . 5 d B m P o _ 1 d BTe le d y n e / C o u g a rA C -1 2 8 6 C

F I L T4


P A D 2

-3 d B

B W -S 3 -2 W 2 6 3 +M in i-C k t s


A TN 1

0 - 1 5 d B a t t e n .J F W 5 0 P -1 9 3 4

I N O U T

I S O 2

2 0 -2 3 G H z I s o l.A Ti2 0 -2 3A TM

F I L T1

2 0 -2 0 . 5 G H z B P FR e a c t e l

5 C 0 -2 0 . 2 5 G -X5 0 0 S 2 2

Analog SM FiberInput from AntennaFront End Assembly

V Pol In1-18 GHz

F I L T2

2 0 -2 0 . 5 G H z B P FR e a c t e l

5 C 0 -2 0 . 2 5 G -X5 0 0 S 2 2


L R -3 0O p t ila b

+V

O U T

R S -2 3 2

A 4


A 6


A 8


M 3


R F

LO

I F

A 9


P A D 1

-3 d B

B W -S 3 -2 W 2 6 3 +M in i-C k t s

[13]M 2


R F

LO

I F

P A D 7

-3 d B

S A 3 0 1 5 -0 3F a irv ie w

P A D 8

-3 d B

S A 3 0 1 5 -0 3F a irv ie w

S P L 2

2 -2 6 . 5 G H z S p lit t e r6 0 2 0 2 6 5K ry t a r

1

2

S

I S O 1

2 0 -2 3 G H z I s o l.A Ti2 0 -2 3A TM

W D M 1D ip le x e rO p t ila b

L O 1

M B U S _ I N

S M F I n p u t

H _ O U T

V _ O U T

L O 2

M B U S _ O U T

H Pol In1-18 GHz

[12]

[12]

0.1 - 2V out

[13]

C P 1


Z F D C -1 0 -1 8 2 -S +M in i-C irc u it s

C P 2



A 1

3 0 d B g a in , 3 . 3 d B N F


+1 0 d B m P o _ 1 d B

P A D 1 1

-3 d B

S A 3 0 1 5 -0 3F a irv ie w

P A D 1 2

-3 d B

S A 3 0 1 5 -0 3F a irv ie w


Downconverter Block Diagram (2 of 2)


[14]

[9]

[14]

[9]

[6]

[6]

1st IF20-20.5 GHz

1st IF20-20.5 GHz

LO1 (21.5-38 GHz)

2nd IF0.65-1.15 GHz

A 2

3 0 d B g a in , 3 . 3 d B N F


+1 0 d B m P o _ 1 d B

2nd IF0.65-1.15 GHz

[6]

[6]

H _ P in

V _ P in

A 1 1

D u a l d if f . a m p

H _ I N

M&C I/O

LO2 (21.15 GHz)

V _ I N

V In-32 dBm

M&C I/O RS-485

H In-32 dBm

V Out-5 dBm[1]

[3]

[2]

[4]

H Out-5 dBm

LO1 In+2 dBm

LO2 In 0 dBm

[7]

[8]

[9]

[10]

[11]

[9]

[5]

[5]

[2][1]

[3]

[4]

[6]

[6]


L R -3 0O p t ila b

+V

O U T

R S -2 3 2

P A D 9

-3 d B

S A 3 0 1 5 -0 3F a irv ie w

A 1 0


M 4


R F

LO

I F

F I L T3



A TN 2

0 - 1 5 d B a t t e n .J F W 5 0 P -1 9 3 4

I N O U T

P A D 1 0

-3 d B

S A 3 0 1 5 -0 3F a irv ie w

S P L 1

1 0 -4 0 G H z S p lit t e rP 2 K 9 AA TM

1

2

S

A 5


U 1


O [ 1 . . 1 4 ]M B _ I

M B _ O

A 31 7 d B g a in , 6 d B N F+1 8 d B m P o _ 1 d BM a rk i A -1 8 4 4

Downconverter Module Assembly Enclosure

P A D 4

-3 d B

B W -S 3 -2 W 2 6 3 +M in i-C k t s

P A D 3

-3 d B

B W -S 3 -2 W 2 6 3 +M in i-C k t s

M 1


R F

LO

I F

A 7


F I L T4


P A D 2

-3 d B

B W -S 3 -2 W 2 6 3 +M in i-C k t s


A TN 1

0 - 1 5 d B a t t e n .J F W 5 0 P -1 9 3 4

I N O U T

I S O 2

2 0 -2 3 G H z I s o l.A Ti2 0 -2 3A TM

F I L T1

2 0 -2 0 . 5 G H z B P FR e a c t e l

5 C 0 -2 0 . 2 5 G -X5 0 0 S 2 2

Analog SM FiberInput from AntennaFront End Assembly

V Pol In1-18 GHz

F I L T2

2 0 -2 0 . 5 G H z B P FR e a c t e l

5 C 0 -2 0 . 2 5 G -X5 0 0 S 2 2


L R -3 0O p t ila b

+V

O U T

R S -2 3 2

A 4


A 6


A 8


M 3


R F

LO

I F

A 9


P A D 1

-3 d B

B W -S 3 -2 W 2 6 3 +M in i-C k t s

[13]M 2


R F

LO

I F

P A D 7

-3 d B

S A 3 0 1 5 -0 3F a irv ie w

P A D 8

-3 d B

S A 3 0 1 5 -0 3F a irv ie w

S P L 2

2 -2 6 . 5 G H z S p lit t e r6 0 2 0 2 6 5K ry t a r

1

2

S

I S O 1

2 0 -2 3 G H z I s o l.A Ti2 0 -2 3A TM

W D M 1D ip le x e rO p t ila b

L O 1

M B U S _ I N

S M F I n p u t

H _ O U T

V _ O U T

L O 2

M B U S _ O U T

H Pol In1-18 GHz

[12]

[12]

0.1 - 2V out

[13]

C P 1



C P 2



A 1

3 0 d B g a in , 3 . 3 d B N F


+1 0 d B m P o _ 1 d B

P A D 1 1

-3 d B

S A 3 0 1 5 -0 3F a irv ie w

P A D 1 2

-3 d B

S A 3 0 1 5 -0 3F a irv ie w


Downconverter Module Interior Layout



Downconverter Front/Rear Panels



Downconverter Module Interface PCB



Downconverter Module Design and Construction - Current status

• All components in, except one 2.92mm cable• Module mechanical design complete, metal

work on order. Assembly drawings TBD.• Need to generate module wiring diagram;

mechanical assembly of 1st module will begin ~ Oct. 8.

• Downconverter interface board in assembly stage, firmware development and GUI TBD.

• Rack DC power cables under constructionSeptember 24-26, 2012


LO Distribution Module



LO Distribution Subsystem: LO1


E TH -A [ 8 . . 1 ][4]

10 MHz Ref In

L O 1 -A _ A N T1

L O 1 -B _ A N T1

[5]

S W _ M O N [ 1 . . 1 6 ]From LO Interface PCB S W _ S E L [ 1 . . 1 6 ]

[6]

LO1 Outputs21.5 - 38 GHz

L O 1 -A _ A N T1

[6]

M&C I/OEthernet

L O 1 -A _ A N T2

[3]

L O 1 _ S E L _ A N T1

[1]

T T LD r iv e r

S W 1 3

CI N 1

I N 212

G +V

L O 1 -A _ A N T3

L O 1 -A _ A N T4

LO1-A

RF Sy nthesizer

21.5 - 38 GHz Out0 to +10 dBm

H it t it e H M C -T2 2 4 0

R F O U T

R E F I N

I / O [ 1 . . 8 ]

T T LD r iv e r

S W 1 1

CI N 1

I N 212

G +V

L O 1 -A _ A N T5

L O 1 -A _ A N T6

T T LD r iv e r

S W 2

CI N 1

I N 212

G +V

P A D 2

-3 d B

2 1 0 9 -3A TM

L O 1 -A _ A N T7

L O 1 -A _ A N T8

T T LD r iv e r

S W 7

CI N 1

I N 212

G +V

L O 1 -A _ A N T9

L O 1 -A _ A N T1 0

P A D 1

-3 d B

2 1 0 9 -3A TM

T T LD r iv e r

S W 1 2

CI N 1

I N 212

G +V

T T LD r iv e r

S W 1 4

CI N 1

I N 212

G +V

L O 1 -A _ A N T1 1

L O 1 -A _ A N T1 2

L O 1 -A _ A N T1 3

T T LD r iv e r

S W 8

CI N 1

I N 212

G +V

L O 1 -A _ A N T1 4

T T LD r iv e r

S W 4

CI N 1

I N 212

G +V

A 1

3 0 d B g a in , 9 d B N F+2 9 d B m P o _ 1 d BQ u in s t a rQ P W -2 1 3 8 2 9 3 0 -0 0

L O 1 -A _ A N T1 5

L O 1 -A _ TE S T

L O 1 -A _ A N T5

L O 1 -B _ A N T5

T T LD r iv e r

S W 9

CI N 1

I N 212

G +V

L O 1 _ S E L _ A N T5L O 1 -A _ A N T6

M&C I/OEthernet

E TH -B [ 8 . . 1 ]

L O 1 -B _ A N T6L O 1 _ S E L _ A N T6

T T LD r iv e r

S W 1 5

S P D T R F S w it c h

S TR -2 -H -I -L -TL -4 0R L C E le c t ro n ic sD C - 4 0 G H z

CI N 1

I N 212

G +V

L O 1 -A _ A N T7

L O 1 -B _ A N T7

T T LD r iv e r

S W 5

CI N 1

I N 212

G +V

L O 1 _ S E L _ A N T7

T T LD r iv e r

S W 1

CI N 1

I N 212

G +V

L O 1 -A _ A N T8

L O 1 -B _ A N T8L O 1 _ S E L _ A N T8

S P L 2

S P L I TTE R 1 6 -W A YP S 1 6 -2 7M C L I

1

2

3

S

4

5

6

7

8

9

1 0

1 1

1 2

1 3

1 4

1 5

1 6

T T LD r iv e r

S W 3

CI N 1

I N 212

G +V

S P L 1


1

2

3

S

4

5

6

7

8

9

1 0

1 1

1 2

1 3

1 4

1 5

1 6

T T LD r iv e r

S W 1 0

CI N 1

I N 212

G +V

T T LD r iv e r

S W 1 6

S P D T R F S w it c h

S TR -2 -H -I -L -TL -4 0R L C E le c t ro n ic sD C - 4 0 G H z

CI N 1

I N 212

G +V

A 2

3 0 d B g a in , 9 d B N F+2 9 d B m P o _ 1 d BQ u in s t a rQ P W -2 1 3 8 2 9 3 0 -0 0

L O 1 -A _ A N T9

T T LD r iv e r

S W 6

CI N 1

I N 212

G +V

L O 1 -B _ A N T9L O 1 _ S E L _ A N T9

L O 1 -A _ A N T1 0

L O 1 _ A N T1

L O 1 _ A N T3

L O 1 _ A N T2

L O 1 -B _ A N T1 0

L O 1 _ A N T6

L O 1 _ A N T5

L O 1 _ A N T4

L O 1 _ S E L _ A N T1 0

L O 1 _ A N T9

L O 1 _ A N T8

L O 1 _ A N T7

L O 1 _ A N T1 1

L O 1 _ A N T1 0

L O 1 _ A N T1 4

L O 1 _ A N T1 3

L O 1 _ A N T1 2

1 0 M H z_ I N 1

L O 1 _ TE S T

L O 1 _ A N T1 5

1 0 M H z_ I N 2

L O 1 -A _ A N T1 1

L O 1 -B _ A N T1 1L O 1 _ S E L _ A N T1 1

+1 2 V

+1 2 V

L O 1 -A _ A N T1 2

+1 2 V

+1 2 V

L O 1 -B _ A N T1 2

+1 2 V

L O 1 _ S E L _ A N T1 2

+1 2 V

+1 2 V

+1 2 V

+1 2 V

+1 2 V

+1 2 V

+1 2 V

+1 2 V

+1 2 V

+1 2 V

+1 2 V

[1]

L O 1 -B _ A N T1

L O 1 -B _ A N T2

L O 1 -B _ A N T3

L O 1 -B _ A N T4

L O 1 -B _ A N T5

L O 1 -B _ A N T6

L O 1 -B _ A N T7

L O 1 -B _ A N T8

L O 1 -B _ A N T9

L O 1 -B _ A N T1 0

L O 1 -B _ A N T1 1

L O 1 -B _ A N T1 2

L O 1 -B _ A N T1 3

L O 1 -B _ A N T1 4

L O 1 -B _ A N T1 5

L O 1 -B _ TE S T

L O 1 -A _ A N T1 3

L O 1 -B _ A N T1 3L O 1 _ S E L _ A N T1 3

L O 1 -A _ A N T1 4

L O 1 -B _ A N T1 4L O 1 _ S E L _ A N T1 4

L O 1 -A _ A N T1 5

L O 1 -B _ A N T1 5L O 1 _ S E L _ A N T1 5

L O 1 -A _ TE S T

L O 1 -B _ TE S TL O 1 _ S E L _ TE S T

LO1-B

RF Sy nthesizer

21.5 - 38 GHz Out0 to +10 dBm

H it t it e H M C -T2 2 4 0

R F O U T

R E F I N

I / O [ 1 . . 8 ]

\ S W _ S E L [ 1 . . 1 6 ]

[1]

L O 1 -A _ A N T2

L O 1 -B _ A N T2L O 1 _ S E L _ A N T2

[2]

L O 1 -A _ A N T3

L O 1 -B _ A N T3L O 1 _ S E L _ A N T3

L O 1 -A _ A N T4

L O 1 -B _ A N T4L O 1 _ S E L _ A N T4

[2]

LO Distribution Module Assembly Enclosure

10 MHz Ref In


LO Distribution Subsystem: LO2, DC input


-12V (RF)

\ S W _ S E L [ 1 . . 1 6 ]

+12V (FAN)

+10V "B"

+10V "A"

B P M O D 1

1 6 -C h a n B ip h a s e M o d u la t o r

I N 1

I N 2

I N 3

I N 4

I N 5

I N 6

I N 7

I N 8

I N 9

I N 1 0

I N 1 1

I N 1 2

I N 1 3

I N 1 4

I N 1 5

I N 1 6

O U T1

O U T2

O U T3

O U T4

O U T5

O U T6

O U T7

O U T8

O U T9

O U T1 0

O U T1 1

O U T1 2

O U T1 3

O U T1 4

O U T1 5

O U T1 6

S D [ 1 . . 1 6 ]

L O 2 _ L O C K

+12V (RF)

LO Distribution Module Assembly Enclosure

(For Future Implementation)

[2]

M O D [ 1 . . 1 6 ]

[3]

[5]

[4][1]

[6]

[7]

[8]S W _ S E L [ 1 . . 1 6 ]

120 VAC Input

[4]

A C [ 1 . . 2 ]

[1]

[9]


+ 10V @ 8.5A

P S 3

TD K -L a m b d a H W S 1 0 0 -1 2 / A

+V

-V

L

N

S +

S -

S W _ M O N [ 1 . . 1 6 ]


+ 12V @ 4.2A

P S 5

P h o e n ix C o n t a c t 2 8 6 6 3 2 3

+V

-V

L

N

From SPDTRF Switches

10 MHz Ref In

LO2 Outputs 21.150 GHz

M U L T1

x15 Freq. Multiplier

150 MHz Out

+13 dBm

S p e c t ra D y n a m ic sF S 1 5 0 -1 0

R F O U T

R E F I N

P A D 3

-6 d B

2 1 0 8 -6A TM

LO Distribution Module Power Supply Assembly Enclosure

L O 2

Ext. Ref . DRO

21.150 GHz Out

+13 to +16 dBm

L u c ixL O -2 1 1 -E C -1 0 2 0 6 1

R F O U T

R E F I N

L O C K

S P L 3


1

2

3

S

4

5

6

7

8

9

1 0

1 1

1 2

1 3

1 4

1 5

1 6

A 3

1 6 d B g a in , 5 d B N F+2 4 d B m P o _ 1 d BC ia o W ire le s sC A 2 0 2 1 -3 0 1 4

L O 2 _ A N T1

1 0 M H z_ I N 3

L O 2 _ A N T3

L O 2 _ A N T2

L O 2 _ A N T6

L O 2 _ A N T5

L O 2 _ A N T4

L O 2 _ A N T9

L O 2 _ A N T8

L O 2 _ A N T7

L O 2 _ A N T1 1

L O 2 _ A N T1 0

L O 2 _ A N T1 4

L O 2 _ A N T1 3

L O 2 _ A N T1 2

L O 2 _ A N T1 6

L O 2 _ A N T1 5

M&C I/O RS-485

U 1Embedded MPU

RMC4000Rabbit

D A TA [ 7 . . 0 ]

M O D B U S [ 1 . . 2 ]

A D D R [ 7 . . 0 ]

I O W R

I O R D

M B U S _ O U T[ 1 . . 4 ]

M B U S _ I N [ 1 . . 4 ]


+ 12V @ 3.4A

P S 1

I n t l. L in e a r H C 1 2 -3 . 4 -A +G

+S

+V

-V

-SG

L

N

LINE A R DC M ODULE

-12V @ 0.4A

P S 2

A c o p ia n 1 2 E B 4 0

+V

-V

L

N


+ 10V @ 8.5A

P S 4

TD K -L a m b d a H W S 1 0 0 -1 2 / A

+V

-V

L

N

S +

S -

L O _ P C B 1 L O M o d u le P C B

S TB [ 1 . . 2 ]

I / O [ 1 . . 1 6 ]M O D [ 1 . . 1 6 ]

L O C K

I N D [ 1 . . 1 6 ]

S E L [ 1 . . 1 6 ]M B [ 1 . . 2 ]

M B _ I [ 1 . . 2 ]

M B _ O [ 1 . . 2 ]

S E L [ 1 . . 1 6 ]

I O W R

I O R D


LO1-A, LO1-B Synthesizer



LO Distribution Module Interior Layout



LO Distribution Module Rear Panel



Quinstar Power Amplifiers for LO1



LO Distribution Module Interface PCB



LO Subsystem Design and Construction Current status

• All components in, except 2.92mm cables.• Distribution module mechanical design complete,

metal work on order. Assembly drawings delivered.• Need to generate detailed wiring diagram;

mechanical assembly will begin ~ Oct. 1.• LO interface module under assembly, firmware

development and GUI in progress.• Power supply module mechanical design and fab is

TBD; DC power cable is ready.



Timing Generation and Distribution Subsystem



Timing & Reference Distribution Block Diagram


A N T1G P S A n t e n n a

O P T_ TX1

1 P P S O p t ic a l Tra n s m it t e r

Tim e L in k D L # D TM TP F S CL in e a r P h o t o n ic s

1 P P S I NS M A

1 P P S O U TF C / A P C

D C I N1 A L A R M

4

G N D5

O P T P W R6

P W R D O W N7

A M P 1

D is t r ib u t io n A m p lif ie rP re c is io n Te s t S y s t e m sP TS 5 0

1 0 M H z I NB N C

O U T1B N C

O U T2B N C

O U T3B N C

O U T4B N C

O U T5B N C

TTL O U TB N C

S L A V EB N CA C I N [ 3 . . 1 ]

R X1

G P S R e c e iv e rA rb it e r S y s t e m s1 0 9 3 B + O p t . 3 4 (N TP )

A C I N [ 3 . . 1 ]

R S -2 3 2 [ 2 . . 1 ]

N TP O U T[ 8 . . 1 ]

R F I NF

1 P P S O U T1

G N D2

O S C 1

R b F re q u e n c y S t a n d a rdS t a n f o rd R e s e a rc h S y s t e m sP R S 1 0 + P R B B

R S -2 3 2 [ 2 . . 1 ]

1 P P S I NB N C

1 P P S O U TB N C

1 0 M H z O U TB N C

+2 4 V I N+2 4 V R E T

1PPS Optical Out, 1550nm

+2 4 V+2 4 V _ R E T

(10 ms p.w.)

TI M _ P C B

5 0 H z G e n e ra t o r

1 P P S I N

1 0 M C L K

1 P P S O U T[ 1 4 . . 1 ]

5 0 H z O U T[ 4 . . 1 ]

(20 us p.w.)

5 0 H z_ O U T[ 4 . . 1 ]

P S 2

A c c o p ia n5 E B 1 0 0

D C P o we r S u p p ly

+5 V

C O M

L

N

1 0 M H Z _ C L K

(4 x TTL 50 ohm)

(+24VDC @ 3A)

E D F A 1

O p t ic a l A m p lif ie r + 1 6 -wa y s p lit t e rA L M A (M a n lig h t )H V V T-N X0 -E D F A -P R D

A C I N [ 3 . . 1 ]C 1 3

R S -2 3 2 [ 2 . . 1 ]D B -9

I NE 2 0 0 0

O U T[ 1 6 . . 1 ]E 2 0 0 0

(+7 dBm)

(+5VDC @ 1A)

(0 dBm)

1 P P S _ O U T1 3

1 P P S _ O U T[ 1 4 . . 1 ] 1PPS Outputs(LO1-A, LO1-B, DPP, ACC, 8 x Correlator, + 1 Spare)

+5 V _ R E T

+5 V

E2000

LO1-A 10 MHz

LO1-B 10 MHz

+5 V _ R E T+5 V

(13 x TTL 50 ohm)

LO2 10 MHz

Corr. Clk. Gen.10 MHz Ref.

(Spare 10 MHz)

1PPSInput

[1]

[2] [2]

[2]

[2]

1PPS Opt. Outputs(16 x SMF)

(Ant. 1-15 + 1 spare)

[2]

[2]

[3]

[3]

Timing Generation and Distribution Module

Monitor and Control(3 x RS-232, Ethernet)

[4]

50 Hz Outputs

+2 4 V _ R E T+2 4 V

[5]

120VAC Input

A L A R M _ M O N

(LO1-A, LO1-B, DPP + 1 Spare)

O P T_ M O N

P S 1

TD K / L a m b d aH W S 1 0 0 -2 4 / A


+2 4 V

C O M

LNG

(TTL)

(0.5 V/mW)

(+5 dBm)

LO and Timing Distribution Rack

SMB

SMB

(0 dBm)

(+13 dBm)

(+2 dBm ea. output)

+2 4 V _ R E T

+2 4 V

SMB

(+10 dBm)

(+10 dBm)

SMB

M 1

E 2 0 0 0 A d a p t e r

[6]

-1 0 d B

FC/APC

-1 0 d B[7]


Timing Generator Module Interior Layout



Timing Generator Module Rear Panel



1 PPS Driver, 50 Hz Generator PCB



1PPS Laser Transmitter Unit



EDFA / 16-way splitter (“PRD-16”)



PRD-16 Rear Panel



1PPS Optical Receiver



Labview GUI for PRD-16



Timing Generation and Distribution Subsystem Design and Construction - Current status

• All components are in.• TGD module mechanical design complete, metal work

on order (fast turnaround)• Assembly drawing delivered.• Need to generate module wiring diagram; mechanical

assembly will begin ~ Oct. 1.• Timing generator boards built, tested.• Will need a small additional PCB for output buffering

of the optical RX, to correct polarity, pulse width and drive level for cRIO.



Correlator Clock Generation (CCG) Module



CCG Module Block Diagram


(+15VDC @ 0.4A)

Correlator Clock Generation Module, 2U 19" Rack Mount Enclosure

P S 1

A c c o p ia n1 5 E B 4 0


+1 5 V

C O M

LNG +1 5 V _ R E T

+1 5 V

10 MHz Ref. In

R E F I N

P L O 1

Ext. Ref . PLO

1200 MHz Out

(+13 dBm)

S p e c t ru m M ic ro wa v e6 2 1 5 1 3 -0 1 5

R F O U T

R E F I N

L O C KL O C K

PLO LockStatus Out

(-13 dB)

(+15 dBm)

P A D 1

-1 0 d B

S A 3 0 1 5 -1 0F a irv ie w

[4]

(+2 dBm)

[3]

(TTL)

1 = Locked

[5]P A D 2

TB D d B

S A 3 0 1 5 -XXF a irv ie w

S P L 1

S P L I TTE R 1 6 -W A Y

Z C 1 6 P D -2 4 +M in i-C irc u it s

1

2

3

S

4

5

6

7

8

9

1 0

1 1

1 2

1 3

1 4

1 5

1 6

A 1

2 0 d B m in . g a in+1 6 d B m P o _ 1 d BM in i-C irc u it sZ F L -2 0 0 0 +

C O R R _ C L K 3

C O R R _ C L K 2

C O R R _ C L K 1

C O R R _ C L K 6

C O R R _ C L K 5

C O R R _ C L K 4

C O R R _ C L K 8

C O R R _ C L K 7

C O R R _ C L K 1 1

C O R R _ C L K 1 0

C O R R _ C L K 9

C O R R _ C L K 1 4

C O R R _ C L K 1 3

C O R R _ C L K 1 2

C O R R _ C L K 1 6

C O R R _ C L K 1 5

[2]

[1]

CorrelatorClock Outputs 1200 MHz

120VAC Input


CCG Module Interior layout



CCG Module Rear Panel



CCG Module Design and ConstructionCurrent status

• All components in, except 1200 MHz PLO; expect it to ship 9/28/12 from vendor.

• CCG module mechanical design complete, metal work on order (fast turnaround)

• Assembly drawing delivered.• Need to generate CCG module wiring diagram;

mechanical assembly will begin ~ Oct. 1.



Rack-Level Design and Cabling



Layout of Equipment Racks, Front View



Partial Drawing of Analog Racks, Rear View



LO Inter-rack Cable Routing



Downconverter Subrack Frame



Analog Rack Layout and ConstructionCurrent status

• Equipment racks on order; delivery expected at end of October.• 6U subrack kits received; awaiting guide rail hardware• PDUs and UPS ordered and received by Kjell N.• Fiber cables to Patch Panel on order, quick delivery.• LO2 cables on hand; LO1 cables expected late Oct.• DC supplies and filters for Downconverter rack on hand, in

sufficient quantity for prototype build.• Mechanical layout and wiring of Downconverter power supply

panel is TBD. Will use DIN rails and terminal blocks like Auxiliary cabinet, but with separate 19” wide panel for power cable mating.

• Downconverter IF output cables to Correlator rack not yet specified or ordered. Short lead-time item.



Schedule, Costing and Personnel



Revised Module Delivery Timeline

• Module construction ~1-3 months behind original schedule. Will have staged deliveries:– Expect to assemble, test and ship TGD and CCG modules mid-

October, with PRD-16.– Begin assembly of LO Distribution module mid-October, test and

ship by mid-November, assuming GUI and firmware are ready.– Assemble Downconverters by early November, test and ship by

end of November, assuming software GUI available and firmware is done.

– Fab of mechanical pieces in Front End assembly by mid-November, assembly complete in early Dec. Test and ship all units by end of year.



Schedule Risks and Assumptions

• Remaining deliveries from vendors are on time. Moderate risk.

• Assume full-time technician help available through end of November. Moderately high risk.

• Assume firmware and GUI available when needed for module testing. Moderately high risk.

• No 11th-hour design changes. – Low risk for TGD, LO Dist. and CCG modules– Moderate risk for Downconverter, Front End modules

• Other unforeseen catastrophes (??). Low risk.



Costing and Personnel

• Prototype and production costing tracked with top-level Excel bill of materials (view)

• Additional personnel in VA working on EOVSA:– Chuck Neff, Mechanical draftsman/designer, Segars

Engineering. 3D mechanical design of modules.– Steve Nuttall, Senior Technician, NRAO. Board and

cable assembly, wiring, mechanical assembly.– Bob Treacy, Tech Spec. I, NRAO. PCB layout.– Jason Castro, Engineer II, NRAO. Embedded firmware

and Labview GUIs.



Documents

Analog System Review and Status Wes Grammer NRAO September 24-26, 2012EOVSA Prototype Review1