14th Workshop on Synthesis And System Integration of Mixed Information technologies SASIMI 2007, Sapporo October 15-16, 2007 This work has been funded by BMBF and edacentrum e.V. within project (No. 01M3072C)

Analog Simulation Meets Digital Verification -A Formal Assertion Approach for Mixed-Signal Verification

Analog Simulation Meets Digital Verification Analog Simulation Meets Digital Verification --A Formal Assertion Approach for MixedA Formal Assertion Approach for Mixed--Signal VerificationSignal Verification

Stefan Lämmermann, Roland Weiss, Jürgen Ruf,Thomas Kropf, Wolfgang RosenstielDepartment of Computer Engineering

University of Tübingen, D-72076 Tübingen, Germany{laemmerm,weissr,ruf,kropf,rosenstiel}@informatik.uni-tuebingen.de

Alexander Jesser, Lars Hedrich

Department of Computer ScienceUniversity of Frankfurt, D-60325 Frankfurt a. M., Germany

{jesser,hedrich}@em.cs.uni-frankfurt.de

Alexander Pacholik, Wolfgang Fengler

Computer Architecture GroupIlmenau Technical University, D-98693 Ilmenau, Germany

{alexander.pacholik,wolfgang.fengler}@tu-ilmenau.de

Abstract— Functional and formal verification are important methodologies for complex mixed-signal designs. But there exists a verification gap between the analog and digital blocks of a mixed-signal system. Our approach improves the verification process by creating mixed-signal assertions which are described by a combination of digital assertions and analog properties. The proposed method is a new assertion-based verification flow for designing mixed-signal circuits. The effectiveness of the approach is demonstrated on a Σ/Δ-converter.

Digital AssertionsDigital AssertionsDigital AssertionsSpecification

Model Property

Implementation Assertions

Design under Verification (DUV)

Formal Simulation Emulation

Monitors

Functional simulation with formal propertiesAssertions for simulation and formal verification

ResultsResultsResults

MSA is based on the industry standard PSL MSA can be used for functional and formal verificationBetter monitoring/controlling of analog/digital interactionsCheck formal properties during simulation

Analog PropertiesAnalog PropertiesAnalog Properties

Continuous signal monitoringContinuous time considerationFrequency analysis

0

0 ( ( ), ( ), ( ), )( ) ( ( ), ( ), )(0)

f x t x t u t ty t g x t u t tx x

===

ProblemProblemProblem

Mixed-Signal System

PSLAssertions

AnalogProperties

DigitalSystem

AnalogSystem

Discrete timeSignal triggeredBoolean values

Continuous timeTime intervalsContinuous valuesRanges with inequalities

Formal property description languages for mixed-signal systems are still not sophisticated

1 (fs)

Property Accept/Reject in tclk

2 (fs)

3 (fs)

4 (fos)

5 (fos)

6 (fos)

7 (fos)

21 43

A,1

MSA5

A,4

A,14

A,26

A,107

A,81

R,0

A,2

A,8

A,18

A,31

A,267

A,161

R,2

A,10

A,24

A,34

A,69

A,306

A,241

R,4

A,11

A,28

A,38

A,186

A,427

A,321

R,6

A,12

A,44

A,54

A,191

A,466

A,401

R,7

Case studyCase studyCase study

Characteristics (general)

Including monitor points (digital/analog block)Specification language: PSL (property specification language) Using implication → operator for combining analog and digital conditionsInterconnection verification

Characteristics (analog)

PSL extension for mixed-signal systemsDiscretize continuous time into, e.g., equidistant time pointsQuantify signal values into a Boolean representationMap time intervals to discrete time points

Solution: combination of conditionsSolution: combination of conditionsSolution: combination of conditionsGeneral definition of Mixed-Signal Assertions (MSA)General definition of MixedGeneral definition of Mixed--Signal Assertions (MSA)Signal Assertions (MSA)

PostconditionPrecondition

{ } | { }{ } | { }Analog DigitalDigital Analog

→→

ˆ ˆ4 :{ ( ) 0.891}| { _ [10]( _ [4]( ( ))& _ [4 :5](! ( ))}ˆ ˆ5 :{ ( ) 0.891}| { _ [10]( _ [4](! ( ))& _ [4 :5]( ( ))}

ˆ ˆ6 :{ ( ) 0}| { _ [1: 2]( ( ))& _ [1: 2](! ( ))}

n n

n n

n n

x t next e next a s t next e s tx t next e next a s t next e s tx t next e s t next e s t

= →= − →

= →

ˆ7 :{ ( )} | { ( ) 1.4}ns t g t→ =

Counterexample

∫

20sf Hz=160osf Hz=( )x t ˆ( )nx tˆ( )ns t

k( )g t

1.4k =

Σ/Δ-Converter

Simulation / Formal VerificationSimulation / Formal VerificationSimulation / Formal Verification

Analog Condition

Analog Condition

D/A

Mixed-Signal Assertions:

8

Digital Condition

Digital Condition

Structure of MSAStructure of MSAStructure of MSA

Simulation

Mixed-Signal System

MSA MessagesWaveforms

Verification

Mixed-Signal Assertion

Analog Digital

Analog signal range Digital signalTemporal operator with interval

Analog Precondition Digital Postcondition

0 1 2( ) 0.7& ( ) 0. ˆ ˆ ˆ( & &!{ } | { }7 _ ] )[1: 4ne x xx t x xt ex t< > − →

0 1 2 3 4 5 6 7

0 1 2 3 4 5 6 7

ˆ ˆ ˆ ˆ ˆ ˆ ˆ ˆ1:{ ( ) 0.7& ( ) 0.7}| { _ [1: 2]!(( ( )& ( )& ( )& ( )& ( )& ( )& ( )& ( )) ||ˆ ˆ ˆ ˆ ˆ ˆ ˆ ˆ(! ( )&! ( )&! ( )&! ( )&! ( )&! ( )&! ( )& ( )))}

n n n n n n n n

n n n n n n n n

x t x t next e x t x t x t x t x t x t x t x tx t x t x t x t x t x t x t x t

< > − →

0 1 2 3 4 5 6 7ˆ ˆ ˆ ˆ ˆ ˆ ˆ ˆ ˆ2 :{ _ [0.0 : 0.05]( ( ) 0.8)}| { _ [2]( ( ) ( )& ( )& ( )& ( )& ( )& ( )& ( )&! ( ))}n n n n n n n n nnext a x t next e x t x t x t x t x t x t x t x t x t≥ → =

0 1 2 3 4 5 6 7ˆ ˆ ˆ ˆ ˆ ˆ ˆ ˆ ˆ3 :{ _ [0.0 : 0.05]( ( ) 0.8)}| { _ [2]( ( ) ! ( )&! ( )&! ( )&! ( )&! ( )&! ( )&! ( )& ( ))}n n n n n n n n nnext a x t next e x t x t x t x t x t x t x t x t x t≤ → =