An Rtos-based Architecture for Industrial Wireless Sensor Network Stacks With Multi-processor Support(1)

7/21/2019 An Rtos-based Architecture for Industrial Wireless Sensor Network Stacks With Multi-processor Support(1)

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ABSTRACT


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ABSTRACT

This paper is an RTOS based architecture designed for the purpose of data

transmission between two controlling units through IWSN without collision. RTOS is a

Process which will be done between hardware and application. Here, stac is the one which is

used to a!oid the independenc" of the la"ers from one with another inside the protocol comes

under the standard I###$%&.'(.).Stac ha!ing two techni*ues +P- and NI-I we are using

in the I### $%&.'(.) to reduce the collision and timing. /ostl", during the pacets

transmission some collision ma" occur. This collision has to be a!oided to pre!ent the data

loss during the transmission.

The pro0ect deals with the data transmission between two units in the e1act time

without an" collision. The data transmission time is increased with the protocol standard. One

of the section runs with RTOS and -P2&')$ as master node and another as normal data

ac*uisition node to which sensors are connected. 3ata ac*uisition node uses the Peripheral

Interface controller. 2ommunications between two nodes +hardware and application are

accomplished through I### $%&.'(.).

The RTOS is to manage the allocation of these resources to users in an orderl" and controlled

manner. This wireless sensor node is composed of a micro4processors, transcei!ers, displa"s

and analog to digital con!erters. Sensor nodes are deplo"ed for industrial process monitoring

and control. The sensing parameters can be displa"ed as graph in /aster node. The basic

!iew of this techni*ue is to reduce the possibilit" of collision and to meet the critical

re*uirement of timing for data transmission of industrial applications


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TABLE OF CONTENTS

TABLE OF CONTENTS

CHAPTER NO. TITLE PAGE NO.


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ABSTRACT vii

LIST OF FIGURES xiii

LIST OF ABBREVATION xiv

1. INTRODUCTION 02

2. POWER SUPPLY UNIT 07

&.' 2ircuit 3iagram 07

&.'.' Woring Principle 07

&.'.& Transformer 08

&.'.5 6ridge Rectifier 08

&.'.) I2 7oltage Regulators 10

3. ICROCONTROLLER 12

R/

!. SERIAL COUNICATION 38

).' Introduction 38

).& Null /O3#/ !1

).5 RS&5& !2


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).) Null /O3#/ without Handshaing !3

).( 2ompatibilit" issues !!

". SOFTWARE TOOLS "#

(.' T"pes of Tools "#

(.'.' 8#I- 2 "#

(.'.& 9lash /agic "7

(.'.5 OR23 "8

(.'.) 3esign flow of OR23 "$

ATLAB

VB

#. HARDWARE TOOLS #1

:.' ;igbee

:.& brainwa!e sensor

8. CONCLUSION 7"

$. 10. REFERENCES


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CHAPTER%1

INTRODUCTION

The RTOS is to manage the allocation of these resources to users in an orderl" and

controlled manner. This wireless sensor node is composed of a micro4processors, transcei!ers,

displa"s and analog to digital con!erters. Sensor nodes are deplo"ed for industrial process

monitoring and control. The sensing parameters can be displa"ed as graph in /aster node. The

basic !iew of this techni*ue is to reduce the possibilit" of collision and to meet the critical

re*uirement of timing for data transmission of industrial applications.


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1.1 BLOC& DIAGRA'

B()*+ ,i-/-'

-/ 4),'

B()*+ Di-/-'

-/ N),'

H-/,5-/ 6 S)5-/ R9i/4'

H-/,5-/'

/icrocontrollers

Sensors


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1.3 E


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No la"er architecture

No data ac*uisition node

1.! PROPOSED SYSTE' No collision

Time Integrit"

9ine transmission and clear displa" units

3ata ac*uisition s"stem

CHAPTER%3


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CHAPTER%3

CHAPTER%3

CHAPTER

3

AR PROCESSOR


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I4/),9*i)4'

The -P2&')'=&=)=:=$ microcontrollers are based on a 5&=': bit R/>T3/I4S

2P? with real4time emulation and embedded trace support, that combines the

microcontroller with embedded high speed flash memor" ranging from 5& 6 to

('& 6. '&$4bit wide memor" interface and a uni*ue accelerator architecture

enable 5&4bit code e1ecution at the ma1imum cloc rate. 9or critical code si@e

applications, the alternati!e ':4bit Thumb mode reduces code b" more than 5% A

with minimal performance penalt".

F-9/ ) LPC21!8'

':=5&4bit R/>T3/I4S microcontroller in a tin" -B9P:) pacage.

:% /H@ ma1imum 2P? cloc a!ailable from programmable on4chip P--

with settling time of '%% Cs.

T"pical fre*uenc" '&/H;.

2P? operating !oltage range of 5.% 7 to 5.: 7 +5.5 7 D '% A with ( 7

tolerant I=O pads.

The -P2&'):=$ pro!ide $ 6 of on4chip R/ accessible to ?S6 b" 3/.

32 5.57 and other functionalit"Es lie SR/ ha!ing )86, 9lash memor"

ha!ing ('&86.

On4chip integrated oscillator operates with an e1ternal cr"stal in range from

' /H@ to 5% /H@ and with an e1ternal oscillator up to (% /H@.

Power sa!ing modes include Idle and Power4down.

P/i:=/-( -9/'


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)$gb input output pins with all internal pullup resistance.

Onchip &32 blocs.each bloc contains >.o!er all ') N

blocs are interfaced.

This 32 is based on successi!e appro1imation with a

con!ersion rate of &.))micro sec.32 fre*uenc" must be

F).(/h@.

/a1imum resolution is '%bit.This resolution is programmed till

5 bits.

On chip &?RTS with $ bits for transmit.

&timers=counters each of 5&bit long with separate matchregisters and capture registers for timer and counters.

)32s with tolerance 5!olts.

Onchip SPI+Serial peripheral register and SSP+s"nchronous

serial port for s"nchronous communication.

5& !ectored interrupts.#ach interrupts can be configured into ':

priorit" le!els with le!el and its sensiti!it".

On chip RT2 for memor" storage.

AR7TDI%S :/)*)/'

R/> is an load store architecture .The R/>T3/I4S is a general purpose 5&4bit

microprocessor, which offers high performance and !er" low power consumption.

The R/ architecture is based on Reduced Instruction Set 2omputer +RIS2


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principles, and the instruction set and related decode mechanism are much simpler

than those of micro programmed 2omple1 Instruction Set 2omputers.

Pipeline techni*ues are emplo"ed especiall" 5 stage pipeling so that all parts

of the processing and memor" s"stems can operate continuousl". In 5 stage

pipeline the process includes fetch,decode,e1ecute in same cloc c"cle for 5 tass.

T"picall", while one instruction is being e1ecuted, its successor is being decoded,

and a third instruction is being fetched from memor".

The R/>T3/I4S processor also emplo"s a uni*ue architectural strateg"

nown as TH?/6, which maes it ideall" suited to high4!olume applications with

memor" restrictions, or applications where code densit" is an issue. The e" idea

behind TH?/6 is that of a super4reduced instruction set. #ssentiall", the

R/>T3/I4S processor has two instruction setsG

> The standard 5&4bit R/ instruction set.

> ':4bit TH?/6 instruction set.

In load store there are > modes of woring .i.e ?ser mode, IRB mode, 9IB

mode ,Super!isor" mode,bort mode,?ndefined mode,S"stem mode.

LPC21!8 i*/)*)4/)((/ '


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9igure G bloc diagram of -P2&')$.

In -P2&')$ ha!ing :) pins di!ided into & ports i.e port% and port'.each port

ha!ing 5& pins .In port ' here we are using p'.%4p'.'( as debugging purpose.e!er"


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pin in multiple1ed internall" with four different functionalities . user ha!e to

program the section bits. In order to select one functionalities for ' port pin there

must be & selection bits. The functionalit" of selection bits will be pair from one

pair to other.

PIN F94*i)4-(i; S(*'

In order to program the re*uired function for the respecti!e pin we ha!e a register

called PINS#-. In pin select there are PINS#-%, PINS#-',PINS#-&.

P=- ()*+, ()): ?PLL@'

There are two P-- modules in the -P2&')'=&=)=:=$ microcontroller. The P--% is

used to generate the 22-8 cloc +s"stem cloc while the P--' has to suppl" the

cloc for the ?S6 at the fi1ed rate of )$ /H@. The input fre*uenc" is multiplied

up the range of '% /H@ to :% /H@ for the 22-8 and )$ /H@ for the ?S6 cloc

using a 2urrent 2ontrolled Oscillators +22O.


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9igure GP-- bloc diagram

The 22O operates in the range of '(: /H@ to 5&% /H@, so there is an

additional di!ider in the loop to eep the 22O within its fre*uenc" range while the

P-- is pro!iding the desired output fre*uenc". The output di!ider ma" be set to

di!ide b" &, ), $, or ': to produce the output cloc. Since the minimum output

di!ider !alue is &, it is insured that the P-- output has a (%A dut" c"cle.

Ri/ ) PLL'

PLLCON'%This register are used to control the P-- i.e to enable or connect .

> : ( ) 5 & ' %

2 #


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PLL0CEF'

It is a $ bit register used to configure the desired fre*uenc". this is done

b" selecting multiplier and di!ider.

> : ( ) 5 & ' %

% % % % %

% % % % '

% % % ' %

% % % ' '

9or e1ampleG % % ' % %

PLL0STAT'

It is a ': bit register.This register pro!ides the actual !alues controlling

the P--, as well as the status of the P-- i.e ploc.

PLL0FEED'

It is a $ bit register. P-- 9eed Register. This register enables loading of

the P-- control and configuration information from the P--2ON and

P--29< registers into the shadow registers that actuall" affect P--

operation. In order to update the !alues we ha!e to toggle all the $ bits

of P--. which are internal latches.


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G4/-( :9/:) i4:9)9:9 ?GPIO@'


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IOCLR'%


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U4iv/-( -;4*=/)4)9 /*iv/ -4, /-4i/ ?UART@

?RT ha!ing two port pins i.e. ?RT% and ?RT'.

S;4*=/)4)9'%

To transmit the data from source to destination with respect

to cloc.

Ex'% SPI, #thernet, 2N.

S/i-( P/i:=/-( I4/-* ?SPI@'%

SPI is a full duple1 serial interfaces. It can handle multiple masters and

sla!es being connected to a gi!en bus. Onl" a single master and a single

sla!e can communicate on the interface during a gi!en data transfer.

3uring a data transfer the master alwa"s sends $ to ': bits of data to the

sla!e, and the sla!e alwa"s sends a b"te of data to the master.

A;4*=/)4)9'%

To transmit the data from source to destination with

respect to baud rate i.e. bits =sec.

Ex'%


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U4iv/-( -;4*=/)4)9 /*iv/ -4, /-4i/ ?UART0@'%

F-9/ ) UART0'

': b"te Recei!e and Transmit 9I9Os

Register locations conform to ((% industr" standard

Recei!ers 9I9O trigger points at ', ), $, and ') b"tes.

6uilt4in fractional baud rate generator with autobauding capabilities.

/echanism that enables software and hardware flow control

implementation.

U4iv/-( -;4*=/)4)9 /*iv/ -4, /-4i/ ?UART1@'%

F-9/ ) UART1'%

> ?RT' is identical to ?RT%, with the addition of a modem interface.

> ': b"te Recei!e and Transmit 9I9Os.

> Register locations conform to ((% industr" standard.

> Recei!er 9I9O trigger points at ', ), $, and ') b"tes.

> 6uilt4in fractional baud rate generator with autobauding capabilities.

> /echanism that enables software and hardware flow control

implementation.

> Standard modem interface signals included with flow control +auto4

2TS=RTS full"supported in hardware +-P2&'))=:=$ onl".


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Ri/ ) UART'%

U0THR'%

ItEs a $ bit register with holds the transmitting !alue. The

?%THR is the top b"te of the ?RT% TJ 9I9O. The top b"te is the

newest character in the TJ 9I9O and can be written !ia the bus

interface. The -S6 represents the first bit to transmit.

UORBR'%

ItEs a $ bit register with holds the recei!inging data !alue.

?%29 : ( ) 5 & ' %3-6 6I Section of parit" Parit" 3ata length

% % % % 3 % ' '' ' % ' # ' ' %

' % % '

' ' % %

?%THR, ?%R6R are enable when 3-6 bit are %E. ?%THR, ?%R6Rare enable when 3-6 bit are 'E.

B-9, /- *-(*9(-i)4'%In order to store the baud rate we ha!e two registers ?%3-/ ?%3--

which are enable onl" when 3-6 bit in ?%9< is 'E.3-6 is %E these

register are disable. We can sa" it as ?RT baud rate is large.

Here mae 3-6 bit as 'Eand than configure ?RT baud rate

after configure ?RT we ha!e loc ?RT after with respecti!e baud

rate. Than we ha!e to r1 K t1 with we do as 3-6 bit as %E.


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?%3--L +P2-8=+':Mbaud rateA&(:.

?%3-/L +P2-8=+':Mbaud rate=&(:.

U0STAT'%

Which is used to red the acnowledgement bits of particular

?RT.

> : ( ) 5 & ' %

R1 fifo T#/T THR# 6I 9# P# O# R3R

The total data will RJ in R1 side than R3R bit will be ' or other

wise %.

If an" o!erlapping error occur in send data than O# bit will be '

other wise %.

In Parit" checing error it will be ' mean error in the frame

otherwise %.

In frame error it will be ' mean error are occurred in the frame

otherwise %. If an" brea occurred in sending data from source to destination

than 6I bit will be ' other wise %.

3ata will be transmits b" using 9I9O if an" o!er lapping are

occurred than R1 9I9O bit will be ' other wise %.

CHAPTER%!


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Gi4 S-/, 5i= AR T;/) &i

The R/>T3/I T"ro


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Select Power for >Seg,


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Con;g&re the Device an" CO/ Port settings

ea" the Device D signat&re

elect #rase !locks an" !rowse yo&r o&tp&t ):#$* ;le.

witch yo&r A/ %yro +it in P9/ /o"e

tart 0ashing the A/ /icrocontroller

##% the %yro +it an" switch over to the #$# 'o"e by Popping &p the p&sh

b&tton. ,ollow the &ser 'an&al for other con;g&rations correspon"ing to yo&r

experi'ent.

ori#+ wi$ Keil 3isio# ARM

teps involve" in Creating an" #xec&ting a Pro(ect?#@ to a"" the "efa&lt tart Up co"e to yo&r pro(ect.

Click ile 7 New an" create a new text ;le an" save it as .C

Develop ?o&r Co"e an" A"" the co"e to the %arget

ight Click on (our%e Group 7 Click A** iles o (our%e Group19


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!&il" an" e-!&il" yo&r Pro(ect for #rrors by right clicking '"r+e 7 ,uil* '"r+e

Do&ble Click on #rrors to locate an" De-b&g

%hese processes are s&Bcient for si'&lation. ,&rther steps help yo& to generate

o&tp&t ;les.

ight click on '"r+e 7 Click Opio#s :or '"r+e '"r+e 19

On the Oupu %ab -- #nable the Checkbox Cre"e ;E< ile9


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e-!&il" yo&r %arget again to generate :#$ ,iles

?o& can si'&late yo&r pro(ect &sing +eil 83ision2 D# by clicking the De=u+

,or tep #xec&tion Press .


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(eps i#!ol!e* i# Pro+r"))i#+ ARM Co#roller usi#+ l"s$ M"+i%

(o:w"re

Click the Desktop hortc&t after nstalling the software

Con;g&re the ,lash/agic software so as not to ##% the har"ware by clicking

Opio#s 7 A*!"#%e* Opio#s

Navigate to the ;"r*w"re Co#>+ %ab an" Disable the checkbox &se D'R "#*

R'( o %o#rol R(' "#* P0.14

Con;g&re DeviceE CO/ Port an" nterface as above.

DO NO% enable the #rase all ,lashFCo"e " Prot checkbox

Click ("r b&ttonG yo&r :#$ co"e wo&l" be s&ccessively 0ashe" into the O/. Never press ##% or Power O,, the +it when the +it is being progra''e".

f there is a proble' in Progra''ing or No response fro' the +it ##% the +it

an" on ,lash/agicH navigate to I(P I click Re"* De!i%e (i+#"ure? an"check for co''&nication with the +it

RTOS INTERFACE FOR DISPLAY'


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?2OS4II is a module that allows "ou to interface with character module. This software

pacage wors with 0ust about an" character module based on the GDM12864B


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G/-:=i*-( Li9i, C/;-( Di:(-; i4/-*i4 :i4'


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PROGRAING PRINCIPLES 6 IPLEENTATION ETHOD'

1. IO B9/

The Input buffer controls the status between the enable and disable of chip. ?nless the

2S'6 to 2S5 is in acti!e mode input or output of data and instruction does not e1ecutes.

Hence internal state is not changes. RST6 and 32 can operate regardless 2S642S5.

2. I4:9 /i/

The Input register is pro!ided to interface with /P? which is different operating

fre*uencies, Input register stores the data temporaril" before writing it into displa" R/

memor".Whene!er 2S'6 to 2S5 are in the acti!e mode R=W and RS select the input

registers. 3ata from /P? is written into input registers then writing it into displa" R/

memor". The 3ata latched for falling of the # signal and write automaticall" into thedispla" data R/ b" internal operations.

3. O9:9 /i/

The Output register stores the data temporaril" from displa" data R/ when 2S'6

2S&6 and 2S5 are in acti!e mode and R=W and RSLH stored data in displa" data R/

is latched in output registers. When 2S'6 to 2S5 is in acti!e mode and R=WLH RSL-

status data +bus" chec can read out from memor". In order to read the contents of

displa" data R/, twice access of read instruction is needed. The first access data in

displa" data R/ is latched into output register and in second access /P? can read data

which is latched out, which is to read the data in displa" data R/ it needs dumm" read.

!. R

S"stem can be initiali@ed b" setting RST6 terminal at low le!el when turning power on

recei!ing

instruction from /P? unit, When RST6 becomes low following procedure occurs.

'. The 3ispla" off.


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&. 3ispla" start line register become set b" % +;4address %.

When RST6 is low no other instruction e1cept status read can b" accepted

therefore,e1ecute other instructions after maing sure that 36)L +clear RST6 and

36>L% +read" b" status read instructions.

".< P- Ri/

The J page register designates pages of the internal displa" data R/ memor". 2ount

function is not a!ailable here. n" address can be set b" instruction of programmer.

#. Y -,,/ *)94/

Similar to J, Q address counter designates address of the internal displa" data R/

memor". This address is set b" instruction and is increased b" ' automaticall" b" read or

write operations of displa" data of gi!en arra".

7. Di:(-; D-- RA

33R/ stores a displa" data for li*uid cr"stal displa", to indicate on state dot matri1 of

li*uid cr"stal displa" and write datra'. Other wa" off state writes %.

33R/ address and segment output can be controlled b" 32 signals.

32LH L Q4address %G S'Q address :5G S:)

32L- L Q4address %G S:)Qaddress :5G S'

32 terminal connect the 733 or 7SS.

8. Di:(-; S-/ Li4 Ri/

3ispla" start line register indicates of displa" data R/ to displa" top line of -23. The

6it data +36F%.( of the displa" start line set instruction is latched in displa" start line.

Here -atched data is transferred to the ; address counter while 9R/ is high, presetting

the ; address which is used for scrolling of the li*uid cr"stal displa".

Di:(-; C)4/)( I4/9*i)4'

3ispla" control instructions control the internal state of the 8S%'%$6. Instruction is

recei!ed from /P?to 8S%'%$6 for the displa" controlling. 9ollowing table shows !arious

instructions.


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I4/-* F94*i)4'

The C2=-23 assumes the presence of a real4time ernel such as C2=OS4II

because it re*uires a semaphore and time dela" ser!ice. 3ispla" module maes use of a

binar" semaphore to pre!ent multiple tass from accessing the displa" at the same time

e!ent. 6" the use of the semaphore is encapsulated in an OS specific file so "ou can

actuall" use C2=-23 with the RTOS of "our re*uirement.


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6elow shows a bloc diagram of the -23 module. Qour application nows about the

displa" onl" through the interface functions pro!ided.

C2=-23 interface functions

1@Di:C=-/?@' This function allows "ou to displa" a single character an"where on the displa".

9unction Protot"peG !oid 3isp2har+INT$? row, INT$? col, INT$? c

row and col specifies the coordinates +row, col where the character will appear. rows +i.e., lines

are numbered from % to 3isp/a1Rows U ', and columns are numbered from % to 3isp/a12ols

U '.

2@Di:C(/Li4?@'this function allows "our application to clear one of the -23 moduleVs lines. The line

is basicall" filled with the S2II character i.e. %1&%. Here rguments

line is the line +i.e., row to clear. Note that lines are numbered from % to 3isp/a1Rows.

3@Di:C(/S*/?@' this function allows "ou to clear the screen. The cursor is positioned on the top

leftmost character.


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!@Di:DC=-/?@' This function allows "ou to define up to eight custom (1$ pi1el characters or

s"mbols, fonts which is one of the most powerful features of the -23 modules because it allows "ou

to create graphics such as icons, bar graphs, arrows, etc,.

v)i, Di:DC=-/?INT8U i, INT8U :-@

Qou need to do to define a new character or s"mbol is to declare an initiali@ed arra" of INT$?s

containing eight entries and call 3isp3ef2har+

"@Di:H)/B-/?@ ' This function is used to displa" hori@ontal bars an"where on the screen.

v)i, Di:H)/B-/?INT8U /)5 INT8U *)( INT8U v-(@

We can use C2=-23to create remarabl" high *ualit" bargraphs. The linear bargraph is an e1cellent

trend indicator and can greatl" enhance operator also depending on the si@e of the module, man"

bargraphs can be simultaneousl" displa"ed on -23. C2=-23 allows "ou to displa" bar graphs of an"

si@e an"where on the screen.

#@Di:I4i?@' This function is used to initiali@es the hardware, creates a semaphore, and sets the

operating mode of the -23 module.


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The initiali@ation code for the module and mustbe in!oed before an" of the other functions.

3ispInit+ assumes the presense of a real4time ernel such as C2=OS4II since it uses ser!ices pro!ided

b" the ernel structure.

7@Di:S/?@' This function allows "ou to displa" S2II strings an"where on the displa"s. we can

easil" displa" either integer or floating4point numbers using the standard librar" functions itoa+,

ltoa+), sprintf+, etc Of course, we should ensure that these functions are reentrant if "ou are using

them in a multitasing.

WOR& FLOW'

To the high end de!ices, at times de!ices ma" malfunction or totall" fail due to long

duration of usage or an" technical problem which gi!e fatal results. #mbedded technolog" is

necessar" for continuousl" collecting !alues from onsite and later anal"@ing that as well astaing proper measures to sol!e the problems. Now a da" s"stems that are in use are non real

time operating s"stems based on mono4tas mechanism that hardl" satisfies the current

specifications.

The e" characteristic of an operating s"stem +OS is its abilit" to handle to multiple

tass at a time on a time sharing basis commonl" nown as /ulti4tasing, s"nchroni@ing and

responsible for managing the hardware resources of a computer and hosting applications that

e1ecute on the RTOS ernel structure. Real4time operating s"stem is a speciali@ed t"pe of

operating s"stem where e1ecution of tass has to be done precisel" without e1ceeding the

deadlines and is intended to use for Real4time e!ents.

We will focus on porting of C2=OS4II in R/> controller that performs multitasing and

time scheduling process. Here C2=OS II features and its porting to R/> are implemented. Then

it pro!ides an o!er!iew for design of embedded s"stem using C2=OS II and with respect to the

response of the applications, !arious features can be implemented.

The C2=OS II +pronounced /icro 2 O S & stands for /icrocontroller Operating

S"stem 7ersion & and can be termed as C2=OS4II or u2=OS4II , this is a !er" small real4time

ernel with memor" footprint is about &%86 for a full" functional ernel and source code is

about (%% lines and is mostl" in NSI 2 language. The source is open but not free for

commercial use. X2=OS4II is upward compatible with C2=OS 7'.'' but pro!ides man"


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impro!ements such as the addition of a fi1ed si@ed memor" manager tas deletion tas switch,

Tas 2ontrol 6loc+T26 e1tensions support.

IPLEENTATION

The implementation of this concept consists of both Hardware and Software pproach.

1@H-/,5-/ A::/)-*='

In the proposed s"stem comprises a /aster node controlled b" the -P2&')$

microcontroller which is ha!ing an R/>T3/I based processor. X2OSII RTOS is ported into

this microcontroller and control commands can be gi!en from this section. #n!ironment Real

time temperature !alue, !oltage le!els at sensor node and intrusions which are rela"ed wirelessl"

from sensor node are, also displa"ed on a


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Initiali@ation of the tas' and tas& is been done. lthough supports for total :) tass all

of them are not used at a time in application therefore with respect to demand the tas must be

created.

X2=OS4II can run with ma1imum number of tass of :). The figure shown below the application

has si1 threads.


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6ased On the re*uired application the number of tass ma" !aries. 9or demonstrating a

sample e1periment to understand the porting of C2OSII we can perform simple tass lie

Temperature sensor +32


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This proposed s"stem comprises a /aster node controlled b" a micro controller ha!ing

R/> processor. ?cos4II RTOS is ported into the micro controller and control commands can be

input from this section. 7arious sensors lie temperature !oltage fire and infrared are placed on

data ac*uisition node and Real time temperature !alues !oltage le!els at 3ata ac*uisition node

are wirelessl" rela"ed and also displa"ed on


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sensor !alues can be displa"ed on the serene, this graph displa" is configured through page

selection and data dri!en to GLCD.This is the complete s"stem configuration.

Now R/ node which wors with RTOS has the following resourcesG

' Touch resolution+32

& Serial data reception+?RT5


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CHAPTER%#

SOFTWARE TOOLS

#.1 TYPES OF TOOLS'

8#I- 2

9lash /agic

OR23

2apture

-a"out

#.1.1 &EIL C'

8eil software is the leading !endor for $=':4bit de!elopment tools +raned at

first position in the &%%) embedded maret stud" of the embedded s"stem and ##

times maga@ine.

8eil software is represented world wide in more than )% countries, since the

maret introduction in 'Y$$ the eil 2(' compiler is the de facto industr" standard


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and supports more than (%% current $%(' de!ice !ariants. Now, eil software offers

de!elopment tools for R/.

8eil software maes 2 compilers, macro assemblers, real4time ernels,

debuggers, simulators, integrated en!ironments, and e!aluation boards for $%(',

&(', R/ and J2':1=2':1=ST'% microcontroller families.

The 8eil 2(' 2 2ompiler for the $%(' microcontroller is the most popular

$%(' 2 compiler in the world. It pro!ides more features than an" other $%(' 2

compiler a!ailable toda".

The 2(' 2ompiler allows "ou to write $%(' microcontroller applications in

2 that, once compiled, ha!e the efficienc" and speed of assembl" language.

-anguage e1tensions in the 2(' 2ompiler gi!e "ou full access to all resources of

the $%('.

The 2(' 2ompiler translates 2 source files into relocatable ob0ect modules

which contain full s"mbolic information for debugging with the X7ision 3ebugger

or an in4circuit emulator. In addition to the ob0ect file, the compiler generates a

listing file which ma" optionall" include s"mbol table and cross reference

Nine basic data t"pes, including 5&4bit I### floating4point,

9le1ible !ariable allocation with bit, data, bdata, idata, 1data, and pdata

memor" t"pes,

Interrupt functions ma" be written in 2,

9ull use of the $%(' register bans,

2omplete s"mbol and t"pe information for source4le!el debugging,

?se of /P and 2-- instructions,


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6it4addressable data ob0ects,

6uilt4in interface for the RTJ(' real time ernels,

Support for the Philips $x2>(%, $x2>(', and $x2>(& limited instruction

sets,

Support for the Infineon $%2('> arithmetic unit.

#.1.2 FLASH AGIC'

9lash magic can control the entr" into ISP mode of some microcontroller

de!ices b" using the 2O/ port handshaing signals to control the de!ice.

T"picall" the handshaing signals are used to control such pins as Reset, PS#N

and 722. The e1act pins used depend on the specific de!ice.

When this feature is supported, 9lash /agic will automaticall" place the

de!ice into ISP mode at the beginning of an ISP operation. 9lash /agic will then

automaticall" cause the de!ice to e1ecute code at the end of the ISP operation.

#.1.3 ORCAD'

OR23 reall" consists of tools. 2apture is used for design entr" in

schematic form. Qou will probabl" be alread" familiar with looing at circuits in

this form from woring with other tools in "our uni!ersit" courses. -a"out is a

tool for designing the ph"sical la"out of components and circuits on a P26.

3uring the design process, "ou will mo!e bac and forth between these two tools.

The design flow diagram is gi!en belowG


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Fi.#.1. Di4 5i4,)5 ) ORCAD

#.1.! DESIGN FLOW OF ORCAD'


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%he $!ee$!ee-PO , /o"&les are "esigne" to operate within the Kig!ee

protocol an" s&pport the &niL&e nee"s of low-costE low-power wireless sensor

networks. %he 'o"&les reL&ire 'ini'al power an" provi"e reliable "elivery of "ata

between re'ote "evices. %he 'o"&les operate within the / M. 9: freL&ency

ban" an" are co'patible with the following( percent. This gi!es the capaciti!e s"stem a much clearer

picture than the resisti!e s"stem

).Surface capacitance

In this basic technolog", onl" one side of the insulator is coated with a conducti!e la"er. small !oltage is

applied to the la"er, resulting in a uniform electrostatic field. When a conductor, such as a human finger,

touches the uncoated surface, a capacitor is d"namicall" formed. The sensorVs controller can determine the

location of the touch indirectl" from the change in the capacitance as measured from the four corners of the

panel. s it has no mo!ing parts, it is moderatel" durable but has limited resolution, is prone to false signals

from parasitic capaciti!e coupling, and needs calibration during manufacture. It is therefore most often used in

simple applications such as industrial controls and ioss.

(.Pro0ected capacitance


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Pro0ected 2apaciti!e Touch +P2T technolog" is a capaciti!e technolog" which permits more accurate and

fle1ible operation, b" etching the conducti!e la"er. n JQ arra" is formed either b" etching a single la"er to

form a grid pattern of electrodes, or b" etching two separate, perpendicular la"ers of conducti!e material with

parallel lines or tracs to form the grid +comparable to the pi1el grid found in man" -23displa"s.

ppl"ing !oltage to the arra" creates a grid of capacitors. 6ringing a finger or conducti!e st"lus close to the

surface of the sensor changes the local electrostatic field. The capacitance change at e!er" indi!idual point on

the grid can be measured to accuratel" determine the touch location.Z([ The use of a grid permits a higher

resolution than resisti!e technolog" and also allows multi4touch operation. The greater resolution of P2T

allows operation without direct contact, such that the conducting la"ers can be coated with further protecti!e

insulating la"ers, and operate e!en under screen protectors, or behind weather and !andal4proof glass.

P2T is used in a wide range of applications including point of sale s"stems, smartphones, and public

information ioss. 7isual PlanetVs 7iP Interacti!e 9oil is an e1ample of a ios P2T product, where a glo!ed

hand can register a touch on a sensor surface through a glass window.Z:[#1amples of consumer de!ices using

pro0ected capaciti!e touchscreens include pple Inc.Vs iPhone and iPod Touch, HT2Vs H3&,


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This latter problem is a result of bacground light increasing the noise floor at the optical sensor, sometimes to

such a degree that the touchscreen\]^s -#3 light cannot be detected at all, causing a temporar" failure of the

touch screen. This is most pronounced in direct sunlight conditions where the sun has a !er" high energ"

distribution in the infrared region.

Howe!er, certain features of infrared touch remain desirable and represent attributes of the ideal touchscreen,

including the option to eliminate the glass or plastic o!erla" that most other touch technologies re*uire in front

of the displa". In man" cases, this o!erla" is coated with an electricall" conducting transparent material such as

ITO, which reduces the optical *ualit" of the displa". This ad!antage of optical touchscreens is e1tremel"

important for man" de!ice and displa" !endors since de!ices are often sold on the percei!ed *ualit" of the user

displa" e1perience.

nother feature of infrared touch which has been long desired is the digital nature of the sensor output when

compared to man" other touch s"stems that rel" on analog4signal processing to determine a touch position.

These competing analog s"stems normall" re*uire continual re4calibration, ha!e comple1 signal4processing

demands +which adds cost and power consumption, demonstrate reduced accurac" and precision compared to

a digital s"stem, and ha!e longer4term s"stem4failure modes due to the operating en!ironment.

>.Strain gauge

In a strain gauge configuration, also called force panel technolog", the screen is spring4mounted on the four

corners and strain gauges are used to determine deflection when the screen is touched. This technolog" has

been around since the 'Y:%s but new ad!ances b" 7issumo and 94Origin ha!e made the solution commerciall"

!iable. It can also measure the ;4a1is and the force of a personVs touch. Such screens are t"picall" used in

e1posed public s"stems such as ticet machines due to their resistance to !andalism.

$.Optical imaging

relati!el"4modern de!elopment in touchscreen technolog", two or more image sensors are placed around the

edges +mostl" the corners of the screen. Infrared baclights are placed in the cameraVs field of !iew on the

other sides of the screen. touch shows up as a shadow and each pair of cameras can then be triangulated to


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locate the touch or e!en measure the si@e of the touching ob0ect +see !isual hull. This technolog" is growing in

popularit", due to its scalabilit", !ersatilit", and affordabilit", especiall" for larger units.

Zedit[3ispersi!e signal technolog"

Introduced in &%%& b" 5/, this s"stem uses sensors to detect the mechanical energ" in the glass that occurs

due to a touch. 2omple1 algorithms then interpret this information and pro!ide the actual location of the touch.

Z'%[ The technolog" claims to be unaffected b" dust and other outside elements, including scratches. Since

there is no need for additional elements on screen, it also claims to pro!ide e1cellent optical clarit". lso, since

mechanical !ibrations are used to detect a touch e!ent, an" ob0ect can be used to generate these e!ents,

including fingers and st"lus. downside is that after the initial touch the s"stem cannot detect a motionless

finger.

Y.coustic pulse recognition

This s"stem, introduced b" T"co InternationalVs #lo di!ision in &%%:, uses more than two pie@oelectric

transducers located at some positions of the screen to turn the mechanical energ" of a touch +!ibration into an

electronic signal.Z''[ The screen hardware then uses an algorithm to determine the location of the touch based

on the transducer signals. This process is similar to triangulation used in


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e1posure times. Instead of pinholes, an arra" of li*uid cr"stals could wor similarl" but more effecti!el"G The

-23Vs panel is composed of patterns of 'Y4b"4'Y blocs, each di!ided into a regular pattern of differentl"

si@ed blac4and4white rectangles. #ach white area of the bi4colored pi1els allows light to pass through.

6acground software uses )3 light fields to calculate depth map, changes the scene, and collects gesture

information. The -23 alternates between mas pattern displa" and a normal scene displa" at a !er" high

fre*uenc"=rate.


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CHAPTER%8

$.2ON2-?SION

. The RTOS is to manage the allocation of these resources to users in an orderl" and controlled

manner. This wireless sensor node is composed of a micro4processors, transcei!ers, displa"s and

analog to digital con!erters. Sensor nodes are deplo"ed for industrial process monitoring and

control. The sensing parameters can be displa"ed as graph in /aster node. The basic !iew of this

techni*ue is to reduce the possibilit" of collision and to meet the critical re*uirement of timing

for data transmission of industrial applications

Documents

An Rtos-based Architecture for Industrial Wireless Sensor Network Stacks With Multi-processor Support(1)