North-Holland Microprocessing and Microprogramming 28 (1989) 315-318 315

AN OVERVIEW OF THE SYSEDIT CHIP DESIGN ENVIRONMENT

Stefan Rust

Institut f~r Informatik, Universit~t Stuttgart, Azenberg Str. 12, 7000 Stuttgart i, West Germany

Abstract:

A graphical tool for the system- and architecture design using application specific integrated circuits is presented. The tools for the system level, register transfer level, and floorplan/layout level are described. The design flow from algorithms to a system consisting of software, firmware, and hardware using different tools from a tool- box and the design automation capabilities are explained.

1. INTRODUCTION

The complexity of todays integrated circuits and systems brings increasing demands to chip design environments.

One important demand is the support of the system design phase which includes the development of the system structure, the specification of the system behaviour and the design of the algorithms which have to be performed. A second demand is to support not only the design of the hardware but of the firmware and software components of a complete system (embedded ASICs).

To make the design process easier the design steps must be automated. So the design system must support design synthesis features at different levels of abstraction. The designer must be enabled to customize the design synthesis to his specific needs. He must be supported by graphical tools to have an overview of the design results and to interact quickly with the synthesis process~ It should also be possible for the designer to include domain specific knowledge in the synthesis tools of the design system in an easy way.

SYSEDIT is an experimental design environment for the development of graphical tools for the system- and architecture synthesis of systems using application specific integrated circuits [i]. It supports the designer from the system- and algorithm design to the floorplan and layout design in an integrated design environment.

SYSEDIT consists of graphical editors for the design of the system behaviour and structure, the architectural level (RT level), and the geometrical level (floorplan and layout). These editors allow the hierarchical description of the design at different levels of abstraction.

The partitioning of the design in hardware- and software- moduls and the development of a layered system structure is supported by a general system description (SIL).

Each level can be verified through the automatic generation of simulation models for DACAPO-II (behavioural level), KARL-III (RT-level), and RELAX (layout extraction).

A toolbox will support the designer in the analysis of the current design, the synthesis of new design modules, and the optimisation of the design at the different design levels. The designer can use the toolbox to explore the different design alternatives. The tools are adapted to the use in an interactive environment. The synthesis tool execution is divided in two parts. In an analysis step, the informations for the synthesis is collected, and internal tables are filled with the results. The results and a statistic overview is displayed and then the designer can decide, whether to apply the synthesis to the design data, to change the internal tables, or to change the initial design and start the analysis and synthesis tools again.

316 S. Rust / SYSEDIT Chip Design Environment

A design language interpreter, which is integrated in the design environment, allows the interactive development of design automation tools and the control of the design tool execution. The design language permits the description of design steps with rules and knowledge frames.

The designer can use SYSEDIT in different ways:

* The design can be done completely interactive

* The design can be done by the interactive use of the analysis-, synthesis, and optimisation tools for the different design levels (interactively guided synthesis)

* The designer can automate design tasks by describing the rules for the different design steps with the design automation language

SYSEDIT uses a common user-interface and a simple database for all tools. A mult i-window environment permits a parallel view on different design aspects [2].

SIL SIL I Compiler J I CompilerJ

RT-SA/SD SIL-Editor

Design Language

UCAMS JFirmware IHardware I AssemberJ JSynthesis JSynthesis I

Figure 1: The System Level Design Flow

2. THE SYSTEM LEVEL DESIGN TOOLS

The system level tools (figure 1) support the description of the system structure and the algorithms used in the system (detailed system behaviour). The design methods are adapted from concepts of computer aided software engineering environ- ments.

The initial design consists of a structural or functional system description. The overview of the system structure is done with the graphical PMS notation. The system functions can be described using the RT-SA/SD method [3]. The detailed behaviour is assembled from algorithmic descriptions written in DACAPO-II [4] or the "C" language [5]. These descriptions are compiled to SIL, a system intermediate level description comparable to the controlf low/dataflow description in other high level synthesis systems.

The elements of the system level are:

* Control-f low elements like assign, switch, fork, and join

* Communication elements like send/receive

* Calls and procedures for the description of different layers

* Functions for the description of dataflow operations

* Data nodes for the descriptions of variables

The SIL description is the internal datastructure of the system level editor. The editor gives an graphical overview of the system functions and structure and the control- and dataflows. The control- and dataflows can be extended and improved with the graphics editor. An analysis tool will give a statistics of the design and an overview on the layer-structure.

A set of tools will allow optimisations, parallelisation, and controlf low and dataflow trans- formations to improve the implementation of the algorithms. For the generation of the architectural level the different layers of the SIL description have to be translated to hardware, firmware, and software.

The controlflows and dataflows of the

S. Rust I SYSEDIT Chip Design Environment 317

hardware- and firmware layer will be transfered directly to the RT-level by the use of a scheduler tool, a variable and function binding tool and a connection tool. The scheduling and binding can also be done interactively. These tools generate the graphical RT-level symbols and place them in the RT-level editor so that the result can be seen immediately. The software level will be generated with a machine language independent assembler.

i ocA s i "r--r" I I--w"" I Assembler Synthesis Synthesis

KARL-Ill 1 / / 1 ~R -~,1E'~ ~'krdPrtogr ram I

De:ll ga~ e I

Netlists Cell Floorplen J Generator J [ Estimation J

Figure 2: The RT-Level Design Flow

4. THE FLOORPLAN/LAYOUT DESIGN TOOLS

The floorplan and layout design tools (figure 3) are extending the design environment to the specific needs for the realisation of a design using application specific integrated circuits.

It is important to get an overview of the possible chip floorplan already in early design phases. This supports the estimation of the feasibility of the system. SYSEDIT allows the transfer of the RT-level modules to an estimated floorplan [7].

I Netllsts

\

I @

= i Generator Estlrnetlon Routing Layout

Editor I

Loader Language

Procedural CIF Layout

Cell Loader Language

I CIF Generator

Figure 3: The Layout Design Flow

3. THE RT-LEVEL DESIGN TOOLS

An overview of the RT-level tools is given in figure 2. The RT-level consists of the graphical description of the RT-structure and RT-behavior. The RT-structure is described with predefined elements, for example registers, memories, busses, alus, and logic blocks. These elements are translated to the hardware description language KARL-III for simulation. New RT-level elements are created by reading KARL-III descriptions into the RT-level editor.

The RT-level behaviour is described using control unit blocks [6]. These control unit blocks are used for the specif ication of the desired register transfers using a microprogram flow-chart editor. The generated register transfers can be displayed and improved. For simulation purposes a control unit description in KARL-III is generated from the flow charts.

The size of the module can be found in different ways:

* The size of the modules can be specified directly

RT-elements can be estimated by their parameters (i.e. the word- size)

A description file gives the mapping of the design modules to predesigned layout elements. The CIF cell description can be loaded into the layout editor.

With a procedural layout function library the layout for the RT-level elements is created

The estimation of the size of the control unit will be based on the size of the RT level behavioural description and the number of control lines (wordsize of the microinstructions)

318 S. Rust / SYSEDIT Chip Design Environment

The layout editor has also full custom design features and can be used for leaf cell design.

The shape of the modules and the wiring information can be written to a file so that external placement and routing tools can be used for the layout assembly.

Kaiserslautern, and Mr. Roos and Dr. Schwederski from the Institut f~r Mikroelektronik, Stuttgart for helpful discussions. Also I want to thank Prof. Dr. W. H. Burkhardt for supporting the SYSEDIT project.

The final layout is transfered to a CIF-File, which can be checked and extracted for verif ication purposes.

5. Status and Future Research Plans

The SYSEDIT design environment is intended to be a prototype and can not fulfil the needs of commercial design systems. The database, the user interface, the graphical editors, a prototype of the design language [8], and some tools of the toolbox has been implemented. The main work is now to extend the toolbox for the analysis, synthesis, and optimisation tasks and use the design automation capabilities for different chip designs.

The development of SYSEDIT uses an incremental software design to get quickly a working prototype for research. For this reason SYSEDIT has been structured so that the different levels can be developed and improved independently.

The SYSEDIT environment is implemented in C on the UNIX BSD 4.2 operating system. The programs can be easily adapted to different workstations by changing the portable graphics library. SYSEDIT has been implemented on APOLLO DN 3000 and SUN 3/60 workstations.

REFERENCES

[i] Rust, S., An Experimental System Design Environment for Chip Design, in: Proceedings 2nd ABAKUS Workshop, Universit~t Kaisers- lautern, 1988.

[2] Holzwarth, P., Entwurf und Imple- mentierung von Benutzerschnitt- stelle, Datenstrukturen und Modul- verwaltung des Multi-Level Editors SYSEDIT, Diplomarbeit Nr. 549, Institut f~r Informatik, Uni- versit~t Stuttgart, 1988.

[3] Bosch, J., Ein System Design Tool f~r ASICs, Diplomarbeit Nr. 593, Institut f~r Informatik, Uni- versit~t Stuttgart, 1989.

[4] F6rderreuther, J., Implementierung eines Compilers f~r die Hardware- Beschreibungssprache DACAPO II unter Verwendung von LEX und YACC, Studienarbeit Nr. 773, Institut f~r Informatik, Universit~t Stutt- gart, 1989.

[5] Janosch, M., Umsetzung von in der Programmiersprache C beschriebenen Algorithmen in die System- beschreibungssprache SIL, Studien- arbeit Nr. 776, Institut f~r Informatik, Universit&t Stutt- gart, 1989.

ACKNOWLEDGEMENTS

Thanks to the students which are helping me to implement and improve the SYSEDIT environment: Winfried Baum, Ulf Bachmann, J~rgen Bosch, Christoph Braun, Johannes F6rder- reuther, Manfred Janosch, Clemens Haimann, Peter Holzwarth, Georg Ruzicka, Bernhard Schloss, Markus Siegle and Ralph W6rn. I want to thank Prof. Dr. R. W. Hartenstein and his group from

[6] Bachmann, U., FluBdiagramm-Editor f~r Mikroprogramme, Software Praktikum II, Institut f~r Informatik, Universit~t Stutt- gart, 1989.

[7] Schloss, B., Layout-Editor/Floor- planner f~r SYSEDIT, Studienarbeit Nr. 766, Institut f~r Informatik, Universit~t Stuttgart, 1989.

[8] Siegle, M., Implementierung eines experimentellen Expertensystems f~r das Chip-Design, Diplomarbeit Nr. 597, Institut f~r Informatik, Universit~t Stuttgart, 1989.