An Open Architecture, Server- Based Solution for Next ...€¦ · Channel, Open Architecture EW Solution Digitization Layer– COTS A/D Solution Digitizes and Multicasts all CDIF

An Open Architecture, Server-

Based Solution for Next Generation

Electronic Warfare System

19 March 2015

Copyright 2015 Lockheed Martin Corporation: No part of this publication may be reproduced or transmitted in any form, or by

any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without

written permission from Lockheed Martin.

Greg Gannett

Outline

Electronic Warfare Overview

IR&D Backstory

System Architecture

Network and GPU Performance

Copyright 2015 Lockheed Martin Corporation 2

The EW Battlespace & RF Spectrum Challenge


• Our Customers Need The Ability to Detect, Analyze, and React to Emitters in the Battlefield

• Modern EW Systems need to measure and report the entire RF Spectrum

• The RF spectrum is both wide and dense

• The emitters are diverse : commercial and military

• Emitters are becoming more agile with the landscape constantly changing

Previous approaches of selective listening on known emitters are not adequate

VHF UHF SHF EHF

300 MHz 100 MHz 4 GHz 6 GHz

S C X

8 GHz

Ku K

12.5 GHz 18.0 GHz 26.5 GHz 40.0 GHz

Ka

30.0 GHz

L

2 GHz 1 GHz

V

75.0 GHz

W

Example emitters are representative and randomly placed on RF spectrum

EW System Architecture - Basic


RF

Time

Ampl

Pulse Detection &

Measurement

Clustering

Deinterleaving

Parameter Measurement

Emitter Tracking

Emitter Classification

FLOPS Breakdown

Digitized IF

Pulse Data Words

Signal Data Control Data

Other

IO Bandwidth Breakdown

RF Distribution

Hardware

Tuners Digitizer Pulse Detection &

Measurement

Signal

Processing

RF IF RF

Ant

Displays

Combat

System

Digitized IF Pulse Data Words

Analog Digital

Pulse Detection &

Measurement Type m

EW System Architecture – Scaled


RF Distribution

Hardware IF

RF

Ant

Tuners Digitizers Signal

Processing Type x

RF Distribution

Hardware IF

RF

Ant

Tuners Digitizers Displays

Combat

System

RF Distribution

Hardware IF

RF

Ant

Tuners Digitizers

Contempory EW Systems will have multiple subsystems with specialized features

Signal

Processing Type y

Signal

Processing Type z

Subsystem 1

Subsystem 2

Subsystem 3

Pulse Detection &

Measurement Type n

Pulse Detection &

Measurement Type o

$$$$$

RF Distribution

Hardware IF

RF

Ant

Tuners Digitizers

Alternative: Digitize Once, Publish CDIF Data to Pulse and Signal Processing

Pulse Detection &

Measurement

Type m

Pulse Detection &

Measurement

Type n

Pulse Detection &

Measurement

Type o

Pulse Detection &

Measurement

Type m

Pulse Detection &

Measurement

Type n

Pulse Detection &

Measurement

Type o

$

Displays

Combat

System

Common Single Channel Sizes: 80 MHz, 375 MHz, 500 MHz

Single Channel of 500 MHz RF Digitized Data: ~2.7 GB/sec

I&RD Project Objectives

Key Tenants Envisioned for Next Generation EW System

Architectures

• Digitize the Spectrum and Distribute CDIF via a Flexible Digital Backbone

• Deliver new capability via mission and target-specific software applications

hosted on a common hardware solution

• Replace custom, proprietary interfaces with open, standardized interfaces to

facilitate rapid and affordable capability insertion

Server-Based Electronic Warfare Engineering Development Model

• Objective: To evaluate the ability of current & projected COTS technologies

to realize Next Gen EW Architecture Vision


Validate key COTS technologies: RF digitization, high-

speed networks and high-speed computing environment

Migrate pre-existing FPGA and PowerPC based receiver

processing to Linux Servers and Intel & NVIDIA

accelerators

Demonstrate scalability of architecture to greater

bandwidths (wideband feasibility)

Validate Open Interface Data Distribution Services (DDS)

publish / subscriber services

Verify key TPMs: CDIF throughput, Processing

Bandwidth, Measurement Accuracy, Dynamic Range

Objectives

Enabling Technologies PCIe Gen 3.0

High Speed Network

General Purpose GPUs

COTS A/Ds Digitizers

Intel Xeon Multicore CPUs

•Open standard with accelerated performance road map •More configurable, higher

bandwidth than VME •Today: 7.88 GB/sec (8xGen 3) •Next Gen: 15.7 GB/sec (8xGen 4)

•Widely used open standard provides most bandwidth solution •User level multicast •Near term (2015) projection of

>100 Gbps •Today: 7GBps per channel •Next Gen: 12.5 GBps per channel

•Excellent GFLOP/watt ratio •Cost benefit over FPGA •High-order SW language •Vast CUDA libraries •Today: Kepler GPUs with ~5

GFLOPS per watt •Next Gen: Maxwell GPUs with

~12 GFLOPS per watt

•Excellent GFLOP/watt ratio •Supports numerous High-order

programming languages •Most mainstream target processing

environment •Today: 2600 Xeons •Next Gen: Xeons with Phi

Accelerator

•Easily scaled across general purpose HW hosts •Flexibility in configurations •Publish source I&Q data •Today: 12 bit @ 500 MHz •Next Gen: 16 bit @ 500 MHz

Architecture

Linux

Server

ADC

PC

Ie ADC

ADC

ADC

I/O

I/O

1 GHz IF

1 GHz IF

56

Gb

In

fin

iba

nd

Sw

itch

CDIF

RF Digitization High Speed

Network

High Speed

Computing

Linux

Server

PDWs

Linux

Server

PC

Ie

I/O

GPU

GPU

I/O

Linux

Server

PC

Ie

I/O

GPU

GPU

I/O CDIF

CDIF

Data Processing

Emitter

Reports

Spectrum

Display

1 GHz IF

Server-Based Electronic Warfare Demonstrator Advanced Development Model Overview


100% COTS Architecture Provides an Open, Scalable, Upgradable and Affordable Solution

EW Advanced Development Model – First Generation

Next Generation EW System – Tactically Relevant, Multi-

Channel, Open Architecture EW Solution

Digitization Layer– COTS A/D Solution

Digitizes and Multicasts all CDIF Data to a

Scalable Number of Processing Nodes

Processing Layer – COTS GPGPUs Perform

Bulk of Real-Time Signal Processing with Multi-

Core CPU’s Completing the Balance High Speed Network– 56 Gbps per

channel Infiniband Network


A/D

Digitization Tuners

Channelized

Receivers G

PDW

Clustering G

Deinter-

leaving Parameter

Measurement

Emitter

Processing &

Classification

Tune

Scheduling &

Control

Real-Time Integration Displays G

Track File

A/D Data (3x)

Tune Cmds PDW

Clusters PDWs Pulse Trains

Emitter Reports

Emitter Detections

C&D

Digitization Layer Receiver Layer Signal Processor Layer

Display Layer

Track File

Mainline Online Mainline Online

Server-Based Electronic Warfare ADM Software Overview

FDR Infiniband

GbE DDS (Pub/Sub)

Key

G GPU-based Processing

Multiple channels of Continuous

Digital IF (CDIF) are multi-cast over

an open, high speed network for consumption by multiple users.

Receiver, Signal and Data Processing is

hosted on Linux Servers featuring

NVIDIA and Intel accelerators supporting higher order programming languages.

IF inputs digitized via COTS A/D

converters (12 bit, up to 1.8 Gsps)

hosted on PCIe slots on a Linux Server.

Standardized open interfaces between software

modules are implemented via Data Distribution

Services (DDS) to enable real-time, reliable and

scalable data exchanges between publishers and subscribers.

The core EW processing thread, tested and proven

on an adjacent defense program, has been further

migrated to an open, scalable, maintainable and affordable architecture.


Open Architecture and Modular, Software-Based Solution Facilitates Rapid Capability

Insertion in Response to New and Evolving Threats

Channelized Receiver GPU Implementation & Timeline


Integer to Floating Point

Conversion

Pre-Sum (Polyphase)

FIR Filter

Receiver Pre-processor

Global Memory 2.7 **

2.7

Fast Fourier

Transform (FFT)

FIR Filter

Magnitude/ Phase

Magnitude Block Integrator

Phase Block Integrator

Constant False Alarm Rate (CFAR)

Pulse Detection

Xeon CPU

PDWs

CDIF

Kepler GPU

Phase Block Integrator

7.3

0.8

15.4 PDWs

0.1

** All Numbers are GB/sec per channel

2013 2014 2015 Quadro 4000 Telsa K20x Telsa K40

Telsa K8 Telsa K80

Architecture

trade studies

Initial SW implementation

using CUDA Libraries

Transition to hand

coded of Kernels

Development Timeline

Achieved Single 500

MHz Channel per GPU

Began transition to 2

channels per GPU

Achieved Two 500 MHz

channels per K40 CUDA 6.5 (10%

performance gain)

7.3

7.3

7.3

7.3

7.3

Benchmarks – 3 Generations of GPGPUs


0.0 5.0 10.0 15.0

NoMod,10,Edge

NoMod,100,Edge

NoMod,1k,Edge

NoMod,10k,Edge

Wide PSK

Many

CW,Edge

CW,LFM

Many+CW

Many+CW,LFM

NoMod,20k,Edge

FFT

Mag Block

Phase Block

CFAR

Detect

Measure

CW

Tesla K20x (3/14) Design Goal

0.000 1.000 2.000 3.000 4.000 5.000 6.000

adc_out_matlab_1k_center_snr_30

adc_out_matlab_1k_edge_snr_30



adc_out_matlab_fmcw_500_center_s…



adc_out_matlab_cw_edge_snr_3

adc_out_matlab_bpsk_25ns_edge_sn…

adc_out_matlab_1M_center_snr_30

adc_out_matlab_1M_edge_snr_30

adc_out_matlab_many_snr_15_with_…

adc_out_matlab_many_snr_15

adc_out_matlab_many_snr_15_with_…

FFT

Block

CFAR

Detect

Measure

PDW

Tesla K40 (1/15) Design Goal

0.000 1.000 2.000 3.000 4.000 5.000 6.000





adc_out_matlab_fmcw_500_center_…



adc_out_matlab_cw_edge_snr_3

adc_out_matlab_bpsk_25ns_edge_s…

adc_out_matlab_1M_center_snr_30

adc_out_matlab_1M_edge_snr_30

adc_out_matlab_many_snr_15_with…

adc_out_matlab_many_snr_15

adc_out_matlab_many_snr_15_with…

FFT

Block

CFAR

Detect

Measure

PDW

Tesla K-80 Performance – on one (of two) GK210 GPUs Design Goal

Kernel K40 K80 (per GPU)

Samples 13330000 13330000

Threads 1666250 1666250

Ops 1.14638 1.14638 Gflops

Time 1.058 1.185 ms

Ops/s 1084 967 Gflops

700 GLOPS typically advertised for Single Precision

cuFFT processing (FFT length of 4096)

Tesla K-80 Single Precision Performance (Constant Data Stream)

cuFFT 6.0 on K40c, ECC ON, 32M elements, input and output data on device

Real-time Instrumentation


• Software monitors all network related

resources and provides real-time

feedback on current throughput

• Screen capture confirms Multicast

Infiniband of high bandwidth Digitization

Data

• Software monitors utilization of GPU

resources

• Color-codes various stages of the

Channelized Receiver processing over

time

Signal Processing Displays


Both Core Signal Processing Software and Real-time Signal Processing displays hosted

on GPU processors

Summary

Conclusions

• The Enabling Technologies are moving fast driven by wide commercial /

non-defense markets

• We continue to be encouraged by results to date and anticipate continued

performance gains due to ongoing COTS evolution


Next Steps

• The transition of this server-based

architecture to a tactical system is

underway

• Extend architecture to additional

applications across the RF/EW

enterprise

– Through integration of mission and

target-specific SW applications

– Through continual integration of next

generation COTS HW technologies

As the Technology Matures, More Systems will Adopt, Accelerating Development

1.0 – Complex Pulse Measurement - Background

Pulse Filtering and Channelizer Compensation

Summary:

• To achieve wideband coverage, the RF spectrum is divided into

channels and further sub-divided into sub-channels

• The division/sub-division of the RF spectrum creates conditions

that have to be accounted for various signal types in order to

accurately measure/characterize the RF environment

Min Freq Channel n Channel n+1 Channel n+2 Channel n+3 Channel n+4 Channel n+5 Channel n+6 Channel n+7 Channel n+8

Max Freq

SubChannel 1 SubChannel n . . . RF Sub-Channels & Channelization: created by

(early stage) signal processing

RF Channels: created by tuners/receivers.

Nominal Stable RF signal : No issues

Signal at sub-channel edge

Signal at channel edge

LFM Pulses at sub-channels edge

LFM Pulses at channels edge

Strong signal with corresponding rabbit ears

Pulse andduplicate

Duplicate at loweramplitude

Falling edge rabbit ears

Rising edge rabbit ears

Copyright 2015 Lockheed Martin Corporation

FFT Performance


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An Open Architecture, Server- Based Solution for Next ...€¦ · Channel, Open Architecture EW Solution Digitization Layer– COTS A/D Solution Digitizes and Multicasts all CDIF