https://doi.org/10.1007/s10836-019-05827-7

An Integrated Framework for Application Independent Testingof FPGA Interconnect

Shukla Banik1 · Suchismita Roy1 · Bibhash Sen1

Received: 17 May 2019 / Accepted: 9 September 2019© Springer Science+Business Media, LLC, part of Springer Nature 2019

AbstractThis paper presents a FPGA interconnect test configuration generation strategy for application-independent testing usingSatisfiability (SAT). The technique generates all possible path configurations for the interconnect to obtain full coverage ofall interconnect resources. The integrated testing approach is proposed which generates test vectors and path configurationsin a single phase, thus obtaining a significant reduction in the number of test configurations needed to test the circuit. Togenerate test configurations, constraints have been designed using SAT. The proposed technique targets open and short faultsin the interconnect resources. Test configurations have been generated for different FPGA architectures. The objective ofthe proposed approach is to minimize the number of configurations without reducing the fault coverage.

Keywords Application-independent testing · Field-programmable gate array (FPGA) · Interconnect ·Testing · Test configurations

1 Introduction

Field Programmable Gate Arrays (FPGAs) are pre-fabricated electronic devices that can be programmed toimplement any digital logic in the field. FPGAs arevery popular target devices for various range of applica-tions as they are reprogrammable and also provide fastertime to market solutions as compared to other ICs (e.g.ASIC). The main components of FPGAs are configurablelogic blocks (CLBs), programmable interconnection net-work and programmable input/output blocks (IOBs). Theconfigurable logic blocks are used to implement a user-defined logic function. CLBs are generally placed in a two-dimensional grid and are interconnected by a programmable

Responsible Editor: R. A. Parekhji

� Shukla Banikshuklabanik86@gmail.com

Suchismita Roysuchismita.roy@cse.nitdgp.ac.in

Bibhash Senbibhash.sen@cse.nitdgp.ac.in

1 Department of Computer Science and Engineering,NIT Durgapur, Durgapur, India

interconnection network. CLBs contains all the resourcesthat are required for implementing an user-defined digitaldesign to be implemented on a FPGA. Inside CLBs, thereexist Look-up tables(LUTs), flip flops, multiplexers etc. Alook-up table can be used to implement an n-input user-defined combinational logic function. I/O blocks provideall the input/output connections to the FPGA. These areplaced at the boundary of the grid and are connected to theprogrammable interconnect. The interconnection resourcescomprise of line segments and programmable switches.Connections among line segments can be altered by pro-gramming the corresponding switches. Among all the cir-cuit components, the interconnections are most error-prone,as they occupy a huge die area and also contain an enormousnumber of transistors. Hence interconnection resources test-ing is very important in order to guarantee the correctfunctionality of the FPGA. Also, FPGA interconnectiontesting should cover maximum possible faults found in theinterconnection network.

In the proposed approach, the entire FPGA interconnec-tion is tested for opens and short faults found in the inter-connection resources i.e. line segments and programmableinterconnection points (PIPs). The key features of the pro-posed approach are listed below:

• the proposed technique uses SAT based modeling of theproblem to generate test configurations for the entireinterconnect.

Published online: 18 October 2019/

Journal of Electronic Testing (2019) 35:729–740

• path configuration generation and test vector generationis combined into an integrated framework to obtain theminimum number of test vectors needed to test for allopen and short faults in the interconnects.

• this approach does not address a specific architecture,rather it can be applied to various types of FPGAs,which shows the flexibility and scalability of theproposed test generation method.

Based on the available FPGA testing approaches, FPGAinterconnects testing methods are broadly categorized asapplication dependent and application independent [17].Application dependent testing does not test the entire FPGAresources, but aims to test only the resources that have beenutilized in a specific design or application. This type oftesting is favourable for application specific FPGAs wherethe design will be fixed for the lifetime of the device. Onthe other hand, application-independent testing targets theentire FPGA. It is also known as ”manufacturing testing”.In this approach, the FPGA interconnect is tested for allpossible configurations to test all the resources. This type oftesting can assure the reliability of an FPGA device. It doesnot concentrate on testing only design specific resources,rather it deals with all the resources that may be used insome design and therefore it broadens the acceptability ofthe FPGA, irrespective of the application to be built on it.

FPGA configuration time is a crucial factor for FPGAtesting. More number of test configurations will take alonger time to test the FPGA. The test vector applicationtime is less significant compared to the time needed toconfigure an FPGA before applying the test vector. So aminimum number of test configurations must be achieved toreduce the FPGA test time.

The novel features of the proposed work are discussedbelow:

• The novelty of the work lies in its strategy of generatinga minimum number of test configurations using SATbased modeling of the problem. The proposed approachutilizes the ability of SAT to express various attributesof the test configuration generation method with thehelp of arithmetic constraints. SMT solver Z3 willsolve this problem by extending the underlying SATsolver and taking help of the theory of arithmetic. Also,SMT supports optimization, with the help of which theobjective function has been designed to minimize thenumber of configurations required to test the FPGAinterconnect.

• The traditional application independent testingapproach is based on two separate phases, the firstphase produces path configurations and in the secondphase test vectors are generated. Each path configu-ration represents programmable connections betweenadjacent interconnect resources. Each configuration

is then tested for different faults using suitable testvectors. In the existing literature, for application inde-pendent testing methods, the objective is to obtain aminimum number of path configurations. For eachconfiguration, to test the resources (paths), mostlycounting sequence algorithms have been used to gener-ate test vectors to test for interconnect faults. This workproposes SAT-based technique to obtain test vectors forthe most significant interconnect faults like open andshort faults. In this work, a SAT-based framework isproposed which is able to obtain a minimum numberof test configurations by an integrated approach forpath configuration generation along with test vectorgeneration.

The satisfiability problem deals with finding asatisfiable assignment of the variables of a problemrepresented as a first-order logic formula. Various typeof problems from different areas (such as verificationof hardware and software, routing problem etc.) can besolved using satisfiability. Boolean satisfiability (SAT)solvers are used to solve problems that are describedusing Boolean formulae. Satisfiability Modulo Theories(SMT) is the problem of finding if a formula issatisfiable with respect to some background theory [2].SMT solvers also offer the use of optimization functionswhich was missing in Boolean SAT solvers. Problemsusing minimization or maximization functions canbe easily encoded using SMT solvers. Various SMTsolvers are available now such as Z3, Yices etc.

All the traditional application independent testingapproaches [9, 13, 19, 20] are based on two separatephases, the first phase produces path configurationsand in the second phase test vectors are generated.This article proposes a novel integrated frameworkto generate path configurations and test vectors in asingle phase. This reduces the number of configurationsand test vectors required to test the interconnect. Theproposed technique is also architecture independent.To generate test vectors, mostly counting sequencealgorithm is used in the literature [7, 20]. Using theproposed SAT based model a significant improvementin terms of test vectors number can be achieved.

This article is a substantially extended version of[1], where the path configuration generation techniqueis only a part of the integrated test configurationgeneration framework. The article is organized asfollows: Section 2 presents a brief background of theXilinx FPGA architecture and fault models used to testinterconnect resources. Section 3 describes our pathconfiguration generation strategy. Section 4 illustratesthe SAT-based test generation approach. In Section 5,we present the integrated framework for the generationof test configurations and test vectors in a single phase.

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Experimental results are presented in Section 6. Finally,Section 7 concludes this paper.

2 Background

2.1 FPGA Interconnect Structure

FPGA interconnection resources consist of line segmentsand switch matrices. Inside switch matrices, the pro-grammable interconnection points are used to connect vari-ous line segments. Different type of line segments are foundin different FPGA architectures. For e.g. single-length linesare used to connect adjacent CLBs, double-length line seg-ments connect CLBs that are two blocks apart, hex-lengthline segments connect CLBs that are three or six blocksapart. Similarly, pent type of line segments connects CLBsthat are five blocks apart. The FPGA switch matrix literallyacts as a black box. Different type of horizontal and verticalline segments entering into the switch matrix are con-nected through programmable interconnection points(PIPs).As these interconnection points are programmable, a con-nection can be established between desired line segmentsby programming the appropriate PIP. The FPGA configura-tion memory is used to store the PIP values. The PIP valuewill be changed once the connection breaks up. Similarly,a new connection can be done between two line seg-ments by changing the corresponding PIP values. As thesePIPs are used to connect different type of line segmentsinside the switch matrix, therefore PIPs can be catego-rized as single-single PIP, hex-hex PIP, hex-single PIP andso on.

Generally, the connections between line segments, insidethe switch matrix are controlled by pass transistors. Eachswitch box contains six pass transistors. These passtransistors are programmable, which provides the routingflexibility inside the switch box. In Fig. 1 an architectureof a Virtex FPGA is shown. The switch matrix pointsW1-W4 indicates the terminal points of west direction,similarly, terminal points of east, north and south directionsare denoted by E1-E4, N1-N4 and S1-S4 respectively.

A programmable interconnect point (PIP) actuallyconsists of one or more transmission gates. A PIP canbe controlled by a configuration memory bit. Three typesof PIPs are found in the FPGA architecture, break-pointPIPs, cross-point PIPs and multiplexer-PIPs [11]. Break-point PIPs are used to establish a connection between eitherhorizontal or vertical line segments. The cross-point PIPsare responsible for connecting horizontal and vertical linesegments. A group of transmission gates and more than onelevel of configuration memory bits to the gates can be usedto implement a multiplexer based PIP.

Each switch box offers interconnection among linesegments in six directions, north-south, north-east, north-west, east-west, east-south and west-south. Li-ne segmentsare generally arranged in horizontal as well as verticalmanner across the four sides of a switch box. XCV300contains 24 single lines and 12 hex lines. Some of theselines are bidirectional and rest of them are unidirectional.Based on the number of CLBs connected by a line segment,these line segments are categorized as long lines, single-length, double-length, hex-length etc. Long lines are usefulfor connecting nets which are placed far away. Also, longlines are responsible for carrying time-critical signals. PIPscan also be classified as intra-PIP and inter-PIP [11]. PIPswhich establish a connection between the same type of linesegments are called intra-PIPs (e.g. single-single PIP). Onthe other hand, PIPs that are used to connect different typeof line segments are called inter-PIPs (e.g. hex-single PIP).

The interconnect resources of an FPGA can be cate-gorized as inter-CLB and intra-CLB resources [20]. Thefirst category i.e.inter-CLB interconnect consists of wiresegments (or line segments) and programmable switchmatrices. On the other hand, the intra-CLB interconnectsoffers connectivity inside a CLB. Inter-CLB interconnectsresources testing is discussed in this paper.

2.2 Fault Models

Two significant faults are found in the FPGA interconnect,opens and shorts [20]. PIPs and line segments can beaffected by open and short faults. PIP short (stuck-on) andPIP open (stuck-off) faults are considered in interconnecttesting as they are equivalent to stuck-at faults in theconfiguration memory bits [4]. Open fault in PIPs causes thePIP to remain open which in turn will disconnect the linesegments that were previously connected by this PIP. It maybe caused by the SRAM cell stuck-O fault or the controlwire open fault. Similarly, a PIP will remain closed whena short fault occurs [21]. It may be due to the SRAM cellstuck-1 fault or the control wire short with Vcc [23]. Forline segments, open and bridge faults are considered.

2.3 RelatedWork

Numerous works have addressed application-indepen-denttesting of FPGA interconnect in the literature and varioustechniques have been proposed to decrease the numberof interconnect configurations. Different strategies havebeen taken in the previous works to test the globalinterconnect resources. Most of these works have utilizedbuilt-in self-test (BIST) strategy to reduce the input-output pin requirements for testing. Generally, in theglobal interconnect testing, the interconnect resources are

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W1

W3

W4

N1 N2 N3 N4

E1

E2

E3

W2

E4

S1 S2 S3 S4

PIPLine Segment Switch Matrix

I/O MuxCLB

IOB

Fig. 1 Virtex FPGA architecture with details of switch box connectivity [20]

configured as global buses and through input-output pins,test vectors are applied. In built-in self-test (BIST) strategythe test vectors are applied internally [4, 5, 8, 10, 15, 18,20, 21]. Local interconnect testing, which involves localinterconnection inside the CLBs, is discussed in [16].

Various type of techniques is found in the recent FPGAtesting process. The traditional manufacture-oriented FPGA

testing involves commercial test equipment and testing isperformed in the production environment [14]. The FPGA isfirst configured and then test vectors are applied externallyvia input pins. After that, the test responses are collectedvia output pins, which are compared with the expectedoutput. BIST approaches are quite popular in applicationindependent FPGA testing to solve the shortage of I/O pin

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problems [4, 5, 8, 10, 15, 18, 20, 21]. BIST techniquerequires test pattern generator (TPG) and output responseanalyzer (ORA) to implement the additional BIST logic andcircuitry for test generation. TPG generates the requiredtest pattern for FPGA and ORA is responsible for checkingthe output response with the desired response. In thisapproach FPGA internal memory is needed to store the testvectors and responses. Also, it is assumed that the TPG andORA circuits are fault-free. In [9] the global interconnectresources of Virtex-4 series FPGA is tested using the BISTtechnique.

In [14], a bit stream read back based method is proposedfor functional testing of FPGA interconnect. The authorsin [13], proposed a routability-aware algorithm for testgeneration of SRAM based FPGA. In [19], interconnecttest configurations are generated on the basis of thePIPs directions. In this approach, four directions of PIPswere proposed, horizontal, vertical, left-diagonal and rightdiagonal. This type of technique is applicable only forsimple interconnect structure such as Xilinx 4000, and fornewer FPGA such as Virtex-4, Virtex-5, Virtex-6 etc, thisapproach is inapplicable since newer versions of FPGA donot follow the regular switch matrix structure like XC4000[22].

To generate test vectors, all the BIST approachesdiscussed in the literature implement counter-based TPGs.Generally, all the counter-based TPGs are made of eithersingle or dual 2 or 4-bit counters. As activation of bridgingfaults between a pair of signals require an assignment ofopposite logic values, TPGs use the current and next stateof the counter to generate these type of test patterns.

In [4], a cross-coupled parity based BIST technique ispresented. The TPG implementations require to include a 2-bit up-counter initialized to all 0s and a 2-bit down-counterinitialized to all 1s. By cross-coupling, the parity from dualcounters, any fault affecting one of the counters will bedetected.

In [20], the authors proposed two mapping algorithmsfor path configuration generation. To minimize the con-figurations further an interleaving strategy is presented.To generate test vectors they use the traditional countingsequence algorithm. Anm-bit counter generates the test vec-tors (counting sequence) to test open and short faults in theinterconnect.

3 Path Configuration Generation

An ideal testing scheme must have both high fault coverageand a minimum number of configurations. The total testtime is dominated by the number of test configurations(milliseconds to seconds for loading each configurationdepending on the size of the FPGA) [20]. Therefore, all

possible faults must be covered in a minimum number oftest configurations.

The proposed test configuration generation approach willuse the following terms throughout this manuscript.

• Path: A path consists of a collection of PIPs andline segments. A path is generated by connecting linesegments using intervening PIPs. Consecutive PIPsare joined by applying path generation constraints. Apath starts at an input terminal and by connecting linesegments and corresponding PIPs, ends at an outputterminal.

• Path configuration: A path configuration consists of aset of paths from the input to the output pins obtainedby programming the switches. All paths in a pathconfiguration can be independently activated as theyhave no PIPs or line segments in common.

• Test vector: A test vector is a set of values assigned tothe input terminals for testing different type of faults.

• Test configuration: A test configuration consists ofa path configuration and the test vector applied onthat path configuration after the PIPs have beenprogrammed. The output is observed on the outputterminals at the end of the paths.

In general, FPGA interconnect testing is performed byfinding path configurations. The programmable resourcesof a FPGA are configured by loading a configurationbitstream. To activate a particular resource in the design, thecorresponding bit value needs to be set. Since applicationindependent FPGA does not have prior design information,so all resources must be tested to ensure the reliability ofthe device. In order to test interconnect resources, in eachconfiguration, several parallel paths are formed, which candrive signals from the input terminal to the output terminalsimultaneously. A path is formed by connecting linesegments and corresponding PIPs. Only independent paths(having no overlapped PIPs) are tested in a configuration,as bridging fault activation requires that opposite valuesshould be applied to the adjacent wires, which can generatea conflict if overlapping PIPs exist. If the resources of a pathare fault free, then any input test vector applied to the pathwill be the same as the output response. On the other hand,a mismatch between the input and the output will indicate afault.

In most of the test configuration generation methodsfound in the literature, heuristics are used to findindependent paths (connecting non-overlapped PIPs) inan iterative manner where every iteration removes thepreviously used PIPs. But while finding a new path, somePIPs might need to be reused, since more than one PIPscan drive the same line segments, when full switch matrixconnectivity is considered. So this type of approach may not

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get full fault coverage. In the proposed approach, instead ofremoving used PIPs, which may reduce the fault coverage,all PIPs are kept in the input file and appropriate constraintshave been designed to ensure that all PIP’s are used in oneor more path configuration.

The proposed strategy finds out a path by connecting thePIPs and line segments. Based on the different type of linesegments entering into the switch matrix, various type ofPIPs are found.

In this approach, paths are formed by connecting thehorizontal line segments entering into the switch matrixfrom one end and the possible PIPs (horizontal and/orvertical), which may have possible subsequent connectivityinside the switch matrix. A configuration consists of oneor more independent paths (having non-overlapped PIPs),which can be tested simultaneously. The SMT solver takesthe connectivity among line segments and PIPs as input andgenerates path and configuration assignment for every PIP.

3.1 SAT Based Generation of Path Configurations

The following constraints are used to generate path con-figurations for application independent FPGA interconnecttesting. SAT solvers are used to solve the optimization prob-lem by providing a satisfying assignment to all variablesused in the problem. A brief description of all the constraintsused are given below:

1) Coverage constraint: Although the main objective is togenerate the minimum number of test configurationsbut fault coverage is also equally important. In orderto get full circuit coverage, all PIPs should be includedin the paths. To activate fault in all PIPs, every PIPshould be a part of a path in some configuration. To

connect an input line segment of a switch matrix to aspecific output line segment, many options (PIPs) arethere. Since a configuration will contain only specificPIPs (among many possible PIPs), between two linesegments, so to activate the rest of the PIPs, separatepaths need to be formed. Therefore every PIP will getassigned to a path val as well as a path conf ig val,which must be assigned positive integer values. Foreach PIP:

path val × path conf ig val �= 0

to ensure that all PIPs in the circuit are covered by somepath in some configuration.

2) Path generation constraint: Line segments can enterinto the switch matrix horizontally as well as vertically.A path is generated by assigning a path val to ahorizontal line segment entering into the switch matrixand PIP which connect the line segment with other PIPsuntil the output end of the switch matrix is reached.Every path will start from one input end of the switchmatrix and will connect subsequent PIPs to reach to theoutput end of the switch matrix. As this approach aimsto find the path as well as configuration at the sametime, so when one or more PIPs are used to connect twoline segments, same (path val × path conf ig val)will be assigned to these PIPs.

If pipi and pipj are consecutively associated to connectspecific line segments, then

path vali × path conf ig vali = path valj

×path conf ig valj

In Fig. 2, two simple paths are illustrated, where solidlines indicate used PIPs and dashed lines indicate unused

Fig. 2 Path generation byconnecting consecutivelyassociated PIPs

AB

CE F

G

H

I JK

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a

b

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A

BC

D

A

BC

D

a

b

Fig. 3 Configuration generation covering all possible PIPs

PIPs. In Fig. 2a, PIP BC, CD, DE will be assigned same(path val × path conf ig val).

3) PIP conflict avoidance constraint: Every configurationshould contain paths having non-overlapped PIPs only.If two paths contain the same PIP, then the pathscontaining common PIP should be assigned to twodifferent configurations. In other words, these paths (orPIPs) will be activated in two different configurations,so that they can carry different test signals at the timeof test vector application.

If pip1 is used in two paths (e.g. pathi and pathj ) then,

path conf ig vali �= path conf ig valj

where, path conf ig vali and pathconf ig valj representsthe path conf ig val of pip1 for pathi and pathj

respectively.In Fig. 3, two paths are shown, where solid lines and

dashed lines are used to denote the used and unusedPIPs respectively. PIP AB should be assigned to differentconfiguration values to avoid conflict.

4) Objective function:

minimize∑

∀PIP s

∑∀path conf ig val

path conf ig val

The objective function is designed to obtain a minimumnumber of path configurations. All the above-mentionedconditions must be satisfied in order to generate pathconfigurations for the entire interconnect. The optimiza-tion objective ensures that minimum nember of path con-figurations are needed to cover all line segments andPIPs in the circuit. The method is applicable for a dif-ferent type of FPGA having a different type of linesegments which shows the flexibility of the proposedapproach.

Example In Fig. 4, an example of an interconnect consistingof three switch matrices SM1, SM2 and SM3 is shown.Path configurations have been generated for the above-mentioned figure using the proposed approach as shown inFig. 5. As can be seen, PIP A1B1 is included in two paths,therefore A1B1 is active in two different configurations.

In the first configuration, PIP A1B1, B1D1, D1C1 inswitch matrix 1 are active. This configuration consists of 4paths. Path 1 consists of PIP A1B1, B1D1, D1C1, E1F1,F1H1, H1G1, I1J1, J1L1 and L1K1. Path 2 consists of PIPA2B2, B2D2, D2C2, E2F2, F2H2, H2G2, I2J2, J2L2 andL2K2. Path 3 includes of PIP A3B3, B3D3, D3C3, E3F3,F3H3, H3G3, I3J3, J3L3 and L3K3. Path 4 contains PIPA4B4, B4D4, D4C4, E4F4, F4H4, H4G4, I4J4, J4L4 andL4K4.

The second configuration also contains 4 paths. Path 1consists of PIP A1B1, B1C4, E4F4, F4G1, I1J1 and J1K4.Path 2 contains PIP A2B2, B2C3, E3F3, F3G2, I2J2 andJ2K3. Path 3 consists of PIP A3B3, B3C2, E2F2, F2G3,I3J3 and J3K2. Path 4 consists of PIP A4B4, B4C1, E1F1,F1G4, I4J4 and J4K1.

In the third configuration, 4 paths have been assigned.Path 1 consists of PIP A1C1, E1G1, and I1K1. Path 2contains PIP A2C2, E2G2, and I2K2. Path 3 consists of PIPA3C3, E3G3, and I3K3. Path 4 consists of PIP A4C4, E4G4,and I4K4. As can be seen, 3 configurations are enough toexercise all available PIPs.

Fig. 4 An example of FPGAinterconnect with all possibleconnection inside switch box

A1

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SM1 SM2 SM3

SM1 SM2 SM3

SM1 SM2 SM3

Fig. 5 Path configurations generated using proposed approach

Figure 6 shows the set of constraints that are givenas input to the backend SMT solver Z3 to generateconfigurations for the example shown in Fig. 4.

3.2 Experimental Results

We have generated path configurations for several FPGAarchitectures. Details of wire segment resources associatedwith each switch box in different FPGA architectures aregiven in Table 1.

Z3 SMT solver [3] is used for solving the SAT problemgenerated for each circuit. All possible PIPs and line seg-ments are taken as input to the test generation problem. Z3provides the solution by using the constraints stated above.

Tables 2 and 3 show comparison of the path configurationnumber of the SAT-based method [1] with [11] for Virtex,

Virtex II, Virtex 4, Virtex 6, Virtex 7 and [12] for XC4010and Virtex-5.

Our approach is able to reduce the number of testconfigurations for XCV300 as well as Virtex-II, Virtex 4,Virtex 6 and Virtex 7. All the line segments and associatedPIPs have been included in the test configuration generationprocess.

4 Test Generation

The existing application-independent testing strategies usetwo different phases to generate path configurations and testvectors [20]. The traditional counting sequence techniquehas been used mostly to generate test vectors. This approachstates that to detect open, stuck-at and bridging fault among

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Fig. 6 The SAT model generated for the example shown in Fig. 4

k×mwires, log2(m×k+2) patterns (the counting sequence)must be applied [20].

The counting sequence method is quite popular inwiring network testing area. It checks for many shorts

Table 1 Wire segment resources associated with each switch box indifferent FPGA architectures

Wire types Virtex VirtexII Virtex 4 Virtex 5 Virtex 6 Virtex 7

Double – 40 40 42 66 70

Hex 12 120 120 – – –

Pent – – – 120 – –

Long – 24 24 18 8 12

Single 24 – – – 66 54

Quad – – – – 66 70

Table 2 Comparison of simulation results using the proposed SAT-based method [1] and Graph based method proposed in [11]

Circuit Number of path configurations required

ProposedSAT-basedmethod

Graph based method proposed in[11]

Virtex 10 11

Virtex-II 24 25

Virtex 4 26 28

Virtex 6 41 44

Virtex 7 56 58

simultaneously. A short between any terminal pair iscovered by at least one differing digit between the binarycodes for the corresponding terminals [6].

Interconnect testing targets faults such as shorts andopens in PIPS and line segments. PIP short (stuck-on) andPIP open (stuck-off) faults are considered in interconnecttesting as they are equivalent to stuck-at faults in theconfiguration memory bits [4].

It is important to test all possible PIPs to obtain a fault-free FPGA interconnect. It is possible to generate testvectors for the above-mentioned faults using SAT-basedconstraints. A brief description of the SAT-based constraintsused in this problem is given below:

1) Open fault activation constraint: In order to detect aparticular fault in a PIP or wire segment, the faultshould be activated first. The open fault (stuck-0 faultsin the configuration memory bits) of a PIP is detectedif the PIP is turned on (fault activation), and it is usedas a part of a path in which appropriate test signals canbe applied and output can be observed. Similarly, thestuck-at fault of a wire segment is detected if that wiresegment is covered by at least one path.For each PIP i,

input vali ×test conf ig valm �= input vali

×test conf ig valn

Table 3 Comparison of simulation results using the proposed SAT-based method [1] and bitstream readback-based method proposed in[12]

Circuit Number of path configurations required

ProposedSAT-basedmethod

Bitstream readback-based method proposedin [12]

XC4010 5 6

Virtex 5 58 56

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i.e. PIP i is used in two test configurations m and n inwhich it is assigned opposite logical values.

2) Short fault activation constraint: A short fault is causedby a stuck-closed fault of two PIPs (i,j). The fault isdetected if 1) the PIP is turned off (i.e., the PIP is notused as a part of a path); 2) there are two paths, p1 andp2, such that p1 passes through i and p2 passes throughj; and 3) the short fault between p1 and p2 is detected[16].If pipi and pipj are used in two different paths, then

in any configuration, if pipi and pipj are stuck closedthen bridging fault between the wire segments passingthrough them will be activated.For two PIPs, i and j ,

path vali �= path valj ∧ test conf ig vali

= test conf ig valj ∧ input vali �= input valj

where path vali represents the path andtest conf ig vali represents the configuration inwhich the PIP is used. Opposite logic values on thePIPs activate any short fault between them.

5 Integrated Framework for TestConfiguration Generation

In this section, we present a novel integrated frameworkfor the generation of test configurations and test vectors.Unlike traditional application independent testing of FPGAswhich follows a 2-phase strategy where path configurationsare generated first and then test vectors are generatedusing a different technique, this integration will allowthe generation of both the path configurations and testvectors in a single phase. This reduces the number oftest configurations necessary to obtain full coverage of allinterconnect resources for the targeted fault models.

Generally testing approaches that use BIST, generatecounting sequences with the help of a TPG. One m-bit counter generates vectors for each of the k set ofconfigurations. Hence, these k number of m-bit countersgenerate log2(m × k + 2) counting-sequence patterns (aslong as 2m ≥ �(log2(m × k + 2)� [20]. For example, ifthere are a total of six paths which are assigned to two testconfigurations m = 3, k = 2. Three 6-bit patterns (000111,011001, and 101010) are required to generate a test for allpaths in those two configurations for detecting all faults.

However, it is possible to generate test vectors alongwith path configurations using SAT-based constraints. SAT-based constraints can be used to generate test configurationswhich include test vectors as well. A brief description of the

SAT-based constraints used in the proposed integratedframework is given below:

1) Coverage constraint: Every PIP will get assigned toa path val as well as a conf ig val, which must beassigned positive integer values. For each PIP:

path val × conf ig val �= 0

to ensure that all PIPs in the circuit are covered by somepath in some configuration.

2) Path generation constraint: If one or more PIPs areused to connect two line segments, same (path val ×conf ig val) will be assigned to these PIPs.

If pipi and pipj are consecutively associated toconnect specific line segments, then

path vali ×conf ig vali = path valj ×conf ig valj

3) PIP conflict avoidance constraint: If two paths containthe same PIP, then the paths containing common PIPshould be assigned to two different configurations. Ifpip1 is used in two paths (e.g. pathi and pathj ) then,

conf ig vali �= conf ig valj

where, conf ig vali and conf ig valj represents theconf ig val of pip1 for pathi and pathj respectively.

4) Open fault activation constraint: To activate this typeof fault, every PIP should be sensitized at least once inone of the configurations.For each PIP i,

input vali ×conf ig valm �= input vali ×conf ig valn

i.e. PIP i is used in two configurationsm and n in whichit is assigned opposite logical values.

5) Short fault activation constraint: Each PIP must bestuck-closed (as detailed in previous section) so thatbridging fault between the wire segments passingthrough them can be activated in a configuration.If pipi and pipj are used in two different paths, then

in any configuration, if pipi and pipj are stuck closedthen bridging fault between the wire segments passingthrough them will be activated.For two PIPs, i and j ,

path vali �= path valj ∧ conf ig vali

= conf ig valj ∧ input vali �= input valj

where path vali represents the path and conf ig valirepresents the configuration in which the PIP is used.Opposite logic values on the PIPs activate any shortfault between them.

6) Objective function:

minimize∑

∀PIP s

∑∀conf ig val

conf ig val

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Table 4 Comparison of Test Vectors using proposed integrated method and the counting sequence algorithm

Circuit Number of test vectors required Comparartive % reduction Computation time (sec)

Proposed integrated method Counting sequence method

XC4010 15 20 25 0.26

Virtex 40 50 20 0.38

Virtex-II 125 144 13.19 0.57

Virtex 4 125 156 19.87 0.57

Virtex 5 290 336 13.69 1.18

Virtex 6 205 246 16.66 1.03

Virtex 7 280 336 16.66 1.12

The objective function is designed to obtain aminimum number of test configurations. To generatetest configurations for the entire interconnect allthe above-mentioned constraints must be satisfied.The path val and conf ig val represents the circuitconfiguration and the input val represent the testvector that must be applied to that configuration.

6 Experimental Results

We have generated test configurations for XC4010, Virtex,Virtex-II, Virtex 4, Virtex 5, Virtex 6 and Virtex 7 FPGAsusing the proposed SAT-based integrated framework. Wehave used Z3 SMT solver [3] as the back-end solver.For comparison with the traditional 2-phase technique, wehave applied the counting sequence method to generatetest vectors using the path configurations obtained beforein Section 3.1. When the traditional counting sequence isapplied to paths that are in the same configuration, animprovement can be achieved if the test vector generationpart is integrated with path configuration generation. Also,no extra algorithm is required to generate test vectors.

Table 4 shows a comparison of the number of test configu-rations required to test each FPGA architecture using ourproposed integrated method and traditional counting sequencealgorithm. To test XC4010, the number of paths per configu-ration is 14, therefore using the counting sequence algo-rithm we require log2(14+ 2) = 4 test vectors per configu-ration. Therefore to test the FPGA we need total 20 (4×5 =20, where 5 is the number of path configurations obtained).Applying our integrated approach total test vector reducedto 15. Similarly, other results are obtained and shown inTable 4. A percentage of reduction in test vector numberwith respect to the counting sequence method is shown inthe table to illustrate the efficiency of the proposed SATbased model. It can be seen from the table that only a fewseconds are needed to generate test vectors for each circuit.

It can be seen that by integrating the path configurationgeneration and test generation into a single framework, asignificant reduction is obtained in the total number of testconfigurations, when compared to the two functions treatedas separate phases.

7 Conclusion

This article proposes a test configuration generation strategyfor different Xilinx Virtex FPGA families in an application-independent testing scenario. As FPGA test time is domi-nated by the number of test configurations, therefore it isimportant to generate a minimum number of test configura-tions without decreasing the fault coverage. The target faultlist consists of opens and shorts faults in the FPGA inter-connect. To obtain the minimum number of interconnect testconfigurations, the presented approach uses satisfiability.The traditional testing approaches test the paths generatedfrom the path configuration generation method and thenapplying test vectors on each configurations. An integratedapproach is presented in this article to generate the path con-figurations and test vectors in a single cycle. To compare theefficiency of the integrated approach, test vectors have beengenerated using both the proposed approach and countingsequence technique popular in literature. The comparison ofthese two approaches is shown in Table 4. The advantage ofthe proposed integrated approach is that using this approachtest vector and test configurations can be generated in a sin-gle phase and the total number of test configurations neededto cover all open and short faults in all the interconnectcomponents is significantly reduced when compared to thetraditional two phase technique.

Acknowledgements This work was supported by the Department ofElectronics and Information Technology, Ministry of Communicationand IT, Government of India under the Visvesvaraya PhD Schemeadministered by Digital India Corporation (formerly Media Lab Asia).

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Shukla Banik received her B.Tech. degree in Computer Science andEngineering from Saroj Mohan Institute of Technology, West Bengal,India, in 2008, and the M.Tech. degree in Information Technologyfrom Indian Institute of Technology, Kharagpur, India, in 2013. She iscurrently pursuing Ph.D.. In Computer Science and Engineering fromNational Institute of Technology, Durgapur, under the supervisionof Dr. Suchismita Roy and Dr. Bibhash Sen. Her research interestsinclude VLSI design and test, Smart Grid.

Suchismita Roy received her B.Tech., M.Tech. and Ph.D. degrees,all in Computer Science and Engineering, from National Institute ofTechnology, Rourkela, Indian Institute of Technology, Bombay andIndian Institute of Technology, Kharagpur, respectively. Currently sheis a Professor of the Department of Computer Science and Engineeringat National Institute of Technology, Durgapur, India where she hasbeen a member of the faculty since 1998. Her research interests includealgorithms for VLSI design and test, Hardware Security, Satisfiabilitychecking and Algorithm design.

Bibhash Sen received his B.Tech. degree in CSE from NERIST,Nirjuli, India in 2002. He has received M.E. and Ph.D. in CSEfrom the IIEST, Shibpur in 2007 and 2015 respectively. Currently,he is an associate professor of CSE department, NIT Durgapur. Hisresearch interests include Hard-ware Security, Security System forwireless sensing, Hardware Trojan, Quantum-dot Cellular Automata,Reversible logic and Fault tolerant architectures for emerging nano-devices.

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