1178 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-28, NO. 10, OCTOBER 1981

Depletion-type NMOS Si-gate transistors also were fabri- cated in few runs using the described process of threshold voltage shifting. The results obtained are in close agreement with the above reported for Al-gate devices.

IV. CONCLUSION We presented in this paper a simple process for adjustment

of the threshold voltage of depletion-type NMOS transistors. By this process we attained a high degree of control of the threshold voltage shift with electrical characteristics proper for high-speed digital circuits and for analog devices.

The drain characteristics obey the C, model as expected for devices with shallow channel junctions [9] .

REFERENCES [ l ] R. Crawford, MOSFET in Circuits Design. New York: McGraw-

Hill, 1967.

D. Senderowicz, D. A. Hodges, and P. R. Gray, “High performance NMOS operational amplifier,” IEEE J. Solid-state Circuits, vol. SC-13, pp. 760-766, Dec. 1978. J . P. de Souza and E. Charry, “A simplified self-aligned Al-gate MOS technology for high performance depletion logic circuits,” IEEE J. Solid-state Circuits, vol. SC-14, pp. 651-653, June 1979. N.G.E. Johansson, J. W. Mayer, and 0. J. Marsh, “Technique used in Hall effect analysis of ion implanted Si and Ge,” Solid-state Electron., vol. 13, pp. 317-335, 1970. W. R. Runyan, Silicon Semiconductor Technology. New York: McGraw-Hill, 1965, ch. 8. M. Kamoshida and 0. Kudoh, “Surface depletion width depen- dence of threshold voltage shift of ion implanted MOS transistors,” Appl. Phys. Lett.,vol. 24, no. 10, pp. 501-503, May 15,1974. R.S.C. Cobbold, Theory and Applications of Field-Effect Tran- sistors. New York: Wiley, 1970. D. Frohman-Bentchkowsky, “On the effect of mobility variation on MOS device characteristics,” Proc. IEEE, vol. 56, pp. 217-218, 1968. J.S.T. Wang and G. W. Taylor, “Modeling of ion-implanted silicon- gate depletion-mode IGFET,” IEEE Trans. Electron Devices, vol. ED-22, pp. 995-1001,1975.

An Experimental Study of the BO-MOS Dynamic RAM Cell

Abstract-A novel structure of a one-transistor dynamic MOS RAM cell is developed for higher integration. The buried-oxide MOS (BO- MOS) RAM cell consists of a planar MOSFET transfer gate and a storage capacitor of buri,ed N+ diffusion. This three-dimensional structure re- sults in a cell size of 6 F 2 with a minimum feature size F and the large capacitance ratio of storage to bit-line which is about 4 times that of a typical commercial 64-kbit RAM cell. The soft-error-immunity cell structure is also taken into account. Static device characteristics of the planar MOSFET transfer gate built on an epitaxial layer and the buried storage capacitance are investigated relating to doses of boron im- plantation to the channel and substrate. Dynamic WRITE/READ oper- ations are performed with an experimental 4 X 10 cell array imple- mented with F = 4-pm features. The technology offers the possibilities of a high density dynamic MOS R A M with a single poly-Si process.

A I. INTRODUCTION

COMBINATION OF a MOSFET transfer gate and an MOS capacitor is the most common form of the present

high-capacity MOS dynamic RAM cell. However, the MOS capacitor occupies a considerable portion of the cell. Further- more, this thin- and large-area oxide film is a major cause of yield degradation, such as gate-oxide shorts, leakage, or threshold-voltage shifts due to unexpected contamination [ 11 .

Manuscript received August 4, 1980; revised May 27, 1981. The author is with the Integrated Circuits Division, Fujitsu Limited,

Kawasaki, Japan 21 1.

This situation will become much more severe for a high pack- ing density memory because as further scalingdown continues, an extremely thin-oxide film may be needed. Under these circumstances, it is a logical step that three-dimensional struc- tures have been introduced for higher packing density. One direction is the buried junction storage concept such as the VMOS dynamic RAM cell [2] and the other is the stacked thin film capacitor cell [3] . The cell structure of either type has the charge storage located under or over the transfer gate, which results in a great saving of the silicon real estate.

In this paper we describe the fabrication processes, struc- tural features, and experimental results of the BO-MOS RAM cell, which has a buried junction storage located under a planar MOSFET transfer gate.

11, PROCESS TECHNOLOGY Fig. 1 illustrates the fabrication steps for a pair of the BO-

MOS RAM cell. The cross-sectional and top views of the cell are shown in Fig. 2. The fabrication sequences were described extensively in a previous paper [4.] .

One of the radical processing steps on the BO-MOS RAM cell is the buried-oxide process [5] , which is a simultaneous growth of poly- and single-silicon layer over the selectively oxidized wafer. The epitaxial layer of 0.6 - 1.0 pm in thick- ness has been grown from the decomposition of 1 percent

0018-9383/81/1000-1178$00.75 0 1981 IEEE

SAKURAI: BO-MOS DYNAMIC RAM CELL 1179

i P-

Fig. 1. Fabrication processing steps of the BO-MOS RAM cell.

t i i

P- I

I

Fig. 2. A cross-sectional view of a pair of the cells (a), a cell topology (b). A cell size 6 F 2 (= 3F x 2F)lbit including an isolation area is in- dicated by broken lines.

SM4 in hydrogen atmosphere with growth rate 0.6 - 1 .O pm/ min below temperature 1000°C in a bell-jar-type reactor. Errors in epi thickness are within 10 percent at 0.6 - 1.0 pm thick. A shallow epi (0.6 pm thick) generally provides better results compared to a thicker one (1.0 pm thick), because the latter requires the thicker field oxide of which thermal process leads to longer bird's beaks of the embedded field oxide and more out-diffusion of the buried layers. A 1-pm epi does not have an advantage in either vertical breakdown or con- trollability of thickness over an 0 .6ym epi in our experiments.

Another important step is a self-aligned vertical connection between the shallow source diffusion and buried storage re- gion. Since the impurity diffusion rate in poly-Si is much higher than that in single-Si, a single diffusion process for the shallow source and drain formation allows the N+ impurity to down-diffuse quickly to the buried N+ diffusion through the narrow 'poly-Si region. A similar poly-Si technique was used previously for a bipolar power IC by Kobayashi [ 6 ] . Some key process parameters are summarized in Table I.

III. CELL STRUCTURE A. Structural Features

As shown in Fig. 2(a), the transfer gate is a conventional MOSFET, while the memory charge is stored at a p-n junction capacitor of buried N+ diffusion just as the VMOS RAM cell.

TABLE I PROCESS PARAMETERS

____-I

Substrate wafer P-type (100) 10 nan 4 in Buried Nt layer (Ast) X, = 0.24 p e, 98 n/O

Buried Pt layer (B') Xj = 3.3 p e , = 0.5 kWo

Buried oxide layer 50 nm thick

Epitaxial layer 0 .6 p thick non-dope

Source/drain (Ast) xj = 0 .24 p e, E 60 n/o

Poly-Si gate (As*) 0.4 p thick e , = 43 n/o

Gate oxide 40 nm thick ____I

Note xj : Jmction depth, e , : Sheet resist ivity

Another remarkable feature of the BO-MOS RAM cell is, as stated before, a self-registering vertical connection between the source and the buried N+ diffusion through the poly-Si column. This vertical cell structure enables the cell size to be 6F2 (=3F X 2F) which is the minimum size of a planar MOSFET including an isolation area as shown in Fig. 2(b).

The P+ diffusion layer surrounding the buried N+ diffusion plays several important roles as follows: I ) Moderate auto- doping of boron atoms during an epitaxial growth produces the lightly doped P-type silicon fdm, on which the n-channel MOSFET's are built. 2) The P+ diffusion prevents the punch- through breakdown between the buried storage and the bit- line N+ diffusion, and also between adjacent buried storages. 3) The junction capacitance per unit area of the buried storage increases with increasing the impurity concentration of the P+ layer. 4) It serves as the channel-stop diffusion under the field oxide. 5 ) It helps to reduce the soft error as discussed later.

The typical impurity profiles are illustrated in Fig. 6(a).

B. Soft-Error Immunity Possible causes of the soft-error are 1) the &-particles [7],

2) high-energy cosmic rays [8], and 3) stray electrons either injected at forward-biased p-n junctions due to an undershoot voltage on input circuits or generated by the secondary im- pact ionizations near the drain junctions [9] , particularly in the boostrap circuits.

In the BO-MOS RAM cell, bit-line diffusions have the lithographic minimum area F2 per bit, which are connected to each other by an aluminum bit-line. This minimizes the bit- line capacitance, which increases the capacitance ratio of a storage to a bit-line. The large Cratio is essential to the noise margin of the sense amplifier.

The buried N+ storage surrounded by P+ diffusion is immune from the soft error for two reasons. One reason is that the numbers of hole-electron pairs generated in the depletion layer by a-particles decreases because the P+ diffusion decreases the depletion layer width beneath the storage region. The deple- tion layer of the N+ storage is about 0.2 pm thick which is roughly one-tenth of that in the conventional 1-Tr RAM cell. The other reason is that the stray electrons in P- substrate will be rejected by a potential barrier of the P'P high-low junction between the buried P+ layer and the P- substrate. This is pos- sible because the potential barrier of the P'P high-low junc- tion is in the order of 0.2 eV, while the migrating electrons

1180 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-28, NO. 1.0, OCTOBER 1981

"0 .2 .4 .6 .8 1.0 1.2 vm (volts)

Fig. 3. Gain factor p versus threshold voltage Vth of the transfer gates. p's are measured at 5-V gate voltage with a zero-substrate bias.

have only thermal energy KT = 0.025 eV [IO], [ l l ] . In- tensive efforts have recently been concentrated on coating the a-particle absorbing material such as polyimide on the chip surface. It is indeed effective for the soft error due to the Q-

particles but useless for that due to high-energy cosmic rays or stray electrons injected by several reasons mentioned earlier, while the potential barrier of the P+P high-low junction can prevent all kinds of migrating electrons from going into the storage area.

IV. DEVICE CHARACTERISTICS A. Static Characteristics

1) Transfer Gate: The electrical characteristics of the MOSFET fabricated on the epitaxial film are not significantly different from those of the conventional MOSFET fabricated on the bulk silicon [ 5 ] .

The measured MOSFET's have two different nominal chan- nel lengths L = 3 pm and 4 pm with a constant nominal chan- nel width W = 4 pm. Channel implantations for threshold ad- justment of B+ 2.5 X 10" and 1.0 X 10" cm-' doses at 50-keV energy are carried out through a gate oxide of 40-nm thickness. The correlation plots between the gain factor p [12] and the threshold voltage Vth with parameters W/L and B+ implant doses are shown in Fig. 3. The p is measured as a ratio of the drain-current increment to the drain-voltage in- crement between the drain currents 25 pA and 100pA. Con- siderable spreading of the measured p's may arise mainly from variations of the poly-Si gate length from chip to chip. The magnitude of 6's are apparently smaller than those expected from wide channel devices. This is due to the channel width narrowing effect by bird's beaks of the embedded field oxide.

2) Buried Storage: The Capacitance, ratio of a charge stor- age to the bit-line is an important factor for an input voltage to the sense amplifier. The storage and bit-line capacitances per bit have been measured by using a test device particularly designed for this purpose. An equivalent circuit of the device is shown in the inset to Fig. 4, which consists,of a single bit- and word-line with 260 pairs of a transfer gate and a buried storage. The actual circuit. is laid out in a 13 X 20 cell array as partially shown in Fig. 5 . A single word-line signal V , can isolate all 260 buried storages from the bit-line. Furthermore, the substrate bias V,, can separate the junction capacitances from the residual fixed capacitances whose com- ponents are of bonding pad, probe, and wiring. The bit-line

'0 ' -2 ' -4 -6 -8 -10 I

V% (volts)

Fig. 4. Total bit-line capacitance Ctot versus substrate bias V,, with a parameter V,. Ctot consists of three components: buried storage C,, bit-line diffuslon CB, and residual fixed capacitance Co.

P O L Y - S I WORD-LINE

Fig. 5. Photomicrograph of a 260-bit device for measurements of ca- pacitances c, and leakage current 1~ of buried storage. An indicated cell size is 96 Km2 (= 8 W r n X 12 prn)/bit with the minimum features F = 4 um.

capacitance largely comes from the drain junction of transfer gates. The components of the gate capacitance overlapping the drain diffusion and of the AI bit-line over the field oxide are negligibly small. Thus we can measure each component of the total bit-line capacitance Ctot separately with com- binations of V, and V,, as follows:

Co t 1 30CB t 260C, at V , = 5 V, V,, = 0

at V , = 0, V,, = 0

at V,,, =0, V,, = - 8 V

where C, is the fixed capacitance per bit-line, and C, and C, are a storage and a bit-line capacitance per bit, respectively. The typical measured capacitance variations with respect to the substrate bias V,, are plotted with a parameter V , as shown in Fig. 4. The C, and C, can be practically controlled by the B+ implantation dose for the buried P-type layer under a constant annealing condition (12OO0C, 60 min in Nz). The B" implantation dose is limited by the avalanche breakdown voltage BV of the buried N+ diffusfon. The dependences of C,, CB, and BV upon the B+ implantation dose are plotted in Fig. 6(b). The calculated avalanche breakdown voltage for one-sided abrupt junction approximation with 1 X lo" cm-3 acceptor concentration is about 11 V, while the depletion layer width under the same reverse-bias condition is about 0.4 pm. Therefore, the punchthrough breakdown between adjacent buried storages cannot be a limitation for this type of the memory cell with even a feature size F = 1 pm. The capacitances of buried storage C, and bit-line diffusion CB are indicated in a cross-sectional view of the cell shown in Fig. 6(a). With these capacitance measurements, the C ratio can be

Ct,, = Co t 1 3 0 C ~

c .

SAKURAI: BO-MOS DYNAMIC RAM CELL 1 1 8 1

103: I

I

10'3 1014 loi5

(b) Fig. 6 . Impurity profiles to produce buried diffusion with an 0 . 6 - ~ m epi

laver. and cauacitances of buried storage C, and bit-line diffusion Ca

B+ dose (cm-2 )

1

indicated in a cross-sectional view of the cell (a), Dependences of C,, Fig. 7. Leakage current per bit of a typical buried storageZL versus re- C,, and avalanche breakdown voltage B V upon B+ implantation under verse bias VR. The inset shows a hystogram of 1, at VR = 5 V on a a constant annealing condition (1200 "C, 60 min in N2) (b). typical wafer.

I " Y

( c) Fig. 8. Voltage wave forms of high WR1T~high READ operation with a

low disturbing pulse prior to the READ operation (a), similarly low WRITE'-~OW READ operation with a high disturbing pulse (b), and a schematic of the memory and test circuits for dynamic WRITE~READ operations (c).

4

estimated easily, e.g., for a 64-kbit RAM, provided that a single by a factor than that of the conventional cell. Because of the bit-line has 32 pairs of storage cells, C,/32CB = 3 - f . These limited experiments, the cause for the leakage has not been values are 2 - 4 times those of the conventional 64-kbit identified. Since the leakage of this kind generally depends RAM [13]. upon complicated factors such as junction geometry, impurity

Leakage characteristics of the storage are studied by again deposition condition, annealing atmosphere, or peripheral con- using the 260-bit 'test device, by which one can easily separate ditions, further extensive investigations are needed. the leakage component of the storage from that of the bit-line diffusion. A typical leakage characteristic at room tempera- B. Dynamic Chmcte~st ics ture is shown in Fig. 7. The inset to Fig. 7 shows a hystogram Dynamic WRITE/READ operations are performed by using a of the leakage currents for a typical wafer at 5-V reverse bias. 4 bit X 10 word cell array implemented by a feature size of 4 In the inset to Fig. 7, it can be seen that the average leak- pm. A schematic of the memory and test circuits is shown in current is 1.5 pA/bit at reverse bias V, = 5 V, which is higher Fig. 8(c), where only one bit-line is shown.

1182 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-28, NO. 10, OCTOBER 1981

Fig. 8(a) shows high WRITE-high READ with a low disturbing pulse prior to the read operation, and similarly, Fig. 8(b) shows low WRITE-low READ with a high disturbing pulse. The storage time of the best chip is observed to be around 300 ms by memory scope. The storage time ts may be estimated from

ts = c s * (V, - VL) IL

where V,, V L , and IL are stored voltages of high and low states, and leakage current per bit at stored voltage V,, respec- tively. As an example, for C, = 0.07 pf/bit, V, = 4 V, VL = 1 V, and IL = 0.5 pA/bit, we have ts = 0.4 s. This is the same order as measured.

V. SUMMARY A 1-Tr dynamic RAM cell having a unique structure has

been described. The BO-MOS RAM cell combines a planar MOSFET transfer gate and a buried-junction capacitor.

Because of the three-dimensional cell structure, a 6F2 cell size is realized with the lithographic minimum feature size F , which is 4 - of those of the conventional I-Tr 64-kbit dy- namic RAM cell [ 131 , [ 141 . A large capacitance ratio of a storage to a bit-line CJC, = 12/bit is obtained. Because the bit-line capacitance is minimized by using an A1 line and an N+ bit-line diffusion of the lithographic minimum area F2 per bit, and also because the buried storage is surrounded by the P”P high-low junction, whose built-in potential rejects the stray electrons, the BO-MOS RAM cell should be more im- mune from the soft error caused by not only the a-particles but also high-energy cosmic rays or stray electrons either in- jected by undershoot voltages at the neighboring p-n junctions or generated by the secondary impact ionization near the drain junctions in the boostrap circuits.

The new RAM cell is fabricated by using an 0.6-pm epi and a single poly-Si technology with six basic mask operations. Dynamic WRITE/READ operations are successfully demon- strated by using an experimental 4 X 10 cell array imple- mented with the minimum feature size F = 4 pm.

A relatively large leakage current 1.5 pA/bit at 5-V reverse bias on the buried storage is observed at room temperature. The measured storage time is around 300 ms at room temper- ature. Leakage characteristics will be improved by more care- ful control of process conditions.

The resistance of a poly-Si word-line will become a limiting factor to speed requirements as the line width continues to be scaled down. but this is not of real concern because the .oolv-Si I --.I -

can be replaced by refractory metal silicide without sacrificing any layout density [ 151 , [ 161 .

For overall judgement, the BO-MOS RAM cell is seen to have significant advantages particularly in packing density and C ratio, as well as the soft-error immunity, over the conventional 1-Tr dynamic RAM cell.

ACKNOWLEDGMENT The author wishes to thank H. Kashimada and M. Takagi for

their encouragement and guidance, and also the personnel in the IC Division of Fujitsu Limited for many helpful discussions and for the fabrication of the devices.

REFERENCES S. J . Rosenberg, D. L. Crook, and B. L. Euzent, “H-MOS re- liability,” IEEE Trans. Electron Devices, vol. ED-26, pp. 48-51, Jan. 1979. J. J. Barnes, S. N. Shodle, and F. B. Jenne, “The buried-source V-MOS dynamic RAM device,” IEEE IEDM Tech. Dig., pp. 272- 275, 1918. M. Koyanagi, H. Sunami, and N. Hashimoto, “Novel high den- sity, stacked capacitor MOS RAM,” in Proc. 10th Con& Solid State Devices, Tokyo, pp. 35-42, 1978. J . Sakurai, “The BO-MOS RAM cell,” IEEE IEDM Tech. Dig., pp. 197-200,1978. - , “A new buried oxide isolation for high-speed high-density MOS integrated circuits,”IEEE J. Solid-State Circuits, vol. SC-13,

I. Kobayashi, “A new technology for high-power IC,” IEEE Trans. Electron Devices, vol. ED-18, pp. 45-50, Jan. 1971. T. C. May and M. H. Woods, in Proc. Int. Reliability Physics Symp. 1978, IEEE Catalog 780H1294-8PHY, pp. 33-40. “DO cosmic rays spell death for VLSI?” Electronics, pp. 44-46, Nov. 22, 1979. T. Furuyama, K. Ohuchi, and S. Kohyama, “An electrical mecha- nism for holding time degradation in dynamic MOS RAM’s,” IEEE Trans. Electron Devices, vol. ED-26, pp. 1684-1690, Nov. 1979. 0. Minato, T. Masuhara, T. Sasaki, H. Nakamura, Y. Sakai, T. Yasui, and K. Uchibari, “2K X 8 bit hi-CMOS static RAM’s,” IEEE Trans. Electron Devices, vol. ED-27, pp. 1591-1595, Aug. 1980. J. Nishizawa, T. Ohmi, and H. L. Chen, “A limitation of channel length in dynamic memories,” ibid, pp. 1640-1649. R. H. Crawford,MOSFET in CircuitDesign. New York: McGraw- Hill, 1967. G.R.M. Rao and J. Hukin, “64 K dynamic RAM needs only one 5-volt supply to outstrip 16-K parts,” Electronics, pp. 109-1 16, Sept. 28,1978. E. Arai and N. Ieda, “A 64-kbit dynamic MOS RAM,” IEEE J. Solid-State Circuits, vol. SC-13, pp. 333-338, June 1978. T. Mochizuki, K. Shibata, T. Inoue, and K. Ohuchi, “A new MOS process using MoSiz as a gate material,” Japan. J. Appl. Phys.,

B. Crowder and S. Zirinsky, “1 pm MOSFET VLSI Technology; Part VII-Metal silicide interconnection technology-A future perspective,” IEEE Trans. Electron Devices, vol. ED-26, pp. 369-371, Apr. 1979.

pp. 468-471, Aug. 1978.

VO~. 17 , suppl. 17-1, pp. 37-42, Oct. 1977.