S C H E M A T I C G E N E R A T O R

An Automatic Nedist-to-Sc hematic

Generator

WITH THE INCREASE IN DESIGN complexity, the problem of enter- ing designs into CAD systems at the behavioral level has received much attention in recent years. Silicon compilers translate a high-level b e havioral description into a low-level physical description. To make the design process interactive, a tool that translates a structural-level d e scription into a schematic diagram is necessary. A schematic gives d e signers better insight into their d e signs. With this insight, designers can prune the heuristic parameters of the silicon compiler and produce designs fulfilling their requirements. A schematic also facilitates design documentation. For these reasons, tool developers are highly interest- ed in automatic schematic genera- tion systems.

B. NAVEEN

K. S. RAGHUNATHAN

Indian Telephone Industries Ltd.

The N2S schematic generator uses a novel variable-ordering

technique in the initial placement phase and simple heuristics in the final placement phase. Its chand- routing techniques result in signal routing with minimal crossovers.

The authors demonstrate the efficiency of N2S by applying

it to a set of benchmark sequential circuits.

Many design automation companies 1 system,’ for example, forms an adjacen- are offering automatic schematic gener- ators as part of their synthesis tools. However, only a few systems have been reported in the literature. The Autodraft

An earlier version o f this article was presented at the Fifth International Conference on VU1 De- sign, Bangalore, India, January 1992.

cy matrix and uses this information for both initial and constructive place- ments. The IITD system2 assigns posi- tions to modules on the basis of weight factors that reduce crossovers and bends in the final schematic. In the ASG ~ystem,~ leveling and bubbling place- ment techniques improve system speed.

The placement techniques of these systems slow down their speed for processing large circuits. In an interactive design system, fast response is important for maximum productivity. This prompted us to look at techniques to improve the speed of a schematic generator.

As a result, we developed N2S, an automatic schematic generator that operates in the Vinyas environ- ment. Vinyas is a fully integrated VLSI CAD system developed by In- dian Telephone Industries ([TI): Vinyas provides a set of powerful tools to support both semicustom and fullcustom design methods. The system’s key attributes are an integrated design environment, a consistent user interface, support for a hierarchical design method, and simplicity.

Figure 1 diagrams the overall Vinyas design system including N2S. N2S consists of three components: input parser, place and-router, and output generator. The first component reads the netlist and the graphical information about the modules. The second component places all the d e sign modules and routes the nets in a read- able way. The third component writes the

36 0740-747519310300-0036$03 00 0 1993 IEEE IEEE DESIGN & TEST OF COMPUTERS

generated schematic information into the Vinyas database. N2S is generic; to use it under non-Vinyas environments, one need only modify the input parser and output generator.

The problem Given a structural circuit description,

(at various levels such as functional and logic), a designer wishes to generate an aesthetically good schematic for easy and fast comprehension of the design. Classifying a schematic as aesthetically good or bad is difficult as it is a subjec- tive decision. However, from our study of various manually drawn schematics, we derived the following set of desirable characteristics:

1. Most of the signal flow is from left to right.

2. Crossovers are minimized for better readability.

3. Converging fan-in and f a n a t mod- ules are grouped for symmetry.

4. The routing avoids excessive bends.

5. Net routing takes place within the span of the net’s pins, for easy net traceability.

Figure 2 shows the layout model of a schematic. The layout is grid based, with

(r,, r2, .... r,,,). We call the ordering of modules on the basis of their logical connectivity leoeling. A module’s level is the order so determined. The level of pri- mary inputs is minimum (=l), and that of primaly outputs is the maximum of all the modules’ levels. All modules with the same level are assigned to the same column. A module’s row determines its relative position within the column. The regions between columns are channels used for net routing.

The general problem of generating a schematic is to achieve placement and routing of modules in the final schemat- ic that reflect the characteristics listed above to the extent possible. Given a set

several columns (c1, cz, .... c,) and rows

I synthesis Logic t

...............................

,.. ..............................

Figure 1 . Vinyas design system.

of modules, we define the placement problem as the task of assigning a col- umn i and row j to each module such that no module overlaps another.

Placement consists of two phases: ini- tial and final. The initial phase assigns columns and rows to modules. Items 1 and 2 in the list of desirable characteris- tics determine the assignment of col- umns and rows, respectively. The final phase further tunes the modules’ row positions by taking into account charac- teristic 3, together with geometric infor- mation about the modules. For routing feedback and feed-forward signals, we add feed (pseudo) modules to a col- umn, between modules, keeping in view characteristics 4 and 5. After place ment, we route channels one at a time, using channel-routing techniques.

In previously reported work,’” the column and row assignment is treated as two separate steps. In contrast, our approach handles it as a single step. For our initial placement algorithm, we modified the variable-ordering tech- nique used in constructing binary deci- sion diagrams, as described by Fujita, Fujisawa, and K a ~ a t o . ~ The relative placement thus determined usually r e sults in a minimum of net crossovers in

0

Channels A

0 0 0

C1 c2 ... c, ... C”

figure 2. Schematic-layout model.

the final schematic, without any further processing. We modified Yoshimura and Kuh’s channel-routing algorithm6 to route the nets with minimal crossovers, even at the expense of routing area.

initial placement We treat initial placement as a node

ordering problem in a graph network circuit, with each node representing a unique module. The graph is a directed one in which the arc direction repre sents the signal flow direction. We carry out the node ordering by means of a depth-first traversal of the graph. We use the following terminology in the descrip tion of the nodeordering algorithm:

MARCH 1993 37

S C H E M A T I C G E N E R A T O R

M

Primary inputs: TO, T I , T2 Primary outputs: T3, T4 Modules: NI , N2, N3, N4

Nets 1 NI-N4 4 TO-NI 7 N4-T3 2 N2-N4 5 TI-N2 3 N3-N4-T4 6 T2-N3

(bl

C1 CP fcl

Figure 3. Example circuit: manually drawn schematic /a); structural representation (b); schematic after initial placement (c); after module grouping (dj; after feed assignment (el.

rn RN list. A node is treated as a root node if it represents a primary out- put in the circuit. The set of root nodes forms an R N list.

rn TN list. The set of nodes traversed (visited) during the graph traversal forms a TN list.

rn Fin-in node. A node N1 is a fan-in node of node N2 if at least one sig nal flows from N 1 to N2.

rn Fan-out node. A node N2 is a f a n a t node of N 1 if at least one signal flows from N 1 to N2.

rn NTN list. The set of nontraversed (not visited during graph traversal) fan-in nodes of a node N forms the NTN list of N. The nodes in the list are sorted in the order of the pins of the module represented by N. For

leaf nodes (primary inputs in the cir- cuit), the NTN list will be empty.

The node-ordering algorithm pro- ceeds as follows: Starting from the R N list, it traverses the graph recursively in a depth-first manner. The recursion folds back at a node when the node’s NTN list is empty. During node traversal, any oc- currence of a traversed fan-in node im- plies the possibility of a feedback loop in the circuit. However, since the algo- rithm looks only in the NTN list for fur- ther traversal, i t can resolve feedback

To maintain the left-to-right signal flow (characteristic l), we traverse the graph twice. The first traversal deter- mines each node’s depth (distance from

loops.

root node). A node’s depth is the recur- sion level at the time of visiting the node. The second traversal reassigns the node depths according to the following rule: All fan-out nodes of a node N must be to the right of it. The depth reassignment satisfies the left-to-right signal flow r e quirement most of the time.

After the second traversal, we assign the graph’s maximum depth as the pri- mary output level. Each module’s level is less than the primary output level by the depth of the node to which the mod- ule belongs.

Finally, we assign level 1 to all the pri- mary inputs. A module’s column direct- ly maps to its level. Also, the order in which rows are assigned to modules in a column is the same as the order in which the nodes representing the mod- ules are traversed. The interesting aspect of the graph traversal technique is that we can determine both the column and row of modules during graph traversal itself.

Final placement The following conditions determine

the final position of a module within a 2olumn:

rn initial position of the module rn its graphical characteristics (size,

rn placement of its fan-in and f a n a t pin positions)

modules

In accordance with criterion 3 for a good schematic, the final placement groups fan-in and f a n a t modules for better symmetry.

To route the feedback and feed- forward nets, we provide additional space by adding feed modules between modules in a column. The following rules determine a feed module’s location:

rn It should lie within the vertical span of the net under consideration.

rn The position must result in a route with a minimum number of bends.

i 38 IEEE DESIGN I TEST OF COMPUTtRS

____~

The feed assignment may affect the final position of the modules. Equivalent to global routing, this step assigns the net segments to various channels.

Figure 3a shows a manually drawn schematic, and Figure 3b shows its struc- tural representation (netlist). Figures 3c through 3e show the execution stages of our placement algorithms for the design in Figure 3b.

Detailed routing Because the region between succes-

sive columns forms a channel, a channel-at-a-time routing scheme is a p propriate. We use Yoshimura and Kuh’s channel router with some modifica- tions, taking into account characteristic 2 of good schematics. The algorithm routes channels one at a time. It involves three steps:

1. forming a verticalconstraint graph (VCG)6 based on the net disposi- tion within the channel

2. track assignment to the nets based on their order (determined by the VCG)

3. resolving vertical constraints if any

Our first modification of the algorithm is the introduction, while forming the VCG, of additional constraints to mini- mize crossovers. Figure 4a shows a pos- sible routing without the additional constraints; Figure 4b shows the same routing with the additional constraints. The router assigns tracks to nets in the order they appear in the VCG. For better aesthetics, it uses one track per net as- signment. However, it assigns nonover- lapping nets with the same order to the same track.

Our second modification is cycle reso Mon. The original channel router algo rithm assumes the VCG to be acyclic. However, we tried to resolve the cycles in the vertical constraints, using the simple technique shown in Figure 4c. To remove the cycle, the router makes a jog at pin p2 of net B such that net B does not conflict

1 2 2 1 3 4 5 6 1 2 2 1 3 4 5 6

3 4 5 6 3 4 5 6 A,, BP2

M (bl (4

Figure 4. Channel routing: without additional constraints (a); with additional constraints (6); cycle resolution (c).

with other net paths. The technique does not adversely affect the schematic’s aes thetics because the jog is localized.

Results The N2S schematic generator is imple

mented in C in a Unix environment. Fig- ure 5 shows two schematics generated by N2S. Analysis of the schematics shows that the signal flow is from left to right, net crossovets are minimal, especially in fan- out-free regions, and the grouping of modules is symmetric. Moreover, all the nets are routed within their vertical spans, ensuring easy net traceability.

For two schematics reported by Jehng, Chen, and Pamg,3 we found that N2S is faster than ASG. We detail the comparison in our earlier report7 To ex- amine the efficiency of N2S, we applied it to a set of benchmark sequential cir- cuits.8 Figures 6 and 7 (next page) sum- marize results obtained on a Sparcstation I. For all the circuits, the placement phase took less time than routing. The overall execution time de- pends on the number of levels in the cir- cuit, in addition to the number of modules and the number of nets.

A NOVEL PLACEMENT TECHNIQUE im- proves the overall execution time of the N2S schematic generator. And the qual- ity of the schematics generated is usual- ly comparable to manually drawn schematics. We have observed that the primary-output ordering has an impact

L 4

Figure 5. N2Sxhematics: 8-to- 1 multiplexer (a); eight-line to hree-line priorifyencoder (bl.

on the quality of the final schematic. In future work toward producing aestheti- cally good schematics, we will consider more efficient heuristics for unbending, feed assignment, module grouping, and primary-output ordering. Also, by modi-

MARCH 1993 39

S C H E M A T I C G E N E R A T O R

Time (rns) x lo3 3.0

2.5

2.0

1.5

1 .o

0.5

0.0

0 500 Modules M

Time (ms) x lo3

3.0

2.5

2.0

1.5

1 .o

0.5

0.0

0 500 Nets

(bl

Figure 6. Placement results: number of modules versus execution time (a); number of nets versus execution time (b).

Time (rns) x lo3 200

180

160

140

120

100

80

60

40

20

0 0 200 400 600

fa) Modules 0 200 400 600

(bl Nets

Figure 7. Routing results: number of modules versus execution time (a); number of nets versus execution time (bj.

40

fying the placement algorithm so that it treats bus nets separately, we hope to further improve schematic quality.

Acknowledgments We thank ITI management for permitting

this work to be published. We also thank Kris Kozminski and Douglas Maltais, at MCNC, for providing the benchmark circuits. Thanksare also due to Camil E. Rego and Anantharaman Balasubramanyan for preparing the manu- script. Finally, we thank the anonymous r e viewers for their critical comments.

References 1. M.A. Majewski et al., “Autodraft: Aute

matic Synthesis of Circuit Schematics,” Roc. Int ‘1 ConL Computer-Aided Design, IEEE Computer Society Press, Los Alam- itos, Calif., 1986, pp. 435438.

2. A. Kumar et al., “Automatic Generation of Digital System Schematic Diagrams,” IEEEDesign & Test of Computers, Vol. 3, No. 1, Feb. 1986, pp. 5865.

3. Y.-S. Jehng, L.G. Chen, and T.-M. Pamg, “ASG: Automatic Schematic Generator,” Integration, The VLSI Journal, Vol. 1 1, Elsevier, 1991, pp. 11-27.

4. Vinyas Design System User’s Manual, Microelectronics and Computer Divi- sion, IT1 Ltd., Bangalore, India.

5. M. Fujita, H. Fujisawa, and N. Kawato, “Evaluation and Improvements of Bool- ean Comparison Method Based on Bi- nary Decision Diagrams, PLoc. Int’l ConL Computer-Aided Design, IEEE CS Press,

6. T. Yoshimura and E.S. Kuh, “Efficient Algorithms for Channel Routing,“ IEEE Trans. Computer-Aided Design, Vol. CADl, No. 1, Jan. 1982, pp. 2535.

7. B. Naveen, A. Savargaonkar, and K.S. Raghunathan, “N2S: An Automatic Netlist to Schematic Generator,” froc. Fifih Int’l ConL VLSl Design, IEEE CS Press, 1992, pp. 26S267.

8. F. Brglez, D. Bryan, and K. Kozminski, “Combinational Profiles of Sequential Benchmark Circuits,” PLoc. Int’l Symp. Circuits and Systems, IEEE, Piscataway, N.J., 1989, pp. 19291934.

1988, pp. 26.

IEEE DESIGN I TEST OF COMPUTERS

1

I

velopment in the Microelectronics and Computer Division of Indian Telephone In- dustries, Bangalore, India. His current inter- est is VLSl design tools. He received the BEng degree in electronics and communica- tion engineering from Andhra University, Waltair, India, and the MTech degree in in- tegrated circuits and systems engineering from the Indian Institute of Technology, Kharagpur. He is a member of the VLSl Soci- ety of India.

project leader for CAD-VLSI development in the Microelectronics and Computer Division of Indian Telephone Industries. In addition to VLSl CAD, his interests include simula- tion, logic and high-level synthesis, and ASIC design. He has extensive experience in the development of electronic switching sys- tems and in the application of VLSl to com- munication. He holds a BE in electronics and communication engineering from Ma- dras University and an MTech from the Indi- an Institute of Science, Bangalore. He is the interim secretary of the VLSI Society of India and was the program cochair of the Fifth In- ternational Conference on VLSl Design.

Send correspondence to the authors at CAD (VLSl) Group, Indian Telephone Indus- tries Ltd., Bangalore 560 016, India; email: raghu@itibang.ernet.in.

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